Semiconductor device with bump and chip stack package

Abstract

A semiconductor device includes a semiconductor chip, a sacrificial metal pattern, and a bump. The sacrificial metal pattern is disposed on the semiconductor chip, and the bump is disposed on the semiconductor chip and the sacrificial metal pattern. The sacrificial metal pattern includes a metal that is more anodic than a metal included in the bump.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, including but not limited to semiconductor devices including bumps and chip stack-up packages. Background Technology

[0002] Chip stack-up packaging is a type of semiconductor packaging that increases capacity and integration by vertically stacking multiple semiconductor chips. One type of chip stack-up packaging is a TSV stack-up package in which through-silicon vias (TSVs) are formed in the semiconductor chips and the upper and lower semiconductor chips are electrically connected using TSVs.

[0003] In TSV stack-up packaging, bumps are used to connect the TSV of the upper semiconductor chip and the TSV of the lower semiconductor chip.

[0004] TSV stacked packaging includes a substrate chip, multiple core chips stacked on the substrate chip, and a mold layer that encapsulates the substrate chip and the core chips. Summary of the Invention

[0005] According to one embodiment, a semiconductor device may include: a semiconductor chip; a sacrificial metal pattern disposed on the semiconductor chip; and a bump disposed on the semiconductor chip and the sacrificial metal pattern, wherein the sacrificial metal pattern comprises a metal that is more anodic than the metal included in the bump.

[0006] According to one embodiment, a chip stack-up package may include: a first semiconductor chip; a first sacrificial metal pattern disposed on the first semiconductor chip; a first bump disposed on the first semiconductor chip and the first sacrificial metal pattern; a second semiconductor chip; a second bump disposed below the second semiconductor chip and connected to the first bump; and a mold layer encapsulating the first semiconductor chip, the second semiconductor chip, the first bump, the second bump, and the first sacrificial metal pattern, wherein the first sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the first bump.

[0007] According to one embodiment, a chip stack-up package may include: a first semiconductor chip; a first bump disposed on the first semiconductor chip in a first region of the chip stack-up package; a second bump disposed on the first semiconductor chip in a second region surrounding the first region; a sacrificial metal pattern disposed between the first semiconductor chip and the second bump; a second semiconductor chip; a third bump disposed below the second semiconductor chip and connected to the first bump; a fourth bump disposed below the second semiconductor chip and connected to the second bump; and a mold layer encapsulating the first semiconductor chip, the second semiconductor chip, the first bump, the second bump, the third bump, the fourth bump, and the sacrificial metal pattern, wherein the sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the second bump.

[0008] According to one embodiment, a chip stack-up package may include: a first semiconductor chip and a second semiconductor chip; a plurality of first bumps disposed in a first region of the chip stack-up package and located between the first semiconductor chip and the second semiconductor chip; a plurality of second bumps disposed in a second region surrounding the first region and located between the first semiconductor chip and the second semiconductor chip; and a sacrificial metal pattern disposed on each of the plurality of second bumps; wherein the sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the plurality of second bumps. Attached Figure Description

[0009] Figure 1 and Figure 2 This is a cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 3 This is a cross-sectional view of a chip stacked package according to one embodiment of the present disclosure.

[0011] Figure 4 yes Figure 3 A magnified view of region A.

[0012] Figure 5 and Figure 6 This is a plan view showing a first sacrificial metal pattern according to one embodiment of the present disclosure.

[0013] Figure 7 This is a plan view showing a first sacrificial metal pattern and a first bump according to one embodiment of the present disclosure.

[0014] Figure 8This is a cross-sectional view showing a first sacrificial metal pattern and a first bump according to one embodiment of the present disclosure.

[0015] Figure 9 This is a plan view showing the first, second, and third regions of a chip stacked package according to one embodiment of the present disclosure.

[0016] Figure 10 This is a cross-sectional view of a chip stacked package according to one embodiment of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] Cross-shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating material associated with those areas.

[0019] When one component is marked "connected" to another component, these components can be connected directly or through an intermediate component between them. When two components are marked "directly connected," one component is directly connected to the other without any intermediate component between them.

[0020] When one element is identified as being "above", "below", or "under" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between them.

[0021] The use of terms such as “vertical,” “top,” “above,” “below,” “under,” “overlapping,” “upper,” “side,” “upper part,” “lower part,” “height,” and other terms that suggest relative spatial relationships or orientations are for descriptive or reference purposes only and are not intended to be limiting in any other way. Other spatial relationships or orientations not shown in the drawings or described in the specification are also possible within the scope of this disclosure.

[0022] The use of terms such as "first" and "second" to distinguish various components does not imply any size, order, priority, number, or importance of the components. For example, in one example, the first component may be named the second component, and in another example, the second component may be named the first component.

[0023] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0024] Figure 1 This is a cross-sectional view of a semiconductor device 10 according to one embodiment of the present disclosure.

[0025] Reference Figure 1 According to one embodiment of the present disclosure, a semiconductor device 10 includes a semiconductor chip 100, a sacrificial metal pattern 200, and a bump 300.

[0026] Semiconductor chip 100 includes a chip body 110, chip pads 120, and a protective layer 130. Chip body 110 includes an integrated circuit. The function of semiconductor chip 100 is implemented in the integrated circuit, which includes various components. Chip pads 120 are disposed on the upper surface of chip body 110 and connected to the integrated circuit.

[0027] A protective layer 130 is disposed on the upper surface of the chip body 110. The protective layer 130 covers the upper surface of the chip body 110. A hole H is formed in the protective layer 130, through which the chip pad 120 is exposed. The protective layer 130 includes a first insulating layer 131 and a second insulating layer 132. The first insulating layer 131 covers the upper surface of the chip body 110. The second insulating layer 132 is disposed on the first insulating layer 131. The first insulating layer 131 may include an oxide. The second insulating layer 132 may include a nitride. The oxide may include silicon oxide, and the nitride may include silicon nitride. Figure 1 In this case, the protective layer 130 is formed to include two insulating layers, but is not limited to this example, and may be a single insulating layer or a stacked structure including three or more insulating layers.

[0028] A base metal layer 500 is disposed on the chip pad 120 exposed through via H and on the protective layer 130 surrounding via H. The base metal layer 500 covers the chip pad 120 and the protective layer 130 beneath the sacrificial metal pattern 200 and bump 300. The base metal layer 500 is connected to the chip pad 120. The base metal layer 500 may include titanium.

[0029] A seed metal layer 600 is disposed on the base metal layer 500. The seed metal layer 600 is disposed between the sacrificial metal pattern 200 and the base metal layer 500, and between the bump 300 and the base metal layer 500. The seed metal layer 600 is connected to the chip pad 120 through the base metal layer 500. The seed metal layer 600 may include copper.

[0030] A sacrificial metal pattern 200 is disposed on the seed metal layer 600. An opening OP is formed in the sacrificial metal pattern 200. A portion of the seed metal layer 600 is exposed through the opening OP. The opening OP overlaps perpendicularly with the chip pad 120 and the protective layer 130 around the via H.

[0031] The sacrificial metal pattern 200 includes a metal with more anodic properties than the metal included in the bump 300. The bump 300 may include nickel (Ni). The sacrificial metal pattern 200 may include zinc (Zn). The bump 300 may be a nickel layer. The sacrificial metal pattern 200 may be a zinc layer. The sacrificial metal pattern 200 replaces or is etched before the bump 300, thereby inhibiting or preventing corrosion of the bump 300. The sacrificial metal pattern 200 includes a flange FS that protrudes beyond the side surface 300_SS of the bump 300. The flange FS of the sacrificial metal pattern 200 is not covered by the bump 300 but is exposed outside the bump 300.

[0032] Bumps 300 are disposed on the seed metal layer 600 exposed through the opening OP and on the sacrificial metal pattern 200 surrounding the opening OP. Bumps 300 fill the opening OP and cover the sacrificial metal pattern 200 surrounding the opening OP. Recesses RS are formed in the upper surface 300_TS of the bumps 300. The recesses RS overlap perpendicularly with the opening OP. The width of the recesses RS of the bumps 300 is narrower than the width of the opening OP of the sacrificial metal pattern 200. The bumps 300 are connected to a through electrode (not shown) via the seed metal layer 600 and the base metal layer 500.

[0033] Figure 2 This is a schematic cross-sectional view of a semiconductor device 10' according to one embodiment of the present disclosure.

[0034] Reference Figure 2 According to one embodiment of the present disclosure, a semiconductor device 10' includes a semiconductor chip 100', a sacrificial metal pattern 200', and a bump 300'.

[0035] Semiconductor chip 100' includes a chip body 110', a through electrode 150', and a protective layer 140'. Chip body 110' includes an integrated circuit. The function of semiconductor chip 100' is implemented in the integrated circuit, which includes various components.

[0036] A through electrode 150' extends vertically through the chip body 110'. The upper end of the through electrode 150' protrudes above the upper surface of the chip body 110'. The through electrode 150' is connected to the integrated circuit.

[0037] A protective layer 140' is disposed on the upper surface of the chip body 110'. The protective layer 140' covers the upper surface of the chip body 110'. The protective layer 140' extends around the outer surface of the upper end of the through electrode 150' protruding above the upper surface of the chip body 110'. The protective layer 140' may include an insulating material. The insulating material may include a nitride. The nitride may include silicon nitride.

[0038] A base metal layer 500' is disposed on the semiconductor chip 100'. The base metal layer 500' covers the through electrode 150' and the protective layer 140' beneath the sacrificial metal pattern 200' and bump 300'. The base metal layer 500' is connected to the through electrode 150'. The base metal layer 500' may include titanium.

[0039] A seed metal layer 600' is disposed on the base metal layer 500'. The seed metal layer 600' is disposed between the sacrificial metal pattern 200' and the base metal layer 500', and between the bump 300' and the base metal layer 500'. The seed metal layer 600' is connected to the through electrode 150' through the base metal layer 500'. The seed metal layer 600' may include copper.

[0040] A sacrificial metal pattern 200' is disposed on a seed metal layer 600'. An opening OP' is formed in the sacrificial metal pattern 200'. A portion of the seed metal layer 600' is exposed through the opening OP'. The opening OP' overlaps perpendicularly with the through electrode 150' and the protective layer 140' surrounding the through electrode 150'.

[0041] The sacrificial metal pattern 200' includes a metal with more anodic properties than the metal included in the bump 300'. The bump 300' may include nickel, and the sacrificial metal pattern 200' may include zinc. The bump 300' may be a nickel layer or a stack of nickel and gold layers, and the sacrificial metal pattern 200' may be a zinc layer.

[0042] The sacrificial metal pattern 200' replaces or is etched before the bump 300', thereby inhibiting or preventing the corrosion of the bump 300'. The flange FS of the sacrificial metal pattern 200' protrudes beyond the side surface of the bump 300'. The flange FS of the sacrificial metal pattern 200' is not covered by the bump 300', but is exposed outside the bump 300'.

[0043] Bumps 300' are disposed on the seed metal layer 600' exposed through the opening OP' and on the sacrificial metal pattern 200' surrounding the opening OP'. Bumps 300' fill the opening OP' and cover the sacrificial metal pattern 200' surrounding the opening OP'. Bumps 300' are connected to the through electrode 150' through the seed metal layer 600' and the base metal layer 500'.

[0044] A recess RS′ is formed in the upper surface 300_TS′ of the protrusion 300′. The recess RS′ overlaps perpendicularly with the opening OP′. The recess RS′ has a width narrower than the width of the opening OP′.

[0045] Figure 3 This is a schematic cross-sectional view of a chip stacked package 20 according to one embodiment of the present disclosure, and Figure 4 yes Figure 3 A magnified view of region A.

[0046] Reference Figure 3 and Figure 4 According to one embodiment of the present disclosure, a chip stacked package 20 includes a first semiconductor chip 100A, a second semiconductor chip 100B, and a third semiconductor chip 100C; a first sacrificial metal pattern 200A, a second sacrificial metal pattern 200B, a third sacrificial metal pattern 200C, and a fourth sacrificial metal pattern 200D; and a first bump 300A, a second bump 300B, a third bump 300C, and a fourth bump 300D. The chip stacked package 20 also includes a first connecting member 400A and a second connecting member 400B; a first base metal layer 500A, a second base metal layer 500B, a third base metal layer 500C, and a fourth base metal layer 500D; a first seed metal layer 600A, a second seed metal layer 600B, a third seed metal layer 600C, and a fourth seed metal layer 600D; a mold layer 700; and an external connecting member 800.

[0047] A second semiconductor chip 100B is stacked on top of a first semiconductor chip 100A, and a third semiconductor chip 100C is stacked on top of a second semiconductor chip 100B. Figure 3 and Figure 4 In this case, the number of stacked semiconductor chips is three, but this number can be two, four or more.

[0048] In one embodiment, the first semiconductor chip 100A may be a substrate die, the second semiconductor chip 100B may be a mid-core die, and the third semiconductor chip 100C may be a top-core die. Although Figure 3 and Figure 4 The diagram shows a core intermediate die, but two or more core intermediate dies may be stacked between the base die and the core top die.

[0049] The first semiconductor chip 100A includes a first chip body 110A, a first chip pad 120A, a first lower protective layer 130A, a first upper protective layer 140A, and a first through electrode 150A.

[0050] The first chip body 110A includes a first integrated circuit. The first integrated circuit can be implemented in various ways depending on the type of the first semiconductor chip 100A. In one embodiment, semiconductor chips 100B and 100C can be memory dies, while semiconductor chip 100A can be a logic die that controls the memory dies. The first integrated circuit includes separate elements that control the memory dies.

[0051] A first chip pad 120A is disposed below the lower surface of a first chip body 110A. The first chip pad 120A is connected to a first integrated circuit. A first lower protective layer 130A is disposed below the lower surface of the first chip body 110A. The first lower protective layer 130A covers the lower surface of the first chip body 110A. A first hole H1 is formed in the first lower protective layer 130A, through which the first chip pad 120A is exposed. The first lower protective layer 130A includes an insulating material. The insulating material may include oxides and / or nitrides.

[0052] The first through electrode 150A extends vertically through the first chip body 110A. The lower end of the first through electrode 150A is exposed through the lower surface of the first chip body 110A. The lower end of the first through electrode 150A is connected to the first chip pad 120A. The upper end of the first through electrode 150A protrudes above the upper surface of the first chip body 110A.

[0053] A first upper protective layer 140A is disposed on the upper surface of the first chip body 110A. The first upper protective layer 140A covers the upper surface of the first chip body 110A. The first upper protective layer 140A surrounds the outer surface of the upper end of the first through electrode 150A protruding above the upper surface of the first chip body 110A. The first upper protective layer 140A may include an insulating material. The insulating material may include a nitride.

[0054] A first base metal layer 500A is disposed on the first semiconductor chip 100A. The first base metal layer 500A covers the first through electrode 150A and the first upper protective layer 140A below the first sacrificial metal pattern 200A and the first bump 300A. The first base metal layer 500A is connected to the first through electrode 150A. The first base metal layer 500A may include titanium.

[0055] A first seed metal layer 600A is disposed on a first base metal layer 500A. The first seed metal layer 600A is located between the first sacrificial metal pattern 200A and the first base metal layer 500A, and between the first bump 300A and the first base metal layer 500A. The first seed metal layer 600A is connected to the first through electrode 150A through the first base metal layer 500A. The first seed metal layer 600A may include copper.

[0056] A first sacrificial metal pattern 200A is disposed on a first seed metal layer 600A. A first opening OP1 is formed in the first sacrificial metal pattern 200A. A portion of the first seed metal layer 600A is exposed through the first opening OP1. The first opening OP1 overlaps perpendicularly with the first through electrode 150A and the first upper protective layer 140A surrounding the first through electrode 150.

[0057] The first sacrificial metal pattern 200A includes a metal with more anodic properties than the metal included in the first bump 300A. The first bump 300A may include nickel, and the first sacrificial metal pattern 200A may include zinc. The first bump 300A may be a nickel layer or a stack of nickel and gold layers, and the first sacrificial metal pattern 200A may be a zinc layer. The first sacrificial metal pattern 200A is etched in place of or before the first bump 300A, thereby inhibiting or preventing corrosion of the first bump 300A. The flange of the first sacrificial metal pattern 200A protrudes beyond the side surface of the first bump 300A. The flange of the first sacrificial metal pattern 200A is not covered by the first bump 300A but is exposed outside the first bump 300A.

[0058] A first bump 300A is disposed on a first seed metal layer 600A exposed through a first opening OP1 and on a first sacrificial metal pattern 200A surrounding the first opening OP1. The first bump 300A fills the first opening OP1 and covers the first sacrificial metal pattern 200A surrounding the first opening OP1. A first recess RS1 is formed in the upper surface of the first bump 300A. The first recess RS1 overlaps perpendicularly with the first opening OP1 of the first sacrificial metal pattern 200A. The first recess RS1 has a width narrower than the width of the first opening OP1.

[0059] A first dummy bump (not shown) can be provided on the first semiconductor chip 100A. The first dummy bump can be formed during the formation of the first bump 300A. The first dummy bump can support the second semiconductor chip 100B to relieve stress on the first bump 300A. The first dummy bump may not be used for input and / or output electrical signals. No electrical signal may be applied to the first dummy bump. The first dummy bump may be electrically floating.

[0060] The sacrificial metal pattern may not be provided between the first dummy bump and the first semiconductor chip 100A. Since no electrical signal is applied to the dummy bump, corrosion of the first dummy bump will not cause electrical failure, therefore the dummy bump does not include a sacrificial metal pattern.

[0061] The second semiconductor chip 100B includes a second chip body 110B, a second chip pad 120B, a second lower protective layer 130B, a second upper protective layer 140B, and a second through electrode 150B.

[0062] The second chip body 110B includes a second integrated circuit. The second integrated circuit can be implemented in various ways depending on the type of the second semiconductor chip 100B. In one embodiment, the second semiconductor chip 100B is a memory die, and the second integrated circuit includes memory cells.

[0063] A second chip pad 120B is disposed below the lower surface of the second chip body 110B. The second chip pad 120B is electrically connected to the second integrated circuit. A second lower protective layer 130B is disposed below the lower surface of the second chip body 110B. The second lower protective layer 130B covers the lower surface of the second chip body 110B. A second hole H2 is formed in the second lower protective layer 130B, through which the second chip pad 120B is exposed. The second lower protective layer 130B includes an insulating material. The insulating material may include oxides and / or nitrides.

[0064] The second through electrode 150B extends vertically through the second chip body 110B. The lower end of the second through electrode 150B is exposed through the lower surface of the second chip body 110B. The lower end of the second through electrode 150B is connected to the second chip pad 120B. The upper end of the second through electrode 150B protrudes above the upper surface of the second chip body 110B.

[0065] A second upper protective layer 140B is disposed on the upper surface of the second chip body 110B. The second upper protective layer 140B covers the upper surface of the second chip body 110B. The second upper protective layer 140B surrounds the outer surface of the upper end of the second through electrode 150B protruding above the upper surface of the second chip body 110B. The second upper protective layer 140B may include an insulating material. The insulating material may include a nitride.

[0066] A second base metal layer 500B is disposed below the second chip pad 120B exposed through the second via H2 and the second lower protective layer 130B surrounding the second via H2. The second base metal layer 500B is disposed above the second sacrificial metal pattern 200B and the second bump 300B to cover the second chip pad 120B and the second lower protective layer 130B. The second base metal layer 500B is connected to the second chip pad 120B. The second base metal layer 500B may include titanium.

[0067] The second seed metal layer 600B is disposed below the second base metal layer 500B. The second seed metal layer 600B is disposed between the second sacrificial metal pattern 200B and the second base metal layer 500B, and between the second bump 300B and the second base metal layer 500B. The second seed metal layer 600B is connected to the second chip pad 120B through the second base metal layer 500B. The second seed metal layer 600B may include copper.

[0068] A second sacrificial metal pattern 200B is disposed below the second seed metal layer 600B. A second opening OP2 is formed in the second sacrificial metal pattern 200B. A portion of the second seed metal layer 600B is exposed through the second opening OP2. The second opening OP2 overlaps perpendicularly with the second chip pad 120B exposed through the second hole H2 and the second lower protective layer 130B surrounding the second hole H2.

[0069] The second sacrificial metal pattern 200B includes a metal with more anodic properties than the metal included in the second bump 300B. The second bump 300B may include nickel, and the second sacrificial metal pattern 200B may include zinc. The second bump 300B may be a nickel layer, and the second sacrificial metal pattern 200B may be a zinc layer. The second sacrificial metal pattern 200B is etched in place of or before the second bump 300B, thereby inhibiting or preventing corrosion of the second bump 300B. The flange of the second sacrificial metal pattern 200B protrudes beyond the side surface of the second bump 300B. The flange of the second sacrificial metal pattern 200B is not covered by the second bump 300B but is exposed outside the second bump 300B.

[0070] A second bump 300B is disposed below the second seed metal layer 600B exposed through the second opening OP2 and below the second sacrificial metal pattern 200B. The second bump 300B fills the second opening OP2 and covers the second sacrificial metal pattern 200B surrounding the second opening OP2. A second recess RS2 is formed in the lower surface of the second bump 300B. The second recess RS2 overlaps perpendicularly with the second opening OP2. The second recess RS2 has a width narrower than the width of the second opening OP2. The second bump 300B is connected to the second chip pad 120B through the second seed metal layer 600B and the second base metal layer 500B.

[0071] The first connecting member 400A is disposed below the second protrusion 300B. The first connecting member 400A may be a solder layer. The solder layer may include tin (Sn) or a tin-silver (Sn-Ag) alloy.

[0072] A first connecting member 400A is engaged with a first bump 300A. The engagement process may include: applying flux to the first connecting member 400A; temporarily attaching the first connecting member 400A to the first bump 300A; removing the flux; and fastening the first connecting member 400A to the first bump 300A by a reflow and cooling process. A second bump 300B is connected to the first bump 300A via the first connecting member 400A.

[0073] A second dummy bump (not shown) can be provided under the second semiconductor chip 100B. The second dummy bump can be formed during the formation of the second bump 300B. The second dummy bump can support the second semiconductor chip 100B to reduce stress on the second bump 300B. The second dummy bump may not be used for input and / or output electrical signals. No electrical signal may be applied to the second dummy bump. The second dummy bump may be electrically floating.

[0074] The sacrificial metal pattern may not be provided between the second dummy bump and the second semiconductor chip 100B. Since no electrical signal is applied to the dummy bump, corrosion of the second dummy bump will not cause electrical failure, therefore the dummy bump does not include a sacrificial metal pattern.

[0075] A third base metal layer 500C is disposed on the second semiconductor chip 100B. The third base metal layer 500C is disposed beneath the third sacrificial metal pattern 200C and the third bump 300C, and covers the second upper protective layer 140B and the second through electrode 150B. The third base metal layer 500C is connected to the second through electrode 150B. The third base metal layer 500C may include titanium.

[0076] A third seed metal layer 600C is disposed on the third base metal layer 500C. The third seed metal layer 600C is located between the third sacrificial metal pattern 200C and the third base metal layer 500C, and between the third bump 300C and the third base metal layer 500C. The third seed metal layer 600C is connected to the second through electrode 150B via the third base metal layer 500C. The third seed metal layer 600C may include copper.

[0077] A third sacrificial metal pattern 200C is disposed on a third seed metal layer 600C. A third opening OP3 is formed in the third sacrificial metal pattern 200C. A portion of the third seed metal layer 600C is exposed through the third opening OP3. The third opening OP3 overlaps perpendicularly with the second upper protective layer 140B surrounding the second through electrode 150B and the second through electrode 150.

[0078] The third sacrificial metal pattern 200C includes a metal with more anodic properties than the metal included in the third bump 300C. The third bump 300C may include nickel, and the third sacrificial metal pattern 200C may include zinc. The third bump 300C may be a nickel layer or a stack of nickel and gold layers, and the third sacrificial metal pattern 200C may be a zinc layer. The third sacrificial metal pattern 200C replaces or is etched before the third bump 300C, thereby inhibiting or preventing the corrosion of the third bump 300C. The flange of the third sacrificial metal pattern 200C protrudes beyond the side surface of the third bump 300C. The flange of the third sacrificial metal pattern 200C is not covered by the third bump 300C but is exposed to the outside of the third bump 300C.

[0079] A third bump 300C is disposed on the third seed metal layer 600C exposed through the third opening OP3 and on the third sacrificial metal pattern 200C surrounding the third opening OP3. The third bump 300C fills the third opening OP3 and covers the third sacrificial metal pattern 200C surrounding the third opening OP3. The third bump 300C is connected to the second through electrode 150B through the third seed metal layer 600C and the third base metal layer 500C.

[0080] A third recess RS3 is formed in the upper surface of the third protrusion 300C. The third recess RS3 overlaps perpendicularly with the third opening OP3 of the third sacrificial metal pattern 200C. The third recess RS3 has a width narrower than the width of the third opening OP3.

[0081] A third dummy bump (not shown) may be provided on the second semiconductor chip 100B. The third dummy bump may be formed during the formation of the third bump 300C. The third dummy bump may support the third semiconductor chip 100C to reduce stress on the third bump 300C. The third dummy bump may not be used for input and / or output electrical signals. No electrical signal may be applied to the third dummy bump. The third dummy bump may be electrically floating.

[0082] The sacrificial metal pattern may not be provided between the third dummy bump and the second semiconductor chip 100B. Because no electrical signal is applied to the dummy bump, corrosion of the third dummy bump will not cause electrical failure. Therefore, the sacrificial metal pattern is not included on the third dummy bump.

[0083] The third semiconductor chip 100C includes a third chip body 110C, a third chip pad 120C, and a third lower protective layer 130C.

[0084] The third chip body 110C includes a third integrated circuit. The third integrated circuit can be implemented in various ways depending on the type of the third semiconductor chip 100C. In one embodiment, the third semiconductor chip 100C may be a memory die, and the third integrated circuit may include memory cells. The third chip body 110C may have a thickness different from that of the second chip body 110B. The third chip body 110C may be thicker than the second chip body 110B.

[0085] A third chip pad 120C is disposed below the lower surface of the third chip body 110C. The third chip pad 120C is connected to a third integrated circuit. A third lower protective layer 130C is disposed below the lower surface of the third chip body 110C. The third lower protective layer 130C covers the lower surface of the third chip body 110C. A third via H3 is formed in the third lower protective layer 130C, through which the third chip pad 120C is exposed. The third lower protective layer 130C includes an insulating material. The insulating material may include oxides and / or nitrides.

[0086] A fourth base metal layer 500D is disposed beneath the third chip pad 120C exposed through the fourth via H4 and the third lower protective layer 130C surrounding the fourth via H4. The fourth base metal layer 500D covers the third chip pad 120C and the third lower protective layer 130C from above the fourth sacrificial metal pattern 200D and the fourth bump 300D. The fourth base metal layer 500D may include titanium. The fourth base metal layer 500D is connected to the third chip pad 120C.

[0087] A fourth seed metal layer 600D is disposed below the fourth base metal layer 500D. The fourth seed metal layer 600D is located between the fourth sacrificial metal pattern 200D and the fourth base metal layer 500D, and between the fourth bump 300D and the fourth base metal layer 500D. The fourth seed metal layer 600D is connected to the third chip pad 120C via the fourth base metal layer 500D. The fourth seed metal layer 600D may include copper.

[0088] A fourth sacrificial metal pattern 200D is disposed below a fourth seed metal layer 600D. A fourth opening OP4 is formed in the fourth sacrificial metal pattern 200D. A portion of the fourth seed metal layer 600D is exposed through the fourth opening OP4. The fourth opening OP4 overlaps perpendicularly with the third chip pad 120C exposed through the third via H3 and the third lower protective layer 130C surrounding the third via H3.

[0089] The fourth sacrificial metal pattern 200D includes a metal with more anodic properties than the metal included in the fourth bump 300D. The fourth bump 300D may include nickel, and the fourth sacrificial metal pattern 200D may include zinc. The fourth bump 300D may be a nickel layer, and the fourth sacrificial metal pattern 200D may be a zinc layer. The fourth sacrificial metal pattern 200D is etched in place of or prior to the fourth bump 300D, thereby inhibiting or preventing corrosion of the fourth bump 300D. The flange of the fourth sacrificial metal pattern 200D protrudes beyond the side surface of the fourth bump 300D. The flange of the fourth sacrificial metal pattern 200D is not covered by the fourth bump 300D but is exposed to the outside of the fourth bump 300D.

[0090] A fourth bump 300D is disposed below the fourth seed metal layer 600D exposed through the fourth opening OP4 and below the fourth sacrificial metal pattern 200D. The fourth bump 300D fills the fourth opening OP4 and covers the fourth sacrificial metal pattern 200D surrounding the fourth opening OP4. A fourth recess RS4 is formed in the lower surface of the fourth bump 300D. The fourth recess RS4 overlaps perpendicularly with the fourth opening OP4. The fourth recess RS4 has a width narrower than the width of the fourth opening OP4. The fourth bump 300D is connected to the third chip pad 120C through the fourth seed metal layer 600D and the fourth base metal layer 500D.

[0091] A fourth dummy bump (not shown) may be provided under the third semiconductor chip 100C. The fourth dummy bump may be formed during the formation of the fourth bump 300D. The fourth dummy bump may support the third semiconductor chip 100C to reduce stress on the fourth bump 300D. The fourth dummy bump may not be used for input and / or output electrical signals. No electrical signal may be applied to the fourth dummy bump. The fourth dummy bump may be electrically floating.

[0092] The sacrificial metal pattern may not be provided between the fourth dummy bump and the third semiconductor chip 100C. Because no electrical signal is applied to the dummy bump, corrosion of the fourth dummy bump will not cause electrical failure. Therefore, the sacrificial metal pattern is not included on the fourth dummy bump.

[0093] The second connecting member 400B is disposed below the fourth protrusion 300D. The second connecting member 400B may be a solder layer. The solder layer may include tin (Sn) or a tin-silver (Sn-Ag) alloy.

[0094] The second connecting member 400B is engaged to the third protrusion 300C. The engagement process may include: applying flux to the second connecting member 400B; temporarily attaching the second connecting member 400B to the third protrusion 300C; removing the flux; and fastening the second connecting member 400B to the third protrusion 300C by a reflow and cooling process. The fourth protrusion 300D is connected to the third protrusion 300C via the second connecting member 400B.

[0095] The mold layer 700 encapsulates semiconductor chips 100A, 100B, and 100C, sacrificial metal patterns 200A, 200B, 200C, and 200D, and bumps 300A, 300B, 300C, and 300D. The mold layer 700 encapsulates these components to protect them from the influence of the external environment.

[0096] A mold layer 700 is disposed on the first semiconductor chip 100A and covers the side surfaces of semiconductor chips 100B and 100C. The upper surface of the third semiconductor chip 100C is exposed through the mold layer 700. The upper surface of the mold layer 700 may be coplanar with the upper surface of the third semiconductor chip 100C. Because the upper surface of the third semiconductor chip 100C is not covered by the mold layer 700, the heat generated during the operation of semiconductor chips 100A, 100B, and 100C can be released to the outside of the chip stack package 20 through the upper surface of the third semiconductor chip 100C without being affected by the mold layer 700.

[0097] A mold layer 700 extends to fill the space between semiconductor chips 100A, 100B, and 100C. The mold layer 700 may have a molded underfill (MUF) structure that fills the space between semiconductor chips 100A, 100B, and 100C. In another example, the space between semiconductor chips 100A, 100B, and 100C may be filled with a separate underfill material different from that of the mold layer 700. In another example, adhesive layers may be provided between the first semiconductor chip 100A and the second semiconductor chip 100B, and between the second semiconductor chip 100B and the third semiconductor chip 100C, thereby attaching the semiconductor chips 100A, 100B, and 100C.

[0098] The mold layer 700 can be formed using a molding process that utilizes a liquid encapsulation material. The encapsulation material may include epoxy molding compound (EMC).

[0099] An external connection member 800 is disposed below the first semiconductor chip 100A. The external connection member 800 is disposed below a first chip pad 120A exposed through a first hole H1 and below a first lower protective layer 130A surrounding the first hole H1. The external connection member 800 is connected to the first chip pad 120A. The external connection member 800 includes a metal pillar 810 and a solder layer 820 below the metal pillar 810. The metal pillar 810 may include copper. The solder layer 820 may include tin or a tin-silver alloy.

[0100] Figure 5 and Figure 6 This is a plan view showing a first sacrificial metal pattern according to an embodiment of the present disclosure.

[0101] Reference Figure 5 Multiple first sacrificial metal patterns 200A are arranged along the X and Y directions. The first sacrificial metal patterns 200A are repeatedly arranged along the X and Y directions according to a first spacing P1. The first sacrificial metal pattern 200A has a first opening OP1 formed at the center of the first sacrificial metal pattern 200A in a ring-shaped structure or annular structure.

[0102] Reference Figure 6 The first sacrificial metal pattern 200A' has a first opening OP1' formed at the center of a rectangular frame structure. When the first sacrificial metal pattern 200A' is configured as a rectangular frame structure, the first sacrificial metal pattern 200A' has a larger... Figure 5 The first sacrificial metal pattern 200A has a larger planar area and a larger volume.

[0103] Figure 7 This is a plan view showing a first sacrificial metal pattern and a first bump according to an embodiment of the present disclosure, and Figure 8 This is a cross-sectional view showing a first sacrificial metal pattern and a first bump according to one embodiment of the present disclosure. Figure 8 It shows along Figure 7 The cross-sectional view taken by line B-B' in the diagram.

[0104] Reference Figure 7 and Figure 8 The first sacrificial metal pattern 200A'' has an inner surface 200A_SS1'' and an outer surface 200A_SS2'' exposed through a first opening OP1''. The first opening OP1'' opens to the outer surface 200A_SS2'' of the first sacrificial metal pattern 200A''. The first sacrificial metal pattern 200A'' has an open annular structure or a partially annular structure.

[0105] The first recess RS1'' is formed on the upper surface 300A_TS'' of the first protrusion 300A'' and overlaps perpendicularly with the first opening OP1''. The first recess RS1'' opens to the side surface 300A_SS'' of the first protrusion 300A''. Because the first recess RS1'' opens to the side surface 300A_SS'' of the first protrusion 300A'', when the first connecting member 400A ( Figure 3 During the process of temporarily attaching the first protrusion 300A' to the first protrusion 300A'', the flux applied to the first connecting member flows through the first recess RS1'' to the side surface 300A_SS'' of the first protrusion 300A''. Therefore, the capture and retention of flux on the upper surface 300A_TS'' of the first protrusion 300A'' can be suppressed or prevented, and the formation of voids caused by residual flux can also be suppressed or prevented.

[0106] Reference Figures 5 to 8 The description of the first sacrificial metal pattern is applicable to Figure 3 The sacrificial metal patterns 200B, 200C, and 200D are shown in the reference. Figures 5 to 8 The description of the first bump is applicable to Figure 3 The bumps in the model are 300B, 300C, and 300D.

[0107] Figure 9 This is a plan view showing a chip stacked package 20' according to one embodiment of the present disclosure, and Figure 10 Is it through Figure 9 A cross-sectional view of the chip stacked package 20' in the first region R1.

[0108] Reference Figure 9 and Figure 10 The chip stacked package 20' includes a first region R1, a second region R2, and a third region R3.

[0109] The second region R2 surrounds the edge of the first region R1, and the third region R3 surrounds the edge of the second region R2. The second region R2 is located between the first region R1 and the third region R3.

[0110] A first semiconductor chip 100A and a mold layer 700 are disposed in a first region R1, a second region R2, and a third region R3. Semiconductor chips 100B and 100C are disposed in the first region R1 and the second region R2.

[0111] The first bumps 300Aa and 300Ab include a first center bump 300Aa disposed in the first region R1 and a first edge bump 300Ab disposed in the second region R2. A first sacrificial metal pattern 200A is disposed between the first edge bump 300Ab and the first semiconductor chip 100A. No sacrificial metal pattern is disposed between the first center bump 300Aa and the first semiconductor chip 100A.

[0112] The second bumps 300Ba and 300Bb include a second center bump 300Ba disposed in the first region R1 and a second edge bump 300Bb disposed in the second region R2. A second sacrificial metal pattern 200B is disposed between the second edge bump 300Bb and the second semiconductor chip 100B. No sacrificial metal pattern is disposed between the second center bump 300Ba and the second semiconductor chip 100B.

[0113] The third bumps 300Ca and 300Cb include a third center bump 300Ca disposed in the first region R1 and a third edge bump 300Cb disposed in the second region R2. A third sacrificial metal pattern 200C is disposed between the third edge bump 300Cb and the second semiconductor chip 100B. No sacrificial metal pattern is disposed between the third center bump 300Ca and the second semiconductor chip 100B.

[0114] The fourth bumps 300Da and 300Db include a fourth center bump 300Da disposed in the first region R1 and a fourth edge bump 300Db disposed in the second region R2. A fourth sacrificial metal pattern 200D is disposed between the fourth edge bump 300Db and the third semiconductor chip 100C. No sacrificial metal pattern is disposed between the fourth center bump 300Da and the third semiconductor chip 100C.

[0115] Moisture can penetrate from the outside into the chip stack package 20' through the mold layer 700. Therefore, the edge bumps 300Ab, 300Bb, 300Cb, and 300Db located in the second region R2 are more susceptible to corrosion than the center bumps 300Aa, 300Ba, 300Ca, and 300Da located in the first region R1. In this example, sacrificial metal patterns are included for the more easily corroded edge bumps 300Ab, 300Bb, 300Cb, and 300Db, while sacrificial metal patterns are not included for the less likely to corrode center bumps 300Aa, 300Ba, 300Ca, and 300D. Therefore, the plurality of first bumps of the chip stack package 20' are formed with sacrificial metal patterns, while the plurality of second bumps of the chip stack package 20' are formed without sacrificial metal patterns. The plurality of first bumps are disposed around the plurality of second bumps.

[0116] Although detailed embodiments of the present disclosure have been described herein, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments are possible without departing from the scope and technical concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the embodiments described above. All variations within the meaning and equivalent scope of the claims are included within its scope.

[0117] Cross-reference to related applications

[0118] This application claims priority to Korean Patent Application No. 10-2025-0057938, filed with the Korean Intellectual Property Office on May 2, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: Semiconductor chips; A sacrificial metal pattern is disposed on the semiconductor chip; as well as A bump is provided on the semiconductor chip and the sacrificial metal pattern; The sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the bump.

2. The semiconductor device according to claim 1, wherein, The bump comprises nickel (Ni), and the sacrificial metal pattern comprises zinc (Zn).

3. The semiconductor device according to claim 1, in, An opening is formed in the sacrificial metal pattern; and The bump fills the opening formed in the sacrificial metal pattern and covers the sacrificial metal pattern around the opening.

4. The semiconductor device according to claim 3, wherein, The opening formed in the sacrificial metal pattern leads to the outer surface of the sacrificial metal pattern.

5. The semiconductor device according to claim 3, wherein, A recess is formed in the upper surface of the protrusion, the recess overlapping perpendicularly with the opening formed in the sacrificial metal pattern.

6. The semiconductor device according to claim 5, wherein, The recess formed in the protrusion has a width narrower than the width of the opening formed in the sacrificial metal pattern.

7. The semiconductor device according to claim 5, wherein, The recess formed in the protrusion leads to the side surface of the protrusion.

8. The semiconductor device according to claim 1, wherein, The flange of the sacrificial metal pattern protrudes beyond the side surface of the bump.

9. The semiconductor device of claim 1, further comprising: A base metal layer is disposed beneath the bumps and the sacrificial metal pattern to cover the semiconductor chip; as well as A seed metal layer is disposed between the sacrificial metal pattern and the base metal layer, and between the bump and the base metal layer.

10. The semiconductor device according to claim 9, wherein, The seed metal layer comprises copper, and the base metal layer comprises titanium.

11. A chip stacked package, the chip stacked package comprising: First semiconductor chip; A first sacrificial metal pattern is disposed on the first semiconductor chip; A first bump is disposed on the first semiconductor chip and the first sacrificial metal pattern; Second semiconductor chip; The second bump is disposed below the second semiconductor chip and connected to the first bump; as well as A mold layer that encapsulates the first semiconductor chip, the second semiconductor chip, the first bump, the second bump, and the first sacrificial metal pattern; The first sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the first bump.

12. The chip stacked package of claim 11, further comprising a second sacrificial metal pattern disposed between the second semiconductor chip and the second bump; and in, The second sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the second bump.

13. The chip stacking package according to claim 11, in, An opening is formed in the first sacrificial metal pattern; and The first bump fills the opening formed in the first sacrificial metal pattern and covers the first sacrificial metal pattern around the opening.

14. The chip stacked packaging according to claim 13, wherein, The opening formed in the first sacrificial metal pattern leads to the outer surface of the first sacrificial metal pattern.

15. The chip stacked package according to claim 13, wherein, A recess is formed in the upper surface of the protrusion, the recess overlapping perpendicularly with the opening formed in the first sacrificial metal pattern.

16. The chip stacked package according to claim 15, wherein, The recess formed in the first protrusion has a width narrower than the width of the opening formed in the first sacrificial metal pattern.

17. The chip stacked package according to claim 15, wherein, The recess formed in the first protrusion leads to the side surface of the first protrusion.

18. The chip stacked package according to claim 11, wherein, The flange of the first sacrificial metal pattern protrudes beyond the side surface of the first bump.

19. A chip stacked package, the chip stacked package comprising: First semiconductor chip and second semiconductor chip; A plurality of first bumps are disposed in a first region of the chip stacked package and located between the first semiconductor chip and the second semiconductor chip; A plurality of second bumps are disposed in a second region surrounding the first region and located between the first semiconductor chip and the second semiconductor chip; as well as A sacrificial metal pattern is disposed on each of the plurality of second bumps; The sacrificial metal pattern comprises a metal with more anodic properties than the metal included in the plurality of second bumps.

20. The chip stacked package according to claim 19, wherein, The plurality of first bumps are formed without a sacrificial metal pattern on the plurality of first bumps.

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