Semiconductor device

Abstract

The present disclosure aims to provide a semiconductor device capable of improving the wire peeling resistance of a gate pad. A semiconductor device (101) includes: a drift layer (4); a base layer (3) formed on a surface layer of the drift layer (4); a source layer (2) formed on a surface layer of the base layer (3); a gate electrode (6) disposed to face a channel region of the base layer (3) sandwiched by the source layer (2) and the drift layer (4) through a gate oxide film (7); an interlayer insulating film (5) covering the gate electrode (6); a source pad (1) in electrical contact with the source layer (2) and insulated from the gate electrode (6) through the interlayer insulating film (5); a gate wiring (8) formed on the drift layer (4) not overlapping the source pad (1) in plan view through an insulating layer (10); and a gate pad (11) formed on the gate wiring (8) through an insulating layer (9). The pitch of the concave-convex shape of the upper surface of the gate pad (11) is different from the concave-convex shape of the lower surface of the gate pad (11).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] A MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) has a semiconductor substrate including a drift layer, and source pads and gate pads formed on the semiconductor substrate. The source pads are the main electrode pads.

[0003] Directly below the source pads, a base layer and a source layer are formed on the surface of the drift layer. The base layer sandwiched between the source layer and the drift layer forms the channel region. A gate electrode is formed, sandwiched between the gate insulating film and the channel region, separated by a gate oxide film. An interlayer insulating film is formed on the semiconductor substrate to cover the gate electrode and the gate oxide film. Since the interlayer insulating film is formed only at the location covering the gate electrode, a step is formed between the upper surface of the interlayer insulating film and the upper surface of the semiconductor substrate where no interlayer insulating film is formed.

[0004] Patent document 1 discloses an electrode pad formed on an interlayer insulating film. The upper surface of the electrode pad is formed with an uneven shape that reflects the step between the interlayer insulating film and the upper surface of the semiconductor substrate.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2002-305217 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] Source electrodes (source pads) are formed on the source layer and the interlayer insulating film. An uneven shape reflecting the step between the interlayer insulating film and the upper surface of the semiconductor substrate is formed on the upper surface of the source pad.

[0010] Therefore, during wire bonding of the source pads, the bonding wire connected to the source pads contacts multiple protrusions on the steps of the upper surface of the source pads. The energy of the ultrasonic bonding is locally concentrated on the smaller protrusions, thereby breaking down the oxide film of the source pads and exposing the clean surface, allowing the bonding process to begin earlier at multiple locations.

[0011] On the other hand, an insulating film is formed directly below the gate pads on a drift layer or a flat P layer, and gate wiring is formed on the insulating film. An insulating film is formed on the gate wiring, and a gate pad is formed on the insulating film.

[0012] Typically, because the gate wiring is flat, the insulating film formed on the gate wiring is also flat. Therefore, the upper surface of the gate pad reflects the shape of the insulating film directly beneath the gate pad and is flat.

[0013] Therefore, when wire bonding the gate pads, it is difficult to generate the localized energy concentration of ultrasonic bonding as described for the source pads. Consequently, if the source and gate pads are wire bonded simultaneously with the same lead diameter and the same bonding conditions, the wire bonding process allowance for the gate pads becomes narrower, leading to the problem of easy wire stripping.

[0014] As described above, MOSFETs have been used as an example, but the same problem can occur in other semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors).

[0015] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device that improves the peel resistance of bonding lines in gate pads.

[0016] Technical means for solving technical problems

[0017] The semiconductor device disclosed herein includes: a drift layer of a first conductivity type; a base layer of a second conductivity type formed on the surface of the drift layer; a carrier supply layer of the first conductivity type formed on the surface of the base layer; a gate electrode configured to face a channel region in the base layer sandwiched between the carrier supply layer and the drift layer, separated by a gate oxide film; an interlayer insulating film covering the gate electrode; a main electrode pad electrically contacting the carrier supply layer and insulated from the gate electrode by the interlayer insulating film; a gate wiring formed on the drift layer, which does not overlap with the main electrode pad when viewed from above, separated by an insulating layer; and a gate pad formed on the gate wiring separated by an insulating layer, wherein at least the upper surface of the gate pad has an uneven shape, and when the lower surface of the gate pad has an uneven shape, the spacing or phase of the uneven shape on the upper surface of the gate pad is different from the uneven shape on the lower surface of the gate pad.

[0018] Invention Effects

[0019] In the gate pad of the semiconductor device disclosed herein, the lower surface does not have an uneven shape but the upper surface has an uneven shape, or the lower surface has an uneven shape but the upper surface has an uneven shape with a spacing or phase different from the uneven shape on the lower surface. Therefore, the uneven shape on the upper surface of the gate pad can be made to approximate the uneven shape on the upper surface of the main electrode pad portion. As a result, process allowance for wire bonding can be ensured, and peeling of the bonding wires at the gate pad can be suppressed. Brief Description of the Drawings

[0020] Figure 1 is a top view of a semiconductor device.

[0021] Figure 2 is a cross-sectional view including a source pad of the semiconductor device according to Embodiment 1.

[0022] Figure 3 is a cross-sectional view including a gate pad of the semiconductor device according to Embodiment 1.

[0023] Figure 4 is a diagram showing a contact surface between a bonding wire and a gate pad.

[0024] Figure 5 is a diagram showing a contact surface between a bonding wire and a gate pad.

[0025] Figure 6 is a cross-sectional view including a gate pad of the semiconductor device according to Embodiment 2.

[0026] Figure 7 is a perspective view showing a gate pad of the semiconductor device according to Embodiment 3.

[0027] Figure 8 is a cross-sectional view including a source pad of the semiconductor device according to Embodiment 4.

[0028] Figure 9 is a cross-sectional view including a gate pad of the semiconductor device according to Embodiment 4. Detailed Description of the Embodiments

[0029] In this specification, regarding the conductivity types of the semiconductor layers, the first conductivity type is defined as n-type and the second conductivity type is defined as p-type, but they may also be reversed. That is, the first conductivity type may be defined as p-type, and the second conductivity type may be defined as n-type.

[0030] <A. Embodiment 1>

[0031] Figure 1 is a top view of the semiconductor device 101 according to Embodiment 1. The semiconductor device 101 includes a source pad 1, a gate pad 11, an edge termination 12, a current sensing pad 13, and a temperature sensing pad 14.

[0032] In the following description, the semiconductor device 101 will be described as a MOSFET, but the semiconductor device 101 may also be another semiconductor device such as an IGBT. When the semiconductor device 101 is an IGBT, Figure 1The source pad 1 shown is replaced with the emitter pad, and the source layer 2 is replaced with the emitter layer. Here, the source pad and emitter pad are an example of the main electrode pad, and the source layer and emitter layer are an example of the carrier supply layer.

[0033] Figure 2 This is a cross-sectional view of the semiconductor device 101 including the source pad 1. The source pad 1 of the semiconductor device 101 and the structure directly below it are referred to as the source pad section. Figure 3 This is a cross-sectional view of the semiconductor device 101 including the gate pad 11. The gate pad 11 of the semiconductor device 101 and the structure directly below it are referred to as the gate pad portion.

[0034] The following is for reference Figure 2 The structure of the source pad section is described below. In the source pad section, the semiconductor device 101 includes an n-type drift layer 4, a p-type base layer 3, an n-type source layer 2, a gate oxide film 7, a gate electrode 6, an interlayer insulating film 5, and a source pad 1. The source pad 1 is made of aluminum, for example, but may also be made of other materials such as copper or an alloy of gold and nickel.

[0035] A base layer 3 is formed on the surface of the drift layer 4. A source layer 2 is formed on the surface of the base layer 3. Multiple trenches are formed, penetrating the source layer 2 and the base layer 3 and reaching the drift layer 4. A gate electrode 6 is buried inside these trenches via a gate oxide film 7. The region in the base layer 3 sandwiched between the source layer 2 and the drift layer 4 that contacts the gate oxide film 7 is the channel region. The gate electrode 6 is opposite the channel region via the gate oxide film 7.

[0036] An interlayer insulating film 5 is disposed on the gate electrode 6. A source pad 1 is disposed on the interlayer insulating film 5. A contact hole is formed on the interlayer insulating film 5 to expose the source layer 2, and the source pad 1 makes electrical contact with the source layer 2 through the contact hole. The upper surface of the source layer 2 exposed from the contact hole of the interlayer insulating film 5 has a step with the upper surface of the interlayer insulating film 5. Since the source pad 1 is formed along this step, the lower surface of the source pad 1 must have an uneven shape.

[0037] Furthermore, since the source pad 1 is typically formed by sputtering, the steps of the substrate (source layer 2 and interlayer insulating film 5) are also reflected on the upper surface of the source pad 1. That is, the upper surface of the source pad 1 also has an uneven shape.

[0038] Next, refer to Figure 3 The structure of the gate pad portion is described below. In the gate pad portion, the semiconductor device 101 includes an n-type drift layer 4, a gate wiring 8, an insulating layer 9, an insulating layer 10, and a gate pad 11. The drift layer 4 is commonly disposed in both the source pad portion and the gate pad portion. The gate pad 11 is made of aluminum, for example, but may also be made of other materials.

[0039] On the drift layer 4, a gate wiring 8 is provided across an insulating layer 10. On the gate wiring 8, a gate pad 11 is provided across an insulating layer 9. The gate wiring 8 is not a flat plate, but a wave. In other words, the upper and lower surfaces of the gate wiring 8 have uneven shapes. Reflecting the uneven shape of the upper surface of the gate wiring 8, the upper surface of the insulating layer 9 also has an uneven shape.

[0040] The gate pad 11 formed on the insulating layer 9 reflects the uneven shape of the insulating layer 9 as a substrate, and has an uneven shape on its lower surface.

[0041] At least one of the spacing and phase of the uneven shape on the upper surface of the gate pad 11 differs from that on the lower surface. Similar to the source pad 1, the gate pad 11 is typically formed by sputtering; therefore, if left as is, the uneven shape on the upper surface of the gate pad 11 has the same phase and spacing as the uneven shape on the lower surface. Therefore, by patterning the upper surface of the sputtered gate pad 11, it is possible to obtain an uneven shape on the upper surface of the gate pad 11 where at least one of the spacing and phase differs from that on the lower surface.

[0042] Alternatively, a bump-mitigation layer can be formed on the insulating layer 9, and a gate pad 11 can be formed on the bump-mitigation layer, such that the bumps on the upper surface of the gate pad 11 are smaller than those on the lower surface. The bump-mitigation layer is a conformal film formed with a uniform film thickness along the bumps of the insulating layer 9, such as a barrier metal. The bump-mitigation layer is formed with a uniform film thickness along the bumps of the insulating layer 9. Therefore, the size of the depression on the upper surface of the bump-mitigation layer is reduced by an amount equivalent to the film thickness of the bump-mitigation layer. As a result, the depression on the upper surface of the gate pad 11 is smaller.

[0043] In addition, Figure 2 and Figure 3 The diagrams of the n-type semiconductor substrate supporting the drift layer 4 and the drain electrode formed on the back side of the semiconductor substrate are omitted.

[0044] The amplitude of the irregularity formed on the upper surface of the gate pad 11 is greater than the amplitude naturally generated by the die on the gate pad 11. Here, the amplitude of the irregularity refers to the height difference between the bottom surface of the recess and the top surface of the convex portion. For example, the amplitude of the irregularity formed on the upper surface of the gate pad 11 is 10 nm or more.

[0045] The unevenness of the upper surface of the gate pad 11 is preferably configured in a certain regularity. Figure 4 and Figure 5The wire bonding area on the upper surface of the gate pad 11 is shown. In these figures, the elliptical outline represents the contour of the contact surface of the bonding wire. Additionally, the small black quadrilaterals represent the protrusions on the upper surface of the gate pad 11.

[0046] like Figure 4 As shown, the protrusions can be configured in a concentric circle shape. Additionally, as... Figure 5 As shown, the protrusions can be configured in a grid pattern. Furthermore, the density of the protrusions can be higher at the center of the contact area with the joint line and lower at the outer periphery.

[0047] The upper and lower surfaces of the current sensing pad 13 and the temperature sensing pad 14 have the same shape as the upper and lower surfaces of the gate pad 11. However, the current sensing pad 13 and the temperature sensing pad 14 are not essential structures for the semiconductor device 101.

[0048] Semiconductor device 101 includes: a drift layer 4 of a first conductivity type; a base layer 3 of a second conductivity type formed on the surface of the drift layer 4; a source layer 2 of a first conductivity type formed on the surface of the base layer 3; a gate electrode 6 disposed opposite to a channel region in the base layer 3 sandwiched between the source layer 2 and the drift layer 4, separated by a gate oxide film 7; an interlayer insulating film 5 covering the gate electrode 6; a source pad 1 electrically contacting the source layer 2 and insulated from the gate electrode 6 by the interlayer insulating film 5; a gate wiring 8 formed on the drift layer 4, separated by an insulating layer 10, which does not overlap with the source pad 1 when viewed from above; and a gate pad 11 formed on the gate wiring 8 separated by an insulating layer 9. The gate pad 11 has an uneven shape on both its upper and lower surfaces, and the spacing or phase of the uneven shape on the upper surface of the gate pad is different from the uneven shape on the lower surface of the gate pad.

[0049] In semiconductor device 101, by having an uneven shape on the upper surface of gate pad 11, the shape of the upper surface of gate pad 11 can be made close to the shape of the upper surface of source pad 1. As a result, it is possible to ensure the process allowance when wire bonding is performed on gate pad 11 and source pad 1 with the same wire diameter and wire bonding conditions, and to suppress the peeling of wire bonds on gate pad 11.

[0050] <B. Implementation Method 2>

[0051] Figure 6 This is a cross-sectional view of the gate pad portion of the semiconductor device 102 according to Embodiment 2. The lower surface of the gate pad 11 of the gate pad portion of the semiconductor device 102 is flat, and the upper surface of the gate pad 11 has an uneven shape.

[0052] exist Figure 6In the example, the gate wiring 8 and the insulating layer 9 on the gate wiring 8 are flat. The lower surface of the gate pad 11 formed on the flat insulating layer 9 is flat. The upper surface of the gate pad 11 formed by sputtering is as flat as the lower surface. The upper surface of the gate pad 11 formed by sputtering is patterned, so that the gate pad 11 has an uneven shape only on the upper surface.

[0053] The top view of the semiconductor device 102 and the cross-sectional view of the source pad portion are as shown in Figure 1 and Figure 2 shown in the figures.

[0054] With the structure of the semiconductor device 102, the shape of the upper surface of the gate pad 11 can also be made close to the shape of the upper surface of the source pad 1. As a result, it is possible to secure a process margin when performing wire bonding on the gate pad 11 and the source pad 1 with the same wire diameter and wire bonding conditions, and to suppress peeling of the wire bonding of the gate pad 11.

[0055] <C. Embodiment 3>

[0056] Figure 7 is a perspective view of the gate pad 11 of the semiconductor device 103 according to Embodiment 3. In Figure 7 , illustration of the semiconductor substrate directly below the gate pad 11 is omitted.

[0057] In the semiconductor device 103, the upper surface of the gate pad 11 has a first uneven shape arranged along a first direction and a second uneven shape arranged along a second direction different from the first direction. The second direction may be a direction orthogonal to the first direction.

[0058] In Figure 7 , the lower surface of the gate pad 11 is flat. However, the lower surface of the gate pad 11 may also have a first uneven shape arranged along the first direction. Further, the lower surface of the gate pad 11 may have a second uneven shape arranged along the second direction in addition to the first uneven shape.

[0059] In this case, the pitch of the first uneven shape on the upper surface of the gate pad 11 is the same as the pitch of the first uneven shape on the lower surface of the gate pad 11, and the pitch of the second uneven shape on the upper surface of the gate pad 11 and the pitch of the second uneven shape on the lower surface of the gate pad 11 may be different.

[0060] With the structure of the semiconductor device 103, the shape of the upper surface of the gate pad 11 can also be made close to the shape of the upper surface of the source pad 1. As a result, it is possible to secure a process margin when performing wire bonding on the gate pad 11 and the source pad 1 with the same wire diameter and wire bonding conditions, and to suppress peeling of the wire bonding of the gate pad 11.

[0061] <D. Embodiment 4>

[0062] Figure 8 is a cross-sectional view of the source pad portion of the semiconductor device 104 according to Embodiment 4. Figure 9 is a cross-sectional view of the gate pad portion of the semiconductor device 104. The top view of the semiconductor device 104 is as Figure 1 shown in the figure.

[0063] As shown Figure 8 in the figure, the upper surface of the source pad 1 is formed with a concavo-convex shape having the same pitch but different phase as the concavo-convex shape on the lower surface of the source pad 1.

[0064] As shown Figure 9 in the figure, the upper surface of the gate pad 11 is formed with a concavo-convex shape having the same pitch but different phase as the concavo-convex shape on the lower surface of the gate pad 11. This concavo-convex shape on the upper surface of the gate pad 11 is formed by simultaneously patterning the upper surface of the source pad 1 and the upper surface of the gate pad 11 after the source pad 1 and the gate pad 11 are simultaneously formed by sputtering or the like.

[0065] Even with the structure of the semiconductor device 104, the shape of the upper surface of the gate pad 11 can be made close to the shape of the upper surface of the source pad 1. As a result, it is possible to secure the process margin when wire bonding is performed on the gate pad 11 and the source pad 1 with the same wire diameter and wire bonding conditions, and peeling of the wire bonding of the gate pad 11 can be suppressed.

[0066] In addition, according to the structure of the semiconductor device 104, the concave portion on the upper surface of the source pad 1 does not overlap directly above the region where the source pad 1 is in contact with the source layer 2 through the contact hole of the interlayer insulating film 5 (hereinafter referred to as "source contact region"). That is, the thickness of the source pad 1 directly above the source contact region can be ensured to be large. Thereby, during wire bonding, the ultrasonic bonding energy transmitted to the source contact region is further attenuated, so damage to the source contact region can be suppressed, and the process margin of the wire bonding step can be secured.

[0067] The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments and the like without departing from the scope defined in the claims.

[0068] Hereinafter, each aspect of the present disclosure will be collectively described as appendices.

[0069] (Appendix 1) A semiconductor device, comprising: a drift layer of a first conductivity type; A base layer of the second conductivity type is formed on the surface of the drift layer; A first conductivity type carrier supply layer, which is located on the surface of the base layer; A gate electrode configured to face the channel region, which is sandwiched between the carrier supply layer and the drift layer in the base layer, through a gate oxide film. An interlayer insulating film covering the gate electrode; The main electrode pad is electrically contacted with the carrier supply layer and insulated from the gate electrode by the interlayer insulating film. Gate wiring, formed across an insulating layer on the drift layer that does not overlap with the main electrode pads when viewed from above; and A gate pad is formed on the gate wiring through an insulating layer. The gate pad has an uneven shape on at least the upper surface of its upper and lower surfaces. When the lower surface of the gate pad has an uneven shape, the spacing or phase of the uneven shape on the upper surface of the gate pad is different from that on the lower surface of the gate pad.

[0070] (Note 2) The semiconductor device as described in Note 1, wherein, The lower surface of the gate pad is flat.

[0071] (Note 3) The semiconductor device as described in Note 1 or Note 2, wherein, The uneven shape of the upper surface of the gate pad includes a first uneven shape formed along a first direction and a second uneven shape formed along a second direction different from the first direction.

[0072] (Note 4) The semiconductor device as described in Note 3, wherein, The gate pad has an uneven shape on its lower surface. The uneven shape of the lower surface of the gate pad includes a first uneven shape formed along a first direction and a second uneven shape formed along a second direction different from the first direction. The spacing of the first convex and concave shapes on the upper surface of the gate pad is the same as the spacing of the first convex and concave shapes on the lower surface of the gate pad. The spacing of the second concave-convex shape on the upper surface of the gate pad is different from the spacing of the second concave-convex shape on the lower surface of the gate pad.

[0073] (Note 5) The semiconductor device as described in Note 1, wherein, The unevenness of the upper surface of the gate pad is at the same distance but at a different phase relative to the unevenness of the lower surface of the gate pad.

[0074] (Note 6) The semiconductor device as described in any one of Notes 1 to 5, wherein, The main electrode pad is the source electrode pad. The carrier supply layer is a source layer.

[0075] (Note 7) The semiconductor device as described in any one of Notes 1 to 6, wherein, The main electrode pad and the gate pad are made of aluminum.

[0076] Label Explanation

[0077] 1 Source pad, 2 Source layer, 3 Base layer, 4 Drift layer, 5 Interlayer insulating film, 6 Gate electrode, 7 Gate oxide film, 8 Gate wiring, 9, 10 Insulating layer, 11 Gate pad, 12 Edge termination, 13 Current sensing pad, 14 Temperature sensing pad, 101 Semiconductor device, 102 Semiconductor device, 103 Semiconductor device, 104 Semiconductor device.

Claims

1. A semiconductor device, characterized in that, include: Drift layer of the first conductivity type; A base layer of the second conductivity type is formed on the surface of the drift layer; A first conductivity type carrier supply layer is formed on the surface of the base layer. A gate electrode configured to face the channel region, which is sandwiched between the carrier supply layer and the drift layer in the base layer, through a gate oxide film. An interlayer insulating film covering the gate electrode; The main electrode pad is electrically contacted with the carrier supply layer and insulated from the gate electrode by the interlayer insulating film. Gate wiring, which is formed on the drift layer through an insulating layer and does not overlap with the main electrode pads when viewed from above; as well as A gate pad is formed on the gate wiring through an insulating layer. The gate pad has an uneven shape on at least the upper surface of its upper and lower surfaces. When the lower surface of the gate pad has an uneven shape, the spacing or phase of the uneven shape on the upper surface of the gate pad is different from that on the lower surface of the gate pad.

2. The semiconductor device as claimed in claim 1, characterized in that, The lower surface of the gate pad is flat.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The uneven shape of the upper surface of the gate pad includes a first uneven shape formed along a first direction and a second uneven shape formed along a second direction different from the first direction.

4. The semiconductor device as claimed in claim 3, characterized in that, The gate pad has an uneven shape on its lower surface. The uneven shape of the lower surface of the gate pad includes a first uneven shape formed along a first direction and a second uneven shape formed along a second direction different from the first direction. The spacing of the first convex and concave shapes on the upper surface of the gate pad is the same as the spacing of the first convex and concave shapes on the lower surface of the gate pad. The spacing of the second concave-convex shape on the upper surface of the gate pad is different from the spacing of the second concave-convex shape on the lower surface of the gate pad.

5. The semiconductor device as claimed in claim 1, characterized in that, The unevenness of the upper surface of the gate pad is at the same distance but in different phase relative to the unevenness of the lower surface of the gate pad.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The main electrode pad is the source electrode pad. The carrier supply layer is the source layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The main electrode pad and the gate pad are made of aluminum.

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