A semiconductor device and a method for manufacturing a semiconductor device
By stacking virtual chips on a first chip with a lower height to form a transition structure, the process consistency problem caused by chip height inconsistency in semiconductor devices is solved, improving product yield and mass production stability, thereby enhancing the performance of semiconductor devices.
Patent Information
- Application Number
- CN202611095705.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-22
- Publication Date
- 2026-11-03
AI Technical Summary
When forming heterogeneous integration of multiple chips on a wafer, the inconsistent height of the top chips makes it difficult to achieve process consistency, reduces the product yield and mass production stability of semiconductor devices, and affects performance.
A virtual chip is stacked on a first chip with a lower height, and a transition structure is formed on at least one side of the virtual chip. The width of a surface connecting the transition structure and perpendicular to the vertical direction of the virtual chip is smaller than the width of the first chip, thereby increasing the contact area of the encapsulation layer and improving the stability of the stacked structure.
It effectively improves the product yield and mass production stability of semiconductor devices, solves the problem of process consistency, and thus improves the performance of semiconductor devices.
Smart Images
Figure CN123036002A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology
[0002] In the process of integrated circuit manufacturing, semiconductor devices are typically stacked to improve their performance.
[0003] However, when forming heterogeneous integration of multiple chips on a wafer, it is common to encounter situations where the height of the top chips is different. This leads to difficulties in process consistency for subsequent wafer reconfiguration and packaging, reduces the product yield of semiconductor devices, limits the stability of mass production, and thus affects the performance of semiconductor devices. Summary of the Invention
[0004] The main technical problem solved by this invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can effectively improve the product yield of the semiconductor device, improve the stability of mass production, solve the problem of process consistency, and thus improve the performance of the semiconductor device.
[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a semiconductor device, comprising: a semiconductor substrate; a first chip and a second chip respectively disposed at intervals on the semiconductor substrate, wherein the height of the first chip is lower than the height of the second chip; and a virtual chip stacked on the first chip, wherein the top surface of the virtual chip and the top surface of the second chip are located on the same plane, at least one side of the virtual chip forms a transition structure, and the width of a surface of the virtual chip connecting the transition structure and perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip.
[0006] In one embodiment of this application, in the vertical direction, the virtual chip includes a first part and a second part, wherein the first part is away from the first chip and the second part is close to the first chip; the transition structure is formed on the side of the first part or the side of the second part.
[0007] In one embodiment of this application, at least one side of the first portion is formed with the transition structure, the bottom vertex of the first portion and the bottom vertex of the transition structure are on the same plane, wherein, in the vertical direction, the first height of the first portion is not greater than the second height of the second portion.
[0008] In one embodiment of this application, the transition structure is an angled structure that extends from the upper vertex of the first part to the bottom vertex of the side of the first part.
[0009] In one embodiment of this application, the second width of the top surface of the virtual chip is smaller than the first width of the first chip, and the third width of the bottom surface of the virtual chip is not greater than the first width of the first chip.
[0010] In one embodiment of this application, at least one side of the second part is formed with the transition structure, the upper vertex of the second part and the upper vertex of the transition structure are on the same plane, wherein, in the vertical direction, the second height of the second part is not greater than the first height of the first part.
[0011] In one embodiment of this application, the transition structure is an angled structure that extends from the bottom vertex of the second part to the top vertex of the side of the second part.
[0012] In one embodiment of this application, the third width of the bottom surface of the virtual chip is smaller than the first width of the first chip, and the second width of the top surface of the virtual chip is not greater than the first width of the first chip.
[0013] In one embodiment of this application, the transition structure is at least one step structure, wherein the at least one step structure is located on the side of the first part, and the bottom vertex of the step structure is on the same plane as the bottom vertex of the first part; or, the at least one step structure is located on the side of the second part, and the bottom vertex of the step structure is on the same plane as the bottom vertex of the second part.
[0014] In one embodiment of this application, it further includes: an encapsulation layer that covers the first chip, the second chip, and the virtual chip, and also covers the transition structure.
[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; disposing a first chip and a second chip at intervals on the semiconductor substrate, wherein the height of the first chip is lower than the height of the second chip; stacking virtual chips on the first chip, wherein the top surface of the virtual chip and the top surface of the second chip are located in the same plane; forming a transition structure on at least one side of the virtual chip, and the width of a surface of the virtual chip connecting the transition structure and perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip.
[0016] In one embodiment of this application, stacking the virtual chip on the first chip includes: providing the virtual chip, wherein, in the vertical direction, the virtual chip includes a first portion and a second portion, the first portion being away from the first chip and the second portion being close to the first chip, and the transition structure being formed on the side of the first portion or the side of the second portion; and disposing the virtual chip on the first chip.
[0017] In one embodiment of this application, the transition structure is an angled structure, and the transition structure is formed on the side of the first part; providing a virtual chip includes: using a first cutting method to cut from the upper vertex of the first part to the bottom vertex of at least one side of the first part to form the angled structure; using a second cutting method to cut a wafer containing multiple virtual chips to form a single virtual chip, wherein the bottom vertex of the first part and the bottom vertex of the transition structure are on the same plane, and in the vertical direction perpendicular to the virtual chip, the first height of the first part is not greater than the second height of the second part.
[0018] In one embodiment of this application, the transition structure is an angled structure, and the transition structure is formed on the side of the second part; providing the virtual chip includes: cutting a wafer containing multiple virtual chips using a second cutting method to form a single virtual chip; and cutting from the bottom vertex of the second part to the top vertex of at least one side of the second part using a first cutting method to form the angled structure, wherein the top vertex of the second part and the top vertex of the transition structure are on the same plane, and in the vertical direction, the second height of the second part is not greater than the first height of the first part.
[0019] In one embodiment of this application, the first cutting angle of the first cutting method is smaller than the second cutting angle of the second cutting method, wherein the second cutting angle is a vertical angle.
[0020] In one embodiment of this application, the transition structure is a step structure; providing a virtual chip includes: forming the step structure on at least one side of the first part by etching, wherein the bottom vertex of the step structure is on the same plane as the bottom vertex of the first part; or, forming the step structure on at least one side of the second part, wherein the bottom vertex of the step structure is on the same plane as the bottom vertex of the second part.
[0021] In one embodiment of this application, the etching method is multi-step etching, which forms multiple step structures on at least one side of the virtual chip.
[0022] Unlike current technologies, the semiconductor device provided in this application includes: a semiconductor substrate; a first chip and a second chip respectively disposed at intervals on the semiconductor substrate, wherein the height of the first chip is lower than the height of the second chip; and a virtual chip stacked on the first chip, wherein the top surface of the virtual chip and the top surface of the second chip are located on the same plane, at least one side of the virtual chip forms a transition structure, and the width of a surface of the virtual chip connecting to the transition structure and perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip. In other words, in this application, when multiple chips are disposed on the same semiconductor substrate, a virtual chip is formed on the lower-height first chip to fill the height gap of the first chip. Furthermore, the formation of a transition structure on at least one side of the virtual chip, and the width of a surface of the virtual chip connecting to the transition structure and perpendicular to the vertical direction of the virtual chip being less than the first width of the first chip, increases the contact area with the subsequently formed packaging layer, improves the stability of the stacked structure, effectively improves the product yield of the semiconductor device, enhances the stability of mass production, solves the process consistency problem, and thus improves the performance of the semiconductor device. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application; Figure 3 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application; Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the semiconductor device in this application; Figure 5 This is a schematic diagram of the structure of the fifth embodiment of the semiconductor device in this application; Figure 6 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application; Figure 7 This is a schematic diagram of an embodiment of the first chip and the second chip in this application; Figure 8 This is a schematic diagram of the structure of the first embodiment of the virtual chip in this application; Figure 9 This is a schematic diagram of the structure of the second embodiment of the virtual chip in this application; Figure 10 This is a schematic diagram of the structure of the third embodiment of the virtual chip in this application.
[0024] In the attached figure, there is a semiconductor substrate 100, a first chip 200, a second chip 300, a virtual chip 400, a transition structure 410, an angled structure 411, a stepped structure 412, an encapsulation layer 500, a first height H1, a second height H2, a first width W1, a second width W2, and a third width W3. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0026] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0028] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0029] This application provides a semiconductor device that effectively improves the product yield of semiconductor devices, enhances the stability of mass production, solves the problem of process consistency, and thereby improves the performance of semiconductor devices.
[0030] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application.
[0031] The semiconductor device of this application includes: a semiconductor substrate 100, a first chip 200, a second chip 300, and a virtual chip 400.
[0032] A first chip 200 and a second chip 300 are disposed on a semiconductor substrate 100 at intervals, with the height of the first chip 200 being lower than the height of the second chip 300; a virtual chip 400 is disposed on the first chip 200, with the top surface of the virtual chip 400 and the top surface of the second chip 300 on the same plane; at least one side of the virtual chip 400 forms a transition structure 410, and the width of a surface of the virtual chip 400 that connects to the transition structure 410 and is perpendicular to the vertical direction of the virtual chip 400 is less than the first width W1 of the first chip 200.
[0033] In this context, semiconductor substrate 100 refers to a single-layer substrate composed of the same or different materials, or at least two-layer substrates composed of the same or different materials; first chip 200 and second chip 300 refer to manufactured functional chips; virtual chip 400 refers to a non-functional chip. A side refers to a side extending perpendicular to the first chip 200; for example, the side of virtual chip 400 closest to the second chip 300 is a side, and the side furthest from the second chip 300 is also a side. Transition structure 410 refers to a transition structure in width and / or height, i.e., the width gradually decreases or increases, and the height gradually decreases or increases. The height of the first chip 200 refers to the vertical distance from the top surface to the bottom surface of the first chip 200; the height of the second chip 300 refers to the vertical distance from the top surface to the bottom surface of the second chip 300. A surface refers to a plane parallel to the horizontal direction of the semiconductor substrate 100, such as the bottom and top surfaces of the virtual chip 400; the bottom surface of the virtual chip 400 refers to the surface close to the semiconductor substrate 100, and the top surface of the virtual chip 400 refers to the surface away from the semiconductor substrate 100. It can be understood that a surface of the virtual chip 400 that connects to the transition structure 410 and is perpendicular to the vertical direction of the virtual chip 400 means that a surface of the virtual chip 400 is perpendicular to the vertical direction of the virtual chip 400, and this surface connects to the transition structure 410, and the width of this surface is smaller than the width of the first chip 200.
[0034] Specifically, a first chip 200 and a second chip 300 are disposed at intervals on a semiconductor substrate 100, wherein the height of the first chip 200 is lower than the height of the second chip 300. To compensate for the height difference and reduce difficulties in process consistency, a dummy chip 400 is stacked on top of the first chip 200, so that after stacking the dummy chip 400, the overall height of the first chip 200 and the dummy chip 400 is the same as the overall height of the second chip 300. That is, after stacking the dummy chip 400 on the first chip 200, the top surface of the dummy chip 400 and the top surface of the second chip 300 are located on the same plane. Furthermore, to ensure the stability of the stacked structure, a transition structure 410 is formed on at least one side of the dummy chip 400, and the width of a surface of the dummy chip 400 connecting the transition structure 410 and perpendicular to the vertical direction of the dummy chip 400 is less than the first width W1 of the first chip 200. The width of the top surface of the virtual chip 400 may be less than the first width W1 of the top or bottom surface of the first chip 200, or the width of the bottom surface of the virtual chip 400 may be less than the first width W1 of the top or bottom surface of the first chip 200. Figure 1 The following explanation uses a transition structure 410 formed on one side as an example. That is, a transition structure 410 is formed on the side of the virtual chip 400 close to the second chip 300, or on the side of the virtual chip 400 far from the second chip 300.
[0035] Understandably, multiple chips can be disposed on the semiconductor substrate 100, with intervals between them. For chips with lower heights, corresponding virtual chips 400 can be stacked, and at least one side of the virtual chip 400 forms a transition structure 410. For example, taking the tallest chip as a reference, other chips are each provided with a virtual chip 400 of their corresponding height, so that all stacked structures after this are made to have the same height as the tallest chip.
[0036] In this embodiment, when multiple chips are disposed on the same semiconductor substrate, virtual chips are stacked on the first chip with a lower height to fill the height gap of the first chip. A transition structure is formed on at least one side of the virtual chip, which reduces the width of the plane in which the transition structure is formed. That is, the width of the surface of the virtual chip connecting the transition structure and perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip, which increases the contact area with the subsequently formed packaging layer, improves the stability of the stacked structure, effectively improves the product yield of semiconductor devices, improves the stability of mass production, solves the problem of process consistency, and thus improves the performance of semiconductor devices.
[0037] In some embodiments, in a vertical direction perpendicular to the virtual chip 400, the virtual chip 400 includes a first portion 420 and a second portion 430, wherein the first portion 420 is away from the first chip 200 and the second portion 430 is close to the first chip 200; a transition structure 410 is formed on the side of the first portion 420 or the side of the second portion 430.
[0038] Specifically, from top to bottom, the virtual chip 400 is divided into a first part 420 and a second part 430, and a transition structure 410 can be formed on at least one side of the first part 420 or on at least one side of the second part 430. If the transition structure 410 is formed in the first part 420, then the first height H1 of the first part 420 is not greater than the second height H2 of the second part 430. If the transition structure 410 is formed in the second part 430, then the second height H2 of the second part 430 is not greater than the first height H1 of the first part 420.
[0039] In some embodiments, at least one side of the first portion 420 is formed with a transition structure 410, and the bottom vertex of the first portion 420 and the bottom vertex of the transition structure 410 are located in the same plane, wherein, in the vertical direction, the first height H1 of the first portion 420 is not greater than the second height H2 of the second portion 430. It is understood that the top vertex of the first portion 420 and the top vertex of the transition structure 410 are located in the same plane.
[0040] Here, the bottom vertex refers to the lowest point of the structure, and the top vertex refers to the highest point of the structure; the first height H1 refers to the height from the bottom surface of the first part 420 to the top surface of the first part 420; the second height H2 refers to the height from the bottom surface of the second part 430 to the top surface of the second part 430.
[0041] like Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application.
[0042] Specifically, a transition structure 410 is formed on at least one side of the first portion 420 of the virtual chip 400, taking two sides as an example. The bottom vertex of the first portion 420 and the bottom vertex of the transition structure 410 are located in the same plane, and the top vertex of the first portion 420 and the top vertex of the transition structure 410 are also located in the same plane. In the vertical direction, the first height H1 of the first portion 420 is not greater than the second height H2 of the second portion 430. Taking the formation of the transition structure 410 on two sides of the virtual chip 400 as an example, one transition structure 410 is formed on the side of the first portion 420 closer to the second chip 300, and another transition structure 410 is formed on the side of the first portion 420 farther from the second chip 300. The height of the transition structure 410, i.e., the first height H1 of the first portion 420, is not greater than the second height H2 of the second portion 430, thus maintaining a certain thickness in the second portion 430, thereby preserving the contour recognition of the virtual chip 400.
[0043] Furthermore, the second width W2 of the top surface of the virtual chip 400 is less than the first width W1 of the top or bottom surface of the first chip 200, or the third width W3 of the bottom surface of the virtual chip 400 is less than the first width W1 of the top or bottom surface of the first chip 200. Figure 1 and Figure 2 The illustration is given as an example where the second width W2 of the top surface of the virtual chip 400 is smaller than the first width W1 of the top or bottom surface of the first chip 200.
[0044] In some embodiments, the transition structure 410 is an oblique structure 411, that is, the upper vertex of the oblique structure 411 is located on the same plane as the upper vertex of the first part 420, and the lower vertex of the oblique structure 411 is located on the same plane as the lower vertex of the first part 420; wherein, in the vertical direction perpendicular to the virtual chip 400, the height of the oblique structure 411 is the first height H1 of the first part 420, that is, the first height of the first part 420 is not greater than the second height H2 of the second part.
[0045] Among them, the oblique structure 411 refers to the inclined slope surface that forms a straight line by obliquely cutting the right angle of the virtual chip 400.
[0046] Specifically, taking the formation of transition structures 410 on both sides of the virtual chip 400 as an example, that is, forming an angled structure 411 on the side of the virtual chip 400 closer to the second chip 300 and another angled structure 411 on the side farther from the second chip 300, that is, forming angled structures 411 on both sides of the first part 420. The height of the two angled structures 411 is the first height H1 of the first part, and the first height H1 is not greater than the second height H2 of the second part 430 of the virtual chip 400, thereby preserving the contour recognition of the virtual chip 400.
[0047] In some embodiments, the beveled structure 411 is located in the first portion 420 and connected to the top surface of the virtual chip 400, that is, it extends from the upper vertex of the first portion 420 of the virtual chip 400 to the bottom vertex of at least one side of the first portion 420.
[0048] Specifically, the beveled structure 411 is formed on the top surface of the virtual chip 400 and extends from the top surface of the virtual chip 400 to the side surface of the virtual chip 400. That is, the beveled structure 411 extends from the upper vertex of the first part 420 to the bottom vertex of the side surface of the first part 420. The bottom surface of the virtual chip 400 is close to the first chip 200, that is, the second part 430 of the virtual chip 400 is close to the first chip 200. For example, the bottom surface of the virtual chip 400 is in contact with the first chip 200, that is, the second part 430 is in contact with the first chip 200.
[0049] In some embodiments, the second width W2 of the top surface of the virtual chip 400 is less than the first width W1 of the first chip 200, the third width W3 of the bottom surface of the virtual chip 400 is not greater than the first width W1 of the first chip 200, and the second width W2 is less than the third width W3.
[0050] Since the angled structure 411 extends from the top of the virtual chip 400 to the side of the virtual chip 400, the second width W2 of the top surface of the virtual chip 400 is smaller than the third width W3 of the bottom surface of the virtual chip 400.
[0051] Specifically, after forming the angled structure 411, the second width W2 of the top surface of the virtual chip 400 is smaller than the third width W3 of the bottom surface of the virtual chip 400. Since the bottom surface of the virtual chip 400 is in contact with the first chip 200, the third width W3 of the bottom surface of the virtual chip 400 can be the same as the first width W1 of the top surface of the first chip 200. Therefore, the second width W2 of the top surface of the virtual chip 400 is smaller than the first width W1 of either the top or bottom surface of the first chip 200. It can be understood that the top and bottom surfaces of the first chip 200 have the same width, both being the first width W1.
[0052] It is understandable that, due to the influence of process precision, the third width W3 of the bottom surface of the virtual chip 400 that is in contact with the first chip 200 may be slightly smaller than the first width W1 of the top surface of the first chip 200. Generally, it can be considered that the third width W3 of the bottom surface of the virtual chip 400 that is in contact with the first chip 200 is equal to the first width W1 of the top surface of the first chip 200.
[0053] In some embodiments, the system further includes an encapsulation layer 500 that covers the first chip 200, the second chip 300, and the virtual chip 400, and also covers the transition structure 410.
[0054] Among them, the encapsulation layer 500 refers to the material layer of the encapsulated chip, which is used to protect the chip.
[0055] Specifically, after the virtual chip 400 is stacked on the first chip 200, it is encapsulated by the encapsulation layer 500 so that the encapsulation layer 500 covers the top and sides of the second chip 300, the top and sides of the virtual chip 400, the transition structure 410 on the virtual chip 400, the sides of the first chip 200, and the exposed portion of the semiconductor substrate 100.
[0056] In some embodiments, at least one side of the second portion 430 is formed with a transition structure 410, the upper vertex of the second portion 430 and the upper vertex of the transition structure 410 are in the same plane, wherein, in the vertical direction, the second height H2 of the second portion 430 is not greater than the first height H1 of the first portion 420.
[0057] Please see Figure 3 , Figure 3 This is a structural schematic diagram of the third embodiment in this application.
[0058] Among them, with Figure 2 The difference is that, in this embodiment, a transition structure 410 is formed on the side of the second part 430.
[0059] Specifically, a transition structure 410 is formed on at least one side of the second portion 430 of the virtual chip 400. Taking two sides as an example, a transition structure 410 is formed on the side of the second portion 430 closer to the second chip 300, and another transition structure 410 is formed on the side of the second portion 430 farther from the second chip 300. The height of the transition structure 410, which is also the second height H2 of the second portion 430, is not greater than the first height H1 of the first portion 420. Similarly, the first portion 420 needs to retain a certain thickness to maintain the contour recognition of the virtual chip 400.
[0060] In some embodiments, the transition structure 410 is an angled structure 411, which extends from the bottom vertex of the second portion 430 of the virtual chip 400 to the top vertex of the side of the second portion 430 of the virtual chip 400. It is understood that the angled structure 411 is located in the second portion 430 and is connected to the bottom surface of the virtual chip 400.
[0061] Please continue reading. Figure 3 The bottom surface of the virtual chip 400 is in contact with the first chip 200, while the angled structure 411 extends from the bottom surface of the virtual chip 400 to the side surface of the virtual chip 400.
[0062] Taking the formation of transition structures 410 on both sides of the virtual chip 400 as an example, a beveled structure 411 is formed from the side of the virtual chip 400 closest to the second chip 300 to the bottom surface of the virtual chip 400, and another beveled structure 411 is formed from the side of the virtual chip 400 furthest from the second chip 300 to the bottom surface of the virtual chip 400. That is, beveled structures 411 are formed on both sides of the second part 430. The beveled structures 411 extend from the bottom surface of the virtual chip 400 along the sides of the virtual chip 400.
[0063] Specifically, the beveled structure 411 is formed on the bottom surface of the virtual chip 400, extending from the bottom surface of the virtual chip 400 to the side surface of the virtual chip 400. That is, the beveled structure 411 extends from the bottom vertex of the second part 430 to the top vertex of at least one side surface of the second part 430. The bottom surface of the virtual chip 400 is close to the first chip 200, that is, the second part 430 of the virtual chip 400 is close to the first chip 200. For example, the bottom surface of the virtual chip 400 is in contact with the first chip 200, that is, the second part 430 is in contact with the first chip 200.
[0064] In some embodiments, the third width W3 of the bottom surface of the virtual chip 400 is less than the first width W1 of the first chip 200, the second width W2 of the top surface of the virtual chip 400 is not greater than the first width W1 of the first chip 200, and the second width W2 is greater than the third width W3.
[0065] Since the angled structure 411 extends from the bottom of the virtual chip 400 to the side of the virtual chip 400, the third width W3 of the bottom surface of the virtual chip 400 is smaller than the first width W1 of the first chip 200.
[0066] Specifically, after forming the angled structure 411, the third width W3 of the bottom surface of the virtual chip 400 is smaller than the second width W2 of the top surface of the virtual chip 400. The second width W2 of the top surface of the virtual chip 400 can be the same as the first width W1 of the top surface of the first chip 200. Therefore, the third width W3 of the bottom surface of the virtual chip 400 is smaller than the first width W1 of the top or bottom surface of the first chip 200.
[0067] In some embodiments, the system further includes an encapsulation layer 500 that covers the first chip 200, the second chip 300, and the virtual chip 400, and also covers the transition structure 410.
[0068] Among them, the encapsulation layer 500 refers to the material layer of the encapsulated chip, which is used to protect the chip.
[0069] Specifically, after the virtual chip 400 is formed on the first chip 200, it is encapsulated by the encapsulation layer 500 so that the encapsulation layer 500 covers the top and sides of the second chip 300, the top and sides of the virtual chip 400, the transition structure 410 on the virtual chip 400, the sides of the first chip 200, and the exposed portion of the semiconductor substrate 100.
[0070] It is understandable that, due to the influence of process precision, the second width W2 of the top surface of the virtual chip 400 may be slightly smaller than the first width W1 of the top surface of the first chip 200. Generally, it can be considered that the second width W2 of the top surface of the virtual chip 400 is equal to the first width W1 of the top surface of the first chip 200.
[0071] In some embodiments, the transition structure 410 is at least one step structure 412, wherein the at least one step 412 is located on the side of the first portion 420, and the bottom vertex of the step structure 412 is in the same plane as the bottom vertex of the first portion 420. It is understood that the top vertex of the step structure 412 is in the same plane as the top vertex of the first portion 420.
[0072] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the semiconductor device in this application.
[0073] Among them, the stepped structure 412 refers to a stepped structure.
[0074] Specifically, taking the formation of stepped structures 412 on two sides of the virtual chip 400 as an example, one stepped structure 412 is formed on the side of the virtual chip 400 near the first part 420 of the second chip 300, and another stepped structure 412 is formed on the side of the virtual chip 400 away from the first part 420 of the second chip 300. The height of the two stepped structures 412 is the first height H1 of the first part 420, that is, the first height H1 is not greater than the second height H2 of the second part 430 of the virtual chip 400, thereby preserving the contour recognition of the virtual chip 400.
[0075] In other embodiments, a stepped structure 412 is formed on the bottom surface of the virtual chip 400.
[0076] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of the fifth embodiment of the semiconductor device in this application.
[0077] Specifically, taking the formation of stepped structures 412 on two sides of the virtual chip 400 as an example, one stepped structure 412 is formed on the side of the virtual chip 400 near the second part 430 of the second chip 300, and another stepped structure 412 is formed on the side of the second part 430 away from the second chip 300. The height of the two stepped structures 412 is the second height H2 of the second part 430, that is, the second height H2 is not greater than the first height H1 of the first part 420 of the virtual chip 400, thereby preserving the contour recognition of the virtual chip 400.
[0078] Understandable Figure 4 A stepped structure 412 is formed on the top surface of the virtual chip 400. Figure 5 A stepped structure 412 is formed on the bottom surface of the virtual chip 400.
[0079] Understandably, a stepped structure 412 can be formed on only one side of the virtual chip 400 to increase the surface area, thereby increasing the contact area for subsequent encapsulation layers.
[0080] It is also understandable that the step structure 412 can be a single step or more, depending on the difficulty of the process. Figure 4 and Figure 5 Let's take a single step as an example to illustrate.
[0081] In some embodiments, the system further includes an encapsulation layer 500 that covers the first chip 200, the second chip 300, and the virtual chip 400, and also covers the transition structure 410.
[0082] Among them, the encapsulation layer 500 refers to the material layer of the encapsulated chip, which is used to protect the chip.
[0083] Specifically, after the virtual chip 400 is formed on the first chip 200, it is encapsulated by the encapsulation layer 500 so that the encapsulation layer 500 covers the top and sides of the second chip 300, the top and sides of the virtual chip 400, the step structure 412 on the virtual chip 400, the sides of the first chip 200, and the exposed part of the semiconductor substrate 100.
[0084] In this embodiment, when multiple chips are disposed on the same semiconductor substrate, a virtual chip is formed on the first chip with a lower height to fill the height gap of the first chip. A transition structure is formed on at least one side of the virtual chip so that the width of a surface of the virtual chip connecting the transition structure and perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip. This increases the contact area with the subsequently formed packaging layer, improves the stability of the stacked structure, effectively improves the product yield of the semiconductor device, improves the stability of mass production, solves the problem of process consistency, and thus improves the performance of the semiconductor device.
[0085] This application also provides a method for manufacturing a semiconductor device.
[0086] Please see Figure 6 , Figure 6 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application.
[0087] S10 provides a semiconductor substrate.
[0088] S20. The first chip and the second chip are respectively disposed on the semiconductor substrate at intervals, wherein the height of the first chip is lower than the height of the second chip.
[0089] S30. A virtual chip is stacked on top of a first chip, wherein the top surface of the virtual chip and the top surface of the second chip are located on the same plane, at least one side of the virtual chip has a transition structure, and the width of a surface of the virtual chip that connects to the transition structure and is perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip.
[0090] To better understand the manufacturing process of semiconductor devices, the following explanation is provided in conjunction with the accompanying drawings.
[0091] First, a semiconductor substrate 100 is provided, and a first chip 200 and a second chip 300 are disposed on the semiconductor substrate 100 at intervals, wherein the height of the first chip 200 is lower than the height of the second chip 300.
[0092] Please see Figure 7 , Figure 7 This is a schematic diagram of an embodiment of the first chip and the second chip in this application.
[0093] Specifically, a semiconductor substrate 100 serves as a support base, and a first chip 200 and a second chip 300, which are functional chips, are respectively disposed on the semiconductor substrate 100, with the first chip 200 and the second chip 300 spaced apart. It is understood that the different chips have different heights; for example, the height of the first chip 200 is lower than the height of the second chip 300.
[0094] Next, a virtual chip 400 is provided. In a vertical direction perpendicular to the virtual chip 400, the virtual chip 400 includes a first portion 420 and a second portion 430, the first portion 420 being away from the first chip 200 and the second portion 430 being close to the first chip 200, and a transition structure 410 being formed on the side of the first portion 420 or the side of the second portion 430.
[0095] In some embodiments, the transition structure 410 is an oblique structure 411, and the transition structure 410 is formed on the side of the first part 420; an oblique cut can be made first, followed by a vertical cut.
[0096] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of the first embodiment of the virtual chip in this application.
[0097] Specifically, a first cutting method is used to cut from the top of the virtual chip 400 to at least one side of the virtual chip 400 to form an oblique structure 411, that is, to cut from the upper vertex of the first part 420 to the bottom vertex of at least one side of the first part 420 to form an oblique structure 411. Then, a second cutting method is used to cut the wafer containing multiple virtual chips 400 to form a single virtual chip 400; wherein, the bottom vertex of the first part 420 and the bottom vertex of the transition structure 410 are on the same plane, and in the vertical direction perpendicular to the virtual chip 400, the height of the oblique structure 411 is the first height H1 of the first part 420, that is, the first height H1 is not greater than the second height H2 of the second part 430 of the virtual chip 400.
[0098] Taking the cutting on two sides as an example, that is, forming beveled structures 411 on both sides of the top surface of the virtual chip 400, the second width W2 of the top surface of the virtual chip 400 is less than the third width W3 of the bottom surface of the virtual chip 400, and the first height H1 corresponding to the beveled structure 411 is not greater than the second height H2 of the second part 430 of the virtual chip 400.
[0099] In another embodiment, a vertical cut can be made first, followed by a bevel cut.
[0100] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of the second embodiment of the virtual chip in this application.
[0101] Specifically, the wafer containing multiple virtual chips is first cut using a second cutting method to form a single virtual chip 400; then, the first cutting method is used to cut from the bottom of the virtual chip to at least one side of the virtual chip to form an oblique structure 411, that is, to cut from the bottom vertex of the second part 430 to the top vertex of at least one side of the second part 430 to form an oblique structure 411; wherein, the top vertex of the second part 430 and the top vertex of the transition structure 410 are on the same plane, and in the vertical direction perpendicular to the virtual chip 400, the height of the oblique structure 411 is the second height H2 of the second part 430, and the second height H2 is not greater than the first height H1 of the first part 420 of the virtual chip 400.
[0102] Alternatively, the second cutting method can be used first, followed by the first cutting method, to cut from the top of the virtual chip 400 to at least one side of the virtual chip 400 to form an angled structure 411. Subsequently, the side forming the angled structure 411 can be brought into contact with the first chip 200.
[0103] Taking the cutting on two sides as an example, that is, forming beveled structures 411 on both sides of the bottom surface of the virtual chip 400, the third width W3 of the bottom surface of the virtual chip 400 is less than the second width W2 of the top surface of the virtual chip 400; and the height of the part where the beveled structure 411 is located is not greater than the height of the other part of the virtual chip 400.
[0104] In some embodiments, the first cutting angle of the first cutting method is smaller than the second cutting angle of the second cutting method, wherein the second cutting angle is a vertical angle.
[0105] Both the first and second cutting methods are dicing methods for semiconductor devices.
[0106] Specifically, the first cutting method is a bevel cut, therefore the first cutting angle is less than 90°, and the second cutting method is a vertical cut, therefore the second cutting angle is equal to 90°.
[0107] In some embodiments, the transition structure is a stepped structure 412.
[0108] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of the third embodiment of the virtual chip in this application.
[0109] The step structure 412 can be formed by etching.
[0110] An etching method is used to form a step structure 412 on at least one side of the first part 420, and the bottom vertex of the step structure 412 is on the same plane as the bottom vertex of the first part 420; it can be understood that the top vertex of the step structure 412 is also on the same plane as the top vertex of the first part 420.
[0111] Specifically, taking the formation of a stepped structure 412 on two sides as an example, the virtual chip 400 is etched at least once, for example, once or multiple times, to form one or more steps in the first part 420. In the vertical direction perpendicular to the virtual chip 400, the height of the stepped structure 412 is the first height H1 of the first part 420, and this first height H1 is not greater than the second height H2 of the second part 430 of the virtual chip 400. Furthermore, the third width W3 of the bottom surface of the virtual chip 400 is greater than the second width W2 of the top surface of the virtual chip 400.
[0112] In another embodiment, a step structure 412 is formed on at least one side of the second portion 430, and the bottom vertex of the step structure 412 is in the same plane as the bottom vertex of the second portion 430. It is understood that the top vertex of the step structure 412 is also in the same plane as the top vertex of the second portion 430.
[0113] Specifically, taking the formation of a step structure 412 on two sides as an example, the virtual chip 400 is etched at least once, for example, once or multiple times, to form one or more steps in the second part 430. In the vertical direction perpendicular to the virtual chip 400, the height of the step structure 412 is the second height H2 of the second part 430, which is not greater than the first height H1 of the first part 420 of the virtual chip 400. At this time, the second width W2 of the top surface of the virtual chip 400 is greater than the third width W3 of the bottom surface of the virtual chip 400. (See [link to relevant documentation]). Figure 5 .
[0114] It is understandable that when multiple steps are required, they can be formed through multi-step etching, creating multiple step structures 412 on at least one side of the virtual chip 400; that is, one step of etching forms one step, and multiple steps of etching form multiple steps. Furthermore, the corresponding step structure 412 can be formed only on one side of the virtual chip 400.
[0115] Alternatively, it can be understood that after the first part 420 forms one or more steps, it can be flipped and then stacked on the first chip 200.
[0116] The virtual chip 400 is then placed on the first chip 200 to obtain a semiconductor device. Please refer to [link to relevant documentation]. Figures 2-5 .
[0117] In this embodiment, when multiple chips are disposed on the same semiconductor substrate, a virtual chip is formed on the first chip with a lower height to fill the height gap of the first chip, and a transition structure is formed on at least one side of the virtual chip so that the width of one plane of the virtual chip is smaller than the first width of the first chip, thereby increasing the contact area with the subsequently formed packaging layer, improving the stability of the stacked structure, effectively improving the product yield of semiconductor devices, improving the stability of mass production, solving the problem of process consistency, and thus improving the performance of semiconductor devices.
[0118] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A semiconductor device, characterized in that, include: Semiconductor substrate; A first chip and a second chip are respectively disposed on the semiconductor substrate at intervals, wherein the height of the first chip is lower than the height of the second chip; A virtual chip is stacked on top of the first chip, wherein the top surface of the virtual chip and the top surface of the second chip are located on the same plane, at least one side of the virtual chip forms a transition structure, and the width of a surface of the virtual chip that connects to the transition structure and is perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip.
2. The semiconductor device according to claim 1, characterized in that, In the vertical direction, the virtual chip includes a first part and a second part, wherein the first part is away from the first chip and the second part is close to the first chip; The transition structure is formed on the side of the first part or the side of the second part.
3. The semiconductor device according to claim 2, characterized in that, The first part has at least one side of the transition structure, the bottom vertex of the first part and the bottom vertex of the transition structure are located in the same plane, wherein, in the vertical direction, the first height of the first part is not greater than the second height of the second part.
4. The semiconductor device according to claim 3, characterized in that, The transition structure is an angled structure that extends from the upper vertex of the first part to the bottom vertex of at least one side of the first part.
5. The semiconductor device according to claim 4, characterized in that, The second width of the top surface of the virtual chip is smaller than the first width of the first chip, and the third width of the bottom surface of the virtual chip is not greater than the first width of the first chip.
6. The semiconductor device according to claim 2, characterized in that, The transition structure is formed on at least one side of the second part, and the upper vertex of the second part and the upper vertex of the transition structure are on the same plane, wherein, in the vertical direction, the second height of the second part is not greater than the first height of the first part.
7. The semiconductor device according to claim 6, characterized in that, The transition structure is an angled structure that extends from the bottom vertex of the second part to the top vertex of the side of the second part.
8. The semiconductor device according to claim 7, characterized in that, The third width of the bottom surface of the virtual chip is smaller than the first width of the first chip, and the second width of the top surface of the virtual chip is not greater than the first width of the first chip.
9. The semiconductor device according to claim 2, characterized in that, The transition structure is at least one step structure, wherein the at least one step structure is located on the side of the first part, and the bottom vertex of the step structure is on the same plane as the bottom vertex of the first part; or, the at least one step structure is located on the side of the second part, and the bottom vertex of the step structure is on the same plane as the bottom vertex of the second part.
10. The semiconductor device according to claim 1, characterized in that, Also includes: An encapsulation layer that covers the first chip, the second chip, and the virtual chip, and also covers the transition structure.
11. A method for manufacturing a semiconductor device, characterized in that, include: Provide semiconductor substrate; A first chip and a second chip are respectively disposed at intervals on the semiconductor substrate, wherein the height of the first chip is lower than the height of the second chip; Virtual chips are stacked on top of the first chip, wherein the top surface of the virtual chip and the top surface of the second chip are located on the same plane, at least one side of the virtual chip has a transition structure, and the width of a surface of the virtual chip that connects to the transition structure and is perpendicular to the vertical direction of the virtual chip is less than the first width of the first chip.
12. The manufacturing method according to claim 11, characterized in that, The step of stacking virtual chips on the first chip includes: A virtual chip is provided, wherein, in the vertical direction, the virtual chip includes a first portion and a second portion, the first portion being away from the first chip and the second portion being close to the first chip, and the transition structure is formed on the side of the first portion or the side of the second portion; The virtual chip is set on the first chip.
13. The manufacturing method according to claim 12, characterized in that, The transition structure is an angled structure, and the transition structure is formed on the side of the first part; The provision of the virtual chip includes: Using a first cutting method, the first part is cut from the top vertex to the bottom vertex of at least one side of the first part to form the oblique structure; A second cutting method is used to cut a wafer containing multiple virtual chips to form a single virtual chip, wherein the bottom vertex of the first part and the bottom vertex of the transition structure are on the same plane, and in the vertical direction, the first height of the first part is not greater than the second height of the second part.
14. The manufacturing method according to claim 12, characterized in that, The transition structure is an angled structure, and the transition structure is formed on the side of the second part; The provision of the virtual chip includes: The wafer containing multiple virtual chips is cut using a second cutting method to form a single virtual chip; Using a first cutting method, the second part is cut from the bottom vertex to the top vertex of at least one side of the second part to form the oblique structure, wherein the top vertex of the second part and the top vertex of the transition structure are on the same plane, and in the vertical direction, the second height of the second part is not greater than the first height of the first part.
15. The manufacturing method according to claim 13 or 14, characterized in that, The first cutting angle of the first cutting method is smaller than the second cutting angle of the second cutting method, wherein the second cutting angle is a vertical angle.
16. The manufacturing method according to claim 12, characterized in that, The transition structure is a stepped structure; The provision of the virtual chip includes: The step structure is formed on at least one side of the first part by etching, and the bottom vertex of the step structure is on the same plane as the bottom vertex of the first part; or, the step structure is formed on at least one side of the second part, and the bottom vertex of the step structure is on the same plane as the bottom vertex of the second part.
17. The manufacturing method according to claim 16, characterized in that, The etching method is a multi-step etching, which forms multiple step structures on at least one side of the virtual chip.