Package structure and method of forming the same

Abstract

A packaging structure, a front surface of a first wafer includes a first overlapping area overlapping a second wafer in a vertical direction and a first non-overlapping area staggered with the second wafer in the vertical direction; a first inorganic dielectric layer covering the first overlapping area and the first non-overlapping area; a second inorganic dielectric layer covering an entire back surface of the second wafer, a part of the first inorganic dielectric layer covering the first overlapping area is mixedly connected with the second inorganic dielectric layer; a circuit layer arranged above the second wafer; a first connecting member electrically connecting the first non-overlapping area and the circuit layer; a second connecting member electrically connecting a front surface of the second wafer facing the circuit layer and the circuit layer; and a molding layer below the circuit layer and covering the first wafer, the first connecting member, the first inorganic dielectric layer, the second wafer, the second connecting member and the second inorganic dielectric layer. Embodiments of the present application reduce the thickness of the packaging structure and improve the reliability of the packaging structure.

Description

Technical Field

[0001] Embodiments of this application relate to packaging structures and methods of forming the same. Background Technology

[0002] As electronic devices become thinner and lighter, semiconductor packaging technology faces increasingly higher requirements for integration and smaller package size. In stacked packaging, how to reduce the thickness of the package structure while ensuring package reliability has become a pressing technical challenge for the industry. Summary of the Invention

[0003] This application provides a packaging structure, including: a first wafer; a second wafer disposed above the first wafer, with the back side of the second wafer facing the front side of the first wafer, the second wafer being offset horizontally relative to the first wafer such that the front side of the first wafer includes a first overlapping region overlapping the second wafer in a vertical direction and a first non-overlapping region offset from the second wafer in a vertical direction; a first inorganic dielectric layer covering the first overlapping region and the first non-overlapping region; a second inorganic dielectric layer covering the entire back side of the second wafer, the portion of the first inorganic dielectric layer covering the first overlapping region being mixed and bonded with the second inorganic dielectric layer; a circuit layer disposed above the second wafer; a first connector electrically connecting the first non-overlapping region and the circuit layer; a second connector electrically connecting the front side of the second wafer facing the circuit layer and the circuit layer; and a molding layer below the circuit layer and covering the first wafer, the first connector, the first inorganic dielectric layer, the second wafer, the second connector, and the second inorganic dielectric layer.

[0004] In some embodiments, the total thickness of the first inorganic dielectric layer and the second inorganic dielectric layer at the first overlapping region is D1, and the thickness of the first inorganic dielectric layer and the thickness of the second inorganic dielectric layer outside the first overlapping region are D2, where D1 > D2.

[0005] In some embodiments, D1 = 2 × D2 ± 20%.

[0006] In some embodiments, two opposing sidewalls of the second wafer are aligned with corresponding sidewalls of the first wafer, and two other sidewalls of the second wafer are offset from corresponding sidewalls of the first wafer, or all sidewalls of the second wafer are offset from corresponding sidewalls of the first wafer.

[0007] In some embodiments, the first inorganic dielectric layer and the second inorganic dielectric layer contact the molding layer relative to the exposed surfaces of the first wafer and the second wafer, and the adhesion between the molding layer and the first inorganic dielectric layer and the second inorganic dielectric layer is greater than the adhesion between the molding layer and the first wafer and the second wafer.

[0008] In some embodiments, the first inorganic dielectric layer and the second inorganic dielectric layer cover a portion of the turning angle of the molding layer.

[0009] In some embodiments, within the molding layer, the surface of the molding layer extending in the horizontal direction is offset from the first wafer and the second wafer.

[0010] In some embodiments, the packaging structure further includes: a first pad disposed in the first inorganic dielectric layer and connecting the first connector and the first input / output layer of the first wafer, wherein the first inorganic dielectric layer covers the first input / output layer.

[0011] In some embodiments, the packaging structure further includes: a first positioning structure disposed in the first inorganic dielectric layer, side by side and spaced apart from the first pad, wherein the first positioning structure is disposed in the first non-overlapping region.

[0012] In some embodiments, the materials of the first inorganic dielectric layer and the second inorganic dielectric layer are SiO2, SICN, or SiN, and the materials of the first wafer and the second wafer include Si.

[0013] In some embodiments, the package structure further includes: a third wafer disposed between the second wafer and the circuit layer, wherein the back side of the third wafer faces the front side of the second wafer, the third wafer being offset horizontally relative to the second wafer such that the front side of the second wafer includes a second overlapping region overlapping the third wafer in a vertical direction and a second non-overlapping region offset from the third wafer in a vertical direction, the second connector electrically connecting the second non-overlapping region and the circuit layer; a third inorganic dielectric layer covering the second overlapping region and the second non-overlapping region; a fourth inorganic dielectric layer covering the entire back side of the third wafer, the portion of the third inorganic dielectric layer covering the second overlapping region being mixed-bonded with the fourth inorganic dielectric layer; and a third connector electrically connecting the front side of the third wafer facing the circuit layer and the circuit layer.

[0014] In some embodiments, the first connector and the second connector are leads extending along the vertical direction.

[0015] In some embodiments, the thickness of the first wafer and the second wafer is 20 μm to 50 μm.

[0016] In some embodiments, the thickness of the first inorganic dielectric layer and the second inorganic dielectric layer is 0.5 ± 10% μm.

[0017] In some embodiments, the packaging structure further includes: a metal barrier layer, the bottom surface of the molding layer being flush with the back surface of the first wafer opposite to the front surface, the metal barrier layer being disposed on the bottom surface of the molding layer and the back surface of the first wafer; and a metal-graphene composite layer disposed on the surface of the metal barrier layer opposite to the first wafer, the metal-graphene composite layer including two metal layers and a graphene sheet sandwiched between the two metal layers.

[0018] In some embodiments, the edges of the metal barrier layer, the two metal layers, and the graphene sheet are aligned with the sidewalls of the molding layer.

[0019] In some embodiments, the material of the metal barrier layer is Ti, and the material of the two metal layers is Cu.

[0020] Embodiments of this application also provide a method for forming a package structure, comprising: forming a first inorganic dielectric layer on a first input / output layer of a first wafer, and forming a first pad electrically connected to the first input / output layer in the first inorganic dielectric layer; forming a third inorganic dielectric layer on a second input / output layer of a second wafer, and forming a second pad electrically connected to the second input / output layer in the third inorganic dielectric layer; forming a second inorganic dielectric layer on the back side of the second wafer opposite to the second input / output layer; disposing the second wafer on the first wafer, wherein the first inorganic dielectric layer and the second inorganic dielectric layer are mixed and bonded, and the second wafer is offset relative to the first wafer in the horizontal direction. The first wafer is moved such that its front side includes a first overlapping region that overlaps with the second wafer in a vertical direction and a first non-overlapping region that is offset from the second wafer in a vertical direction, with the first inorganic dielectric layer exposed in the first non-overlapping region; a first connector connecting the first pad and a second connector connecting the second pad are formed; a molding layer is formed covering the first wafer, the first connector, the first inorganic dielectric layer, the second wafer, the second connector, and the second inorganic dielectric layer, and the first connector and the second connector are exposed in the molding layer; a circuit layer is formed on the molding layer, the circuit layer connecting the first connector and the second connector.

[0021] In some embodiments, the first inorganic dielectric layer, the second inorganic dielectric layer, and the third inorganic dielectric layer are formed by a chemical vapor deposition process.

[0022] In some embodiments, the method further includes: forming a metal barrier layer on a back side of the first wafer exposed relative to the molding layer and on the molding layer, the back side of the first wafer being opposite to the first input / output layer and flush with the molding layer; forming a metal-graphene composite layer on the surface of the metal barrier layer opposite to the first wafer, the metal-graphene composite layer comprising two metal layers and a graphene sheet sandwiched between the two metal layers.

[0023] The embodiments of this application reduce the thickness of the packaging structure and improve the reliability of the packaging structure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It is worth noting that, according to industry standard practice, the various components are not drawn to scale and are only used for illustrative purposes. In fact, for the sake of clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0025] Figure 1 A semiconductor package structure according to some embodiments is shown.

[0026] Figure 2 The packaging structure according to other embodiments of this application is shown.

[0027] Figure 3 The image shows DAF applying force to a wafer.

[0028] Figure 4 This demonstrates the force exerted on the wafer by the inorganic dielectric layer.

[0029] Figure 5 The diagram shows the variation of internal stress in the wafer caused by DAF and SiO2 when the wafer thickness is different.

[0030] Figure 6 The front side of the first inorganic dielectric layer is shown, which is attached to the first wafer.

[0031] Figure 7 The back and front sides of the inorganic dielectric layer bonded to the second wafer are shown.

[0032] Figure 8 The first wafer is shown.

[0033] Figure 9 The material forming the first pad is shown.

[0034] Figure 10 The chemical mechanical polishing process is shown.

[0035] Figure 11 It shows that Figure 10 The structure shown is placed on the first tape.

[0036] Figure 12 Multiple first wafers are shown.

[0037] Figure 13 The first wafer and the first inorganic dielectric layer are shown.

[0038] Figure 14 The provision of a second wafer is shown.

[0039] Figure 15 The material forming the second pad is shown.

[0040] Figure 16 The chemical mechanical polishing process is shown.

[0041] Figure 17 The formation of the second DAF and the first carrier are shown.

[0042] Figure 18 The back side of the second wafer is shown being thinned.

[0043] Figure 19 The formation of the second inorganic dielectric layer is shown.

[0044] Figure 20 The planarized second inorganic dielectric layer is shown.

[0045] Figure 21 The diagram shows the removal of the first carrier and the second DAF, with the resulting structure placed on a second tape.

[0046] Figure 22 Multiple second wafers are shown.

[0047] Figure 23 The second wafer, the third inorganic dielectric layer, and the second inorganic dielectric layer are shown.

[0048] Figure 24 The diagram shows the placement of the first wafer on the second carrier.

[0049] Figure 25 The diagram shows the second, third, and fourth wafers stacked on top of the first wafer in sequence.

[0050] Figure 26 The connection is shown.

[0051] Figure 27 The formation of the molding layer is shown.

[0052] Figure 28 The planarized molding layer is shown.

[0053] Figure 29 The circuit layer and solder balls are shown.

[0054] Figure 30 The fourth DAF and the third carrier are shown to be formed on the line layer.

[0055] Figure 31 Showing flip Figure 30 The structure shown is modified by removing the second carrier and the third DAF.

[0056] Figure 32 The removal of the temporary molding layer is shown.

[0057] Figure 33 The removal of the fourth DAF and the third vector is shown.

[0058] Figure 34A A top view of the packaging structure is shown.

[0059] Figure 34B It shows the relationship with Figure 34A Different implementations.

[0060] Figure 35 The diagram shows the variation of internal stress in a wafer caused by inorganic dielectric layers of different materials when the wafer thickness varies.

[0061] Figure 36 The phone's cooling system is shown.

[0062] Figure 37 and Figure 38 This demonstrates the use of a heat spreader to dissipate heat from the package structure.

[0063] Figure 39 A top view of the packaging structure is shown.

[0064] Figure 40 The packaging structure according to other embodiments of this application is shown.

[0065] Figure 41 The image shows a molded layer covering the wafer and connectors.

[0066] Figure 42 The back side of the first wafer is shown.

[0067] Figure 43 The diagram shows a deposited metal barrier layer, a metal layer, a graphene sheet, and a metal layer.

[0068] Figure 44It shows that Figure 43 The structure shown is flipped and joined to the fourth carrier.

[0069] Figure 45 The exposed connector is shown.

[0070] Figure 46 The circuit layer and solder balls are shown.

[0071] Figure 47 The removal of the fourth carrier is shown.

[0072] Figure 48 The packaging structure according to an embodiment of this application is shown. Detailed Implementation

[0073] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0074] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are represented by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0075] The terms “approximately,” “generally,” “substantial,” “substantial,” “about,” and “approximately” used herein are used to indicate and explain minor variations. For example, when used in conjunction with numerical values, the above terms may refer to a range of variation less than or equal to ±10% of the corresponding numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another embodiment, the thickness of a film or layer being “substantially uniform” may refer to the average thickness of the film or layer being less than or equal to ±10% of the standard deviation, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces that are within 50 μm along the same plane (such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane). If, for example, two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm, then the two components can be considered "substantially aligned." If the angle between two surfaces or components is, for example, 90° ± 10° (such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°), then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "approximately," "generally," "substantially," "materially," "about," and "approximately" can refer to the exact occurrence of the event or situation as well as the very close approximation of its occurrence.

[0076] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “backside,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0077] For ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0078] Figure 1 A semiconductor package structure according to some embodiments is shown, illustrating a technique of vertical fan-out (VFO) via a die-attach film (DAF). A first die 11, a second die 12, a third die 13, and a fourth die 14 are connected to a circuit layer 50 via first connectors 61, second connectors 62, third connectors 63, and fourth connectors 64, respectively. In some embodiments, first connectors 61, second connectors 62, third connectors 63, and fourth connectors 64 are vertically extending wires that directly connect the bottom surface of each die 11, second die 12, third die 13, and fourth die 14 to the circuit layer 50, achieving a 27% thickness reduction compared to package structures using conventional wires (wires with curvature and arc height). In some embodiments, the circuit layer 50 is a redistribution layer (RDL). In some embodiments, the first die 11, second die 12, third die 13, and fourth die 14 are memory dies, such as dynamic random access memory (DRAM) dies.

[0079] In some embodiments, a wafer bonding film 1 is used to bond stacked first wafers 11, second wafers 12, third wafers 13, and fourth wafers 14. The thickness of the wafer bonding film 1 is difficult to reduce, and its thickness is, for example, >10 μm. Taking a package structure with four stacked wafers as an example, the wafer bonding film 1 occupies a thickness of at least 30 μm. In some embodiments, the thickness of the circuit layer 50 is, for example, 40 μm, the total thickness of the structure on the circuit layer 50 (which is also the thickness of the molding layer 52) is, for example, 240 μm, and the thickness of the solder balls 90 is, for example, 200 μm.

[0080] In some embodiments, the main material of the first wafer 11, the second wafer 12, the third wafer 13, and the fourth wafer 14 is Si, and the wafer bonding film 1 is a polymer material (such as polyimide (PI), epoxy resin, etc.). A wafer bonding film 1 with a small coefficient of thermal expansion (CTE) is selected, and the thickness of the first wafer 11, the second wafer 12, the third wafer 13, and the fourth wafer 14 is maintained at 45 μm to 50 μm to balance the stress in the packaging structure.

[0081] From the bending stress formula It can be seen that as the first wafer 11, the second wafer 12, the third wafer 13, and the fourth wafer 14 become thinner, the stress inside the wafer increases. Here, M represents the bending moment, y represents the distance, b represents the cross-sectional width, and t represents the cross-sectional thickness. When the wafer thickness decreases, the bending stress increases exponentially under the same bending moment.

[0082] On the other hand, the mismatch in the coefficients of thermal expansion between the wafer bonding film 1 and the wafer, and the mismatch in their expansion rates, will be amplified as the temperature increases, which will increase the risk of chipping and cracking of the wafer when the molding process 52 is performed.

[0083] Figure 2 A package structure 100 according to other embodiments of this application is illustrated, wherein a hybrid bond vertical fan-out (VFO) technique is shown. A first wafer 11, a second wafer 12, a third wafer 13, and a fourth wafer 14 are bonded using inorganic dielectric layers. In some embodiments, a first inorganic dielectric layer 21 covers the front side (active side) of the first wafer 11, and a second inorganic dielectric layer 22 covers the back side (passive side) of the second wafer 12. The first inorganic dielectric layer 21 and the second inorganic dielectric layer 22 are hybrid bonded to bond the first wafer 11 and the second wafer 12. A third inorganic dielectric layer 23 covers the front side of the second wafer 12, and a fourth inorganic dielectric layer 24 covers the back side of the third wafer 13. The third inorganic dielectric layer 23 and the fourth inorganic dielectric layer 24 are hybrid bonded to bond the second wafer 12 and the third wafer 13. A fifth inorganic dielectric layer 25 covers the front side of the third wafer 13, and a sixth inorganic dielectric layer 26 covers the back side of the fourth wafer 14. The fifth and sixth inorganic dielectric layers 25 and 26 are mixed and bonded to bond the third wafer 13 and the fourth wafer 14. Some embodiments of this application use stacked four wafers as an example; in other embodiments, other numbers of wafers can be stacked. In some embodiments, the material of the inorganic dielectric layer is, for example, SiO2, SICN, or SiN.

[0084] The inorganic dielectric layer has a lower coefficient of thermal expansion than the wafer bonding film 1, making its coefficient of thermal expansion a better match for the wafer. Furthermore, the inorganic dielectric layer is only about 0.5 μm thick, compared to... Figure 1 The illustrated embodiment can reduce the overall thickness of the package structure 100. Furthermore, the stress of the formed inorganic dielectric layer can be adjusted by modifying the parameters of the plasma-enhanced chemical vapor deposition (PECVD) process to balance the stress within the thinned wafer. In some embodiments, the thickness of the circuit layer 50 is, for example, 40 μm, and the total thickness of the structure on the circuit layer 50 (which is also the thickness of the molding layer 52) is, for example, 200 μm (compared to...). Figure 1 The embodiment shown is small), and the thickness of the solder ball 90 is, for example, 200 μm.

[0085] Using the biaxial thermal stress formula Calculating the internal stress of different materials, assuming the material is heated to 125℃ by a thermal process and then returned to room temperature of 25℃, with a temperature difference ΔT of 100℃, it can be found that the internal stress of SiO2 will be less than that of DAF. E f Representing the elastic modulus / Young's modulus, the elastic modulus of Si is 130 GPa, that of DAF is 3 GPa, and that of SiO2 is 70 GPa. α f α represents the thermal expansion coefficient of DAF and SiO2. s The coefficient of thermal expansion of Si is 2.6 ppm / ℃, that of DAF is 70 ppm / ℃, and that of SiO2 is 0.5 ppm / ℃. f The Poisson's ratio is represented by 0.28 for Si, 0.35 for DAF, and 0.17 for SiO2.

[0086] The internal stress of DAF is:

[0087] .

[0088] The internal stress of SiO2 is:

[0089] .

[0090] At the same wafer thickness (e.g., 50 μm), since the thickness of SiO2 material is much thinner than that of DAF, calculations show that, compared to using DAF to bond the wafer, the force of SiO2 on the wafer (the internal stress of SiO2 multiplied by the thickness of SiO2) is reduced to 2.9% of the force of DAF on the wafer (the internal stress of DAF multiplied by the thickness of DAF), which significantly reduces the risk of wafer breakage.

[0091] Among them, such as Figure 3 As shown, the force exerted by DAF 1 on the wafer (e.g., the first wafer 11) is:

[0092] .

[0093] like Figure 4 As shown, the force exerted by SiO2 (e.g., the first inorganic dielectric layer 21) on the wafer (e.g., the first wafer 11) is:

[0094] .

[0095] Based on the principle of action and reaction, the force F exerted by the DAF on the wafer... DAF Equal to the force F exerted by the chip on the DAF Si ,Right now ,get , where t DAF σ represents the thickness of the DAF.Si t represents the internal stress of the wafer. Si This represents the thickness of the chip.

[0096] As the wafer thickness decreases, the internal stress on the wafer increases, raising the probability of wafer breakage. When the wafer thickness is reduced from 50μm to 20μm, the internal stress on the wafer increases by 2.5 times.

[0097] Figure 5 The graph shows the variation of internal stress in the wafer caused by DAF and SiO2 with different wafer thicknesses, where line 501 represents DAF and line 502 represents SiO2. The horizontal axis represents the wafer thickness in μm, and the vertical axis represents the internal stress in MPa. The thinner the wafer, the more significant the difference in internal stress caused by DAF and SiO2.

[0098] The embodiments of this application are not limited to the illustrated package structure 100, and can be applied to FOWLP (Fan-Out Wafer-Level Packaging) and FOPLP (Fan-Out Panel-Level Packaging) package structures. The embodiments of this application reduce the thickness of the package structure 100, or allow more chips to be stacked within the limited thickness of the package structure 100.

[0099] In some embodiments, for the first wafer 11 and the fourth wafer 14, an inorganic dielectric layer is bonded to one side of the wafer. Figure 6 For example, the first inorganic dielectric layer 21 is bonded to the front side of the first wafer 11, and the first inorganic dielectric layer 21 covers the first input / output layer 81 of the first wafer 11. In other embodiments, the inorganic dielectric layer may also be bonded to both sides of the fourth wafer 14. For the second wafer 12 and the third wafer 13, the inorganic dielectric layer is bonded to both sides of the wafer. Figure 7 For example, the second inorganic dielectric layer 22 is attached to the back side of the second wafer 12, and the third inorganic dielectric layer 23 is attached to the front side of the second wafer 12, covering the second input / output layer 82 of the second wafer 12. That is, for wafers located in the middle position (excluding the top and bottom layers), the inorganic dielectric layer covers both the front side (avoiding the electrical connections of the input / output layer) and the back side. Therefore, the areas on the front and back sides of the wafer located in the middle position that do not overlap with other wafers are covered by the inorganic dielectric layer. In some embodiments, the thickness of the wafers (first wafer 11, second wafer 12, third wafer 13, and fourth wafer 14) is 20 μm to 50 μm.

[0100] According to some embodiments, a method is provided for bonding a first wafer 11 and a fourth wafer 14 using an inorganic dielectric layer. The inorganic dielectric layer is bonded to the front side of the first wafer 11 and the back side of the fourth wafer 14.

[0101] Taking the first chip 11 as an example, Figure 8 A first wafer 110 is shown, and a first input / output layer 81 of the first wafer 110 includes a first electrical connector 811 and a first dielectric layer 812. In some embodiments, the first electrical connector 811 is made of copper, and the first dielectric layer 812 is made of polyimide (PI). A first inorganic dielectric layer 21 is formed by chemical vapor deposition (CVD), which covers the first dielectric layer 812 and exposes the first electrical connector 811.

[0102] Since the first inorganic dielectric layer 21 covers the first dielectric layer 812, after the subsequent molding process, the first inorganic dielectric layer 21 contacts the molding layer 52, replacing the direct contact between the first dielectric layer 812 and the molding layer 52. This reduces the likelihood of the first dielectric layer 812 absorbing moisture (compared to the first inorganic dielectric layer 21) and causing a popcorn effect with the molding layer 52 during subsequent thermal processes, thus preventing cracking within the encapsulation structure 100.

[0103] Figure 9 A first pad material 710 is shown formed on the first electrical connector 811 and the first inorganic dielectric layer 21. In some embodiments, the first pad material 710 is copper.

[0104] Figure 10 The illustration shows a chemical mechanical polishing (CMP) process exposing a first inorganic dielectric layer 21, with the remaining first pad material 710 forming a first pad 71. The first pad 71 is disposed within the first inorganic dielectric layer 21 and the first input / output layer 81 of the first wafer 11, to electrically connect the first electrical connector 811 of the first input / output layer 81 to the first connector 61 in a subsequent step. The first inorganic dielectric layer 21 covers the first dielectric layer 812 of the first input / output layer 81.

[0105] Figure 11 It shows that Figure 10 The structure shown is placed on the first tape 901, and the first DAF 921 is bonded to the first wafer 110 and the first tape 901.

[0106] Figure 12 The process of performing a monolithic process is shown to obtain multiple first wafers 11.

[0107] Figure 13The diagram shows the first wafer 11 and the first inorganic dielectric layer 21 attached to the front side of the first wafer 11 after the monolithic process.

[0108] According to some embodiments, a method is provided for bonding a second wafer 12 and a third wafer 13 using an inorganic dielectric layer.

[0109] Taking the second chip 12 as an example, Figure 14 A second wafer 120 is shown, wherein a second input / output layer 82 of the second wafer 120 includes a second electrical connector 821 and a second dielectric layer 822. In some embodiments, the material of the second electrical connector 821 includes copper, and the material of the second dielectric layer 822 includes polyimide (PI). A third inorganic dielectric layer 23 is formed by chemical vapor deposition (CVD), which covers the second dielectric layer 822 and exposes the second electrical connector 821.

[0110] Since the third inorganic dielectric layer 23 covers the second dielectric layer 822, after the subsequent molding process, the third inorganic dielectric layer 23 contacts the molding layer 52, replacing the direct contact between the second dielectric layer 822 and the molding layer 52. This reduces the likelihood of the second dielectric layer 822 absorbing moisture (compared to the second inorganic dielectric layer 22) and causing a "popcorn" effect with the molding layer 52 during subsequent thermal processes, thus preventing cracking within the package structure 100.

[0111] Figure 15 A second pad material 720 is shown formed on the second electrical connector 831 and the third inorganic dielectric layer 23. In some embodiments, the second pad material 720 is copper.

[0112] Figure 16 The illustration shows the application of a chemical mechanical polishing (CMP) process to expose a third inorganic dielectric layer 23, with the remaining second pad material 720 forming the second pad 72.

[0113] Figure 17 The second DAF 922 and the first carrier 931 are shown to be formed on the third inorganic dielectric layer 23.

[0114] Figure 18 Showing flip Figure 17 The structure shown thins the back side of the second wafer 120.

[0115] Figure 19 The process of performing chemical vapor deposition (CVD) is shown to form a second inorganic dielectric layer 22 on the back side of the second wafer 120.

[0116] Figure 20The second inorganic dielectric layer 22 is planarized by performing a chemical mechanical polishing (CMP) process.

[0117] Figure 21 The diagram shows the removal of the first carrier 931 and the second DAF 922, with the resulting structure placed on the second tape 902.

[0118] Figure 22 The process of performing a monolithic process is shown to obtain multiple second wafers 12.

[0119] Figure 23 The diagram shows the second wafer 12 after the monolithic process, and the third inorganic dielectric layer 23 attached to the front side of the second wafer 12 and the second inorganic dielectric layer 22 attached to the back side of the second wafer 12.

[0120] According to some embodiments, a method for forming the encapsulation structure 100 is provided.

[0121] Figure 24 The diagram shows the placement of a first wafer 11 on a second carrier 201, a third DAF 211, and a temporary molding layer 51.

[0122] Figure 25 The diagram illustrates the sequential stacking of a second wafer 12, a third wafer 13, and a fourth wafer on a first wafer 11. Two inorganic dielectric layers are mixed and bonded between adjacent wafers to secure the stacked wafers. Consequently, the thickness of the inorganic dielectric layer in the overlapping region between adjacent wafers is greater than the thickness of the inorganic dielectric layer in the non-overlapping region.

[0123] Taking the first wafer 11 and the second wafer 12 as examples, the total thickness of the first inorganic dielectric layer 21 and the second inorganic dielectric layer 22 in the first overlapping region 31 is D1, and the thickness of the first inorganic dielectric layer 21 and the thickness of the second inorganic dielectric layer 22 outside the first overlapping region 31 are D2, where D1 > D2. In some embodiments, considering the machine capability, the tolerance of the thickness of a single inorganic dielectric layer is ±10%, and D1 = 2 × D2 ± 20%, that is, the thickness of the inorganic dielectric layer in the overlapping region is twice the thickness of a single inorganic dielectric layer ± 20%. In some embodiments, D2 = 0.5 ± 10% μm.

[0124] Figure 26 The diagram shows the formation of a first connector 61, a second connector 62, a third connector 63, and a fourth connector 64.

[0125] Figure 27The molding layer 52 is shown. Since the adhesion between the molding layer 52 and the inorganic dielectric layer is greater than the adhesion between the molding layer 52 and the wafer, forming inorganic dielectric layers on both the front and back sides of the wafer can improve the structural stability of the package structure 100. In some embodiments, since the back side of the first wafer 11 is exposed relative to the molding layer 52 in the finished product of the package structure 100, it is not necessary to form an inorganic dielectric layer on the back side of the first wafer 11. In some embodiments, if the back side of the first wafer 11 is embedded in the molding layer 52 in the finished product of the package structure 100, an inorganic dielectric layer can be formed on the back side of the first wafer 11. Taking the first wafer 11 and the second wafer 12 as examples, the first inorganic dielectric layer 21 and the second inorganic dielectric layer 22 contact the molding layer 52 on surfaces exposed to the first wafer 11 and the second wafer 12, and the adhesion between the molding layer 52 and the first inorganic dielectric layer 21 and the second inorganic dielectric layer 22 is greater than the adhesion between the molding layer 52 and the first wafer 11 and the second wafer 12.

[0126] In some embodiments, since inorganic dielectric layers are formed on the facing surfaces of adjacent wafers, and these inorganic dielectric layers are also located in the non-overlapping region of the two wafers, the turning angles of the molding layer 52 at the offset regions of the two wafers are covered by the inorganic dielectric layers, rather than being directly located on the wafer surface. Stress typically concentrates at the turning angles of the molding layer 52. By structurally making the turning angles of the molding layer 52 an inorganic dielectric layer, rather than the wafer itself, stress concentration on the wafer and potential damage to the wafer is avoided. Taking the first wafer 11 and the second wafer 12 as examples, the first inorganic dielectric layer 21 and the second inorganic dielectric layer 22 cover a portion of the turning angles of the molding layer 52. The first turning angle 271 of the molding layer 52 located below the second wafer 12 is covered by the first inorganic dielectric layer 21 and the second inorganic dielectric layer 22, compared to... Figure 1 The embodiment (where the turning angle of the molding layer 52 is located at the junction of the wafer and the DAF) improves structural stability. Furthermore, since the modulus of the inorganic dielectric layer is located between the wafer and the molding layer 52, it can provide a buffer between them.

[0127] Within the molding layer 52, the horizontally extending surface of the molding layer 52 is offset from the wafer, and an inorganic dielectric layer lies on the same plane as this surface. Therefore, even if a crack exists on the horizontally extending surface of the molding layer 52, the crack will not extend directly into the wafer, but will be blocked by the inorganic dielectric layer. Taking the first wafer 11 and the second wafer 12 as examples, the horizontally extending surface of the molding layer 52 is offset from the first wafer 11 and the second wafer 12, and the first inorganic dielectric layer 21 and the second inorganic dielectric layer 22, after being mixed and bonded, are located on the same plane as this surface.

[0128] Figure 28A planarized molding layer 52 is shown to expose the first connector 61, the second connector 62, the third connector 63, and the fourth connector 64.

[0129] Figure 29 The circuit layer 50 and solder balls 90 are shown.

[0130] Figure 30 The fourth DAF 212 and the third carrier 202 are shown to be formed on the line layer 50.

[0131] Figure 31 Showing flip Figure 30 The structure shown is modified by removing the second carrier 201 and the third DAF 211.

[0132] Figure 32 The removal of the temporary molding layer 51 is shown.

[0133] Figure 33 It shows that Figure 32 The structure shown is flipped and placed on the third tape 903, and the fourth DAF 212 and the third carrier 202 are removed.

[0134] An embodiment of this application provides a packaging structure 100, including: a first wafer 11; and a second wafer 12 disposed above the first wafer 11, with the back side of the second wafer 12 facing the front side of the first wafer 11. The second wafer 12 is offset from the first wafer 11 in the horizontal direction, such that the front side of the first wafer 11 includes a first overlapping region 31 that overlaps with the second wafer 12 in the vertical direction, and a first non-overlapping region 41 that is offset from the second wafer 12 in the vertical direction.

[0135] The first inorganic dielectric layer 21 covers the first overlapping region 31 and the first non-overlapping region 41. The second inorganic dielectric layer 22 covers the entire back side of the second wafer 12, and the portion of the first inorganic dielectric layer 21 covering the first overlapping region 31 is mixed and bonded with the second inorganic dielectric layer 22.

[0136] A circuit layer 50 is disposed above the second wafer 12. A first connector 61 electrically connects the first non-overlapping region 41 and the circuit layer 50. A second connector 62 electrically connects the front side of the second wafer 12 facing the circuit layer 50 and the circuit layer 50. A molding layer 52 is below the circuit layer 50 and covers the first wafer 11, the first connector 61, the first inorganic dielectric layer 21, the second wafer 12, the second connector 62, and the second inorganic dielectric layer 22.

[0137] A third wafer 13 is disposed between the second wafer 12 and the circuit layer 50, with the back side of the third wafer 13 facing the front side of the second wafer 12. The third wafer 13 is offset horizontally relative to the second wafer 12, such that the front side of the second wafer 12 includes a second overlapping region 32 that overlaps with the third wafer 13 in the vertical direction, and a second non-overlapping region 42 that is offset from the third wafer 13 in the vertical direction. A second connector 62 electrically connects the second non-overlapping region 42 and the circuit layer 50. A third inorganic dielectric layer 23 covers the second overlapping region 32 and the second non-overlapping region 42. A fourth inorganic dielectric layer 24 covers the entire back side of the third wafer 13, and the portion of the third inorganic dielectric layer 23 covering the second overlapping region 32 is mixed-bonded with the fourth inorganic dielectric layer 24. A third connector 63 electrically connects the front side of the third wafer 13 facing the circuit layer 50 and the circuit layer 50.

[0138] Some embodiments of this application also provide a method for forming a package structure 100, comprising: forming a first inorganic dielectric layer 21 on a first input / output layer 81 of a first wafer 11, and forming a first pad 71 electrically connected to the first input / output layer 81 in the first inorganic dielectric layer 21; forming a third inorganic dielectric layer 23 on a second input / output layer 82 of a second wafer 12, and forming a second pad 72 electrically connected to the second input / output layer 82 in the third inorganic dielectric layer 23; and forming a second inorganic dielectric layer 22 on the back side of the second wafer 12 opposite to the second input / output layer 82. A second wafer 12 is disposed on a first wafer 11. A first inorganic dielectric layer 21 and a second inorganic dielectric layer 22 are mixed and bonded. The second wafer 12 is offset from the first wafer 11 in the horizontal direction, such that the front side of the first wafer 11 includes a first overlapping region 31 that overlaps with the second wafer 12 in the vertical direction and a first non-overlapping region 41 that is offset from the second wafer 12 in the vertical direction. The first inorganic dielectric layer 21 is exposed in the first non-overlapping region 41. A first connector 61 connecting the first pad 71 and a second connector 62 connecting the second pad 72 are formed. A molding layer 52 is formed covering the first wafer 11, the first connector 61, the first inorganic dielectric layer 21, the second wafer 12, the second connector 62, and the second inorganic dielectric layer 22, exposing the first connector 61 and the second connector 62 to the molding layer 52. A circuit layer 50 is formed on the molding layer 52, and the circuit layer 50 connects the first connector 61 and the second connector 62.

[0139] In some embodiments, a first inorganic dielectric layer 21, a second inorganic dielectric layer 22, and a third inorganic dielectric layer 23 are formed by a chemical vapor deposition process.

[0140] Figure 34AA top view of the package structure 100 is shown, where the portion of the circuit layer 50, solder balls 90, and molding layer 52 located above the wafer is not shown. In some embodiments, a positioning structure is provided on each wafer, the positioning structure being located in the same layer as the pads, and the positioning structure is not covered by other wafers. For example, a first positioning structure 91 on a first wafer 11 is located in the same layer as a first pad 71, and the first positioning structure 91 and the first pad 71 are disposed side by side and spaced apart from each other in a first inorganic dielectric layer 21. The first positioning structure 91 is located in a first non-overlapping region 41 of the first wafer 11 and is not covered by the second wafer 12, the third wafer 13, and the fourth wafer 14. The positioning structure is used to identify the position of the wafers to make the wafer stacking process more accurate. In some embodiments, the positioning structure is not limited to the cross-shaped and L-shaped shapes shown in the figure, but can also be triangular or rectangular, etc., and the shape of the positioning structure can be adjusted according to different machines.

[0141] In some embodiments, multiple wafers in Figure 34A Aligned vertically, and Figure 34A They are offset from each other in the lateral direction. Taking the first wafer 11 and the second wafer 12 as examples, two opposite sidewalls of the second wafer 12 are aligned with the corresponding sidewalls of the first wafer 11, and the other two sidewalls of the second wafer 12 are offset from the corresponding sidewalls of the first wafer 11.

[0142] Figure 34B It shows the relationship with Figure 34A In other embodiments, multiple wafers are in... Figure 34B The sides can also be offset from each other in the longitudinal direction to further increase the contact area between the inorganic dielectric layer and the molding layer 52. Taking the first wafer 11 and the second wafer 12 as examples, all sidewalls of the second wafer 12 are offset from the corresponding sidewalls of the first wafer 11.

[0143] Figure 35 The diagram shows line graphs illustrating the changes in internal stress of a wafer caused by inorganic dielectric layers of different materials when the wafer thickness varies. The material of the inorganic dielectric layer is not limited to SiO2; it can be other inorganic thin films. Other materials for the inorganic dielectric layer include SiN and SiCN. The elastic modulus of SiN is 185 GPa, while that of SiCN is 110 GPa; the coefficient of thermal expansion of SiN is 2.8 ppm / ℃, while that of SiCN is 4.0 ppm / ℃; the Poisson's ratio of SiN is 0.25, while that of SiCN is 0.28. Figure 35In the diagram, line 501 represents DAF, line 502 represents SiO2, line 503 represents SiCN, and line 504 represents SiN. The horizontal axis represents the wafer thickness in μm, and the vertical axis represents the wafer's internal stress in MPa. The wafer's internal stress is minimized when the inorganic dielectric layer is made of SiN. In some embodiments, multiple inorganic dielectric layers on multiple wafer surfaces are made of the same material. Taking the first wafer 11 and the second wafer 12 as examples, the first inorganic dielectric layer 21, the second inorganic dielectric layer 22, and the third inorganic dielectric layer 23 are made of the same material, such as SiO2, SICN, or SiN.

[0144] The packaging structure 100 of the embodiments of this application can be used in mobile phone memory.

[0145] Figure 36 The diagram illustrates a high-end mobile phone cooling system where a vapor chamber (VC) 350 replaces a thermal pad to enhance heat conduction. The VC 350 is first soldered to the housing 356 and then dissipates heat through contact with the battery 352 and the integrated fan-out package-on-package (InFO-PoP) 358 (including the logic chip 359) package structure 100. A problem arises from the contact thermal resistance at the interface between the different materials in the heat dissipation package structure 100, which reduces the effectiveness of heat dissipation.

[0146] Figure 37 and Figure 38 This illustrates the use of a heat spreader 350 to dissipate heat from the package structure 100. Figure 37 In one embodiment, multiple wafers are embedded within the molding layer 52. Figure 38 In one embodiment, the seventh inorganic dielectric layer 27 on the back side of the first wafer 11 is exposed to the molding layer 52. Figure 37 and Figure 38 The arrows illustrate the heat conduction path. Because the heat from the encapsulation structure 100 is transferred longitudinally to the heat spreader 35, therefore... Figure 37 The embedded embodiment shown, or Figure 38 In the exposed embodiment shown, the heat dissipation area of ​​the entire package structure 100 is limited, and heat dissipation can only be carried out locally, which cannot maximize the heat conduction area and has limited heat dissipation efficiency.

[0147] Figure 39 It shows Figure 37 and Figure 38 A top view of the package structure 100 (where the inorganic dielectric layer and molding layer located above the wafer are not shown). In this case, using a common size for mobile phone DRAM packages, the cross-sectional area of ​​a wafer is, for example, 6 x 4 = 24 mm². 2The cross-sectional area of ​​the package structure 100 is, for example, 12 x 7 = 84 mm². 2 According to the heat conduction equation – Fourier's law Where ΔT is the temperature difference, Q is the heat flow, L is the thickness, A is the heat dissipation area, and k is the thermal conductivity of the material. If the heat dissipation area can be expanded from only the first chip 11 to the entire package structure 100, the heat flow Q of the package structure 100 can be increased by 3.5 times.

[0148] Figure 40 The following diagram illustrates a package structure 100 according to other embodiments of this application, and shows that a vapor chamber 350 is used to dissipate heat from the package structure 100. Figure 40 The solid arrows in the diagram illustrate the heat conduction path of the packaging structure. In some embodiments, the surface of the molding layer 52 is flush with the back surface of the first wafer 11, and a metal barrier layer 54 is disposed on both the surface of the molding layer 52 and the back surface of the first wafer 11. A metal-graphene composite layer 56 is disposed on the back of the metal barrier layer 54 opposite to the surface of the first wafer 11. The metal-graphene composite layer 56 includes two metal layers 562 and a graphene sheet 564 sandwiched between the two metal layers 562.

[0149] In some embodiments, the edges of the metal barrier layer 54, the two metal layers 562, and the graphene sheet 564 are aligned with the sidewalls of the molding layer 52. The embodiments of this application utilize the characteristic that graphene has extremely high thermal conductivity (2000–5000 W / (m×K)) in the horizontal direction (within the plane of carbon atom arrangement). First, the first wafer 11 is exposed by grinding, and then a metal barrier layer 54 (e.g., a Ti layer, used to block the diffusion of the metal layer 562) is sequentially deposited using a physical vapor deposition (PVD) process; the metal layer 562 (e.g., a Cu layer, used to attach the graphene sheet 564); the graphene sheet 564 (providing high thermal conductivity in the horizontal direction); and the metal layer 562 (protecting the graphene sheet 564 and preventing it from cracking due to brittleness).

[0150] In some embodiments, the outer layer of the heat spreader 350 is stainless steel, which is a magnetic metal. The metal layer 562 is a highly conductive metal (Cu), which can shield against potential external electromagnetic interference. In other embodiments, the material of the metal layer 562 is not limited to Cu; it can also be other highly thermally conductive metal materials that have good adhesion to the graphene sheet 564.

[0151] According to the formula for thermal resistance per unit area , where t represents thickness and k represents thermal conductivity. For Figure 1 The embodiment shown (directly bonded to the heat spreader 350, therefore the wafer needs to be embedded in the molding layer 52 to avoid damage), interface thermal resistance R total for:

[0152] Among them, R Si R represents the thermal resistance of the first chip 11; Mold This indicates the thermal resistance of the portion of the molding layer 52 located above the first wafer 11; t Si t represents the thickness of the first wafer 11. Mold This indicates the thickness of the portion of the molding layer 52 located above the first wafer 11, in μm; k Si k represents the thermal conductivity of Si. Mold This represents the thermal conductivity of the molding layer 52, expressed in W / (m×K).

[0153] If in Figure 1 In the illustrated embodiment, a layer of DAF 1 is further disposed on the back side of the first wafer 11, and the interface thermal resistance R total for:

[0154] Among them, t DAF This indicates the thickness of DAF 1, in μm; k DAF This represents the thermal conductivity of DAF 1, with units of W / (m×K).

[0155] It is understood that the composite heat dissipation structure (metal layer-graphene sheet-metal layer) of this application can also be used... Figure 1 The illustrated embodiment. For example, the back side of the first wafer 11 is exposed (and coplanar with the molding layer 52), and a metal barrier layer 54, a metal layer 562, a graphene sheet 564, and another metal layer 562 are formed sequentially. For such embodiments and... Figure 40 In the embodiment shown, the interfacial thermal resistance R total for:

[0156] Among them, t Ti t represents the thickness of the metal barrier layer 54. Cu t represents the thickness of metal layer 562. Graphene This indicates the thickness of the graphene sheet 564, in μm; k Ti The thermal conductivity of the metal barrier layer 54 is represented by k. Cu The thermal conductivity of the metal layer 562 is represented by k. Graphene This indicates the thermal conductivity of the graphene sheet 564, expressed in W / (m×K).

[0157] The embodiments of this application are applicable to all InFo-PoP packaging structures for mobile phone chips. The embodiments of this application can improve the interface thermal resistance of mobile phone packaging modules: through the composite heat dissipation structure of this application, the interface thermal resistance of the packaging structure 100 can be reduced from 7 μm to the same module size. 2K / W, 27 m 2 K / W dropped significantly to 0.34 m 2 K / W. The embodiments of this application can also be used in other products, such as 2.5D or silicon photonics (SiPh) products.

[0158] The embodiments of this application also provide Figure 40 Method for forming the encapsulation structure 100.

[0159] Figure 41 The image shows a molding layer 52, a temporary molding layer 51 covering the wafer, and connectors. Figure 41 The steps shown can be performed at any time. Figure 27 Perform the steps shown below.

[0160] Figure 42 The grinding process is shown, exposing the back side of the first wafer 11.

[0161] Figure 43 The diagram shows the sequential deposition of a metal barrier layer 54, a metal layer 562, a graphene sheet 564, and a metal layer 562.

[0162] Figure 44 It shows that Figure 43 The structure shown is flipped and joined to the fourth carrier 411.

[0163] Figure 45 The planarization step is shown, exposing the first connector 61, the second connector 62, the third connector 63, and the fourth connector 64.

[0164] Figure 46 It shows in Figure 45 A circuit layer 50 and solder balls 90 are formed on the structure shown. In some embodiments, the solder balls 90 are controlled collapse chip connection (C4) bumps.

[0165] Figure 47 The removal of the fourth carrier 411 is shown.

[0166] Figure 48 An encapsulation structure 100 according to an embodiment of this application is shown.

[0167] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A packaging structure, characterized in that, include: First chip; A second wafer is disposed above the first wafer, with the back side of the second wafer facing the front side of the first wafer. The second wafer is offset from the first wafer in the horizontal direction, such that the front side of the first wafer includes a first overlapping region that overlaps with the second wafer in the vertical direction and a first non-overlapping region that is offset from the second wafer in the vertical direction. A first inorganic dielectric layer covers the first overlapping region and the first non-overlapping region; A second inorganic dielectric layer covers the entire back side of the second wafer, and a portion of the first inorganic dielectric layer covering the first overlapping region is mixed and bonded with the second inorganic dielectric layer. A circuit layer is disposed above the second wafer; A first connector electrically connects the first non-overlapping region and the circuit layer; The second connector electrically connects the front side of the second wafer facing the circuit layer and the circuit layer; A molding layer is located below the circuit layer and covers the first wafer, the first connector, the first inorganic dielectric layer, the second wafer, the second connector, and the second inorganic dielectric layer.

2. The packaging structure according to claim 1, characterized in that, The total thickness of the first inorganic dielectric layer and the second inorganic dielectric layer in the first overlapping region is D1, and the thickness of the first inorganic dielectric layer and the thickness of the second inorganic dielectric layer outside the first overlapping region are D2, where D1 > D2.

3. The packaging structure according to claim 2, characterized in that, D1 = 2 × D2 ± 20%.

4. The packaging structure according to claim 1, characterized in that, Two opposing sidewalls of the second wafer are aligned with the corresponding sidewalls of the first wafer, and the other two sidewalls of the second wafer are offset from the corresponding sidewalls of the first wafer, or... All sidewalls of the second wafer are offset from the corresponding sidewalls of the first wafer.

5. The packaging structure according to claim 1, characterized in that, The first inorganic dielectric layer and the second inorganic dielectric layer contact the molding layer relative to the exposed surfaces of the first wafer and the second wafer. The adhesion between the molding layer and the first inorganic dielectric layer and the second inorganic dielectric layer is greater than the adhesion between the molding layer and the first wafer and the second wafer.

6. The packaging structure according to claim 1, characterized in that, The first inorganic dielectric layer and the second inorganic dielectric layer cover a portion of the turning angle of the molding layer.

7. The packaging structure according to claim 6, characterized in that, Within the molding layer, the surface of the molding layer extending in the horizontal direction is offset from the first wafer and the second wafer.

8. The packaging structure according to claim 1, characterized in that, Also includes: A first pad is disposed in the first inorganic dielectric layer and connects the first connector and the first input / output layer of the first chip, wherein the first inorganic dielectric layer covers the first input / output layer.

9. The packaging structure according to claim 8, characterized in that, Also includes: A first positioning structure is disposed in the first inorganic dielectric layer, parallel to and spaced apart from the first pad, and the first positioning structure is disposed in the first non-overlapping region.

10. The packaging structure according to claim 1, characterized in that, The materials of the first inorganic dielectric layer and the second inorganic dielectric layer are SiO2, SICN or SiN, and the materials of the first wafer and the second wafer include Si.

11. The packaging structure according to claim 1, characterized in that, Also includes: A third wafer is disposed between the second wafer and the circuit layer, with the back side of the third wafer facing the front side of the second wafer. The third wafer is offset from the second wafer in the horizontal direction, such that the front side of the second wafer includes a second overlapping region that overlaps with the third wafer in the vertical direction and a second non-overlapping region that is offset from the third wafer in the vertical direction. The second connector electrically connects the second non-overlapping region and the circuit layer. A third inorganic dielectric layer covers the second overlapping region and the second non-overlapping region; A fourth inorganic dielectric layer covers the entire back side of the third wafer, and the portion of the third inorganic dielectric layer covering the second overlapping region is mixed and bonded with the fourth inorganic dielectric layer. The third connector electrically connects the front side of the third wafer facing the circuit layer to the circuit layer.

12. The packaging structure according to claim 1, characterized in that, The first connector and the second connector are leads extending along the vertical direction.

13. The packaging structure according to claim 1, characterized in that, The thickness of the first wafer and the second wafer is 20 μm to 50 μm.

14. The packaging structure according to claim 1, characterized in that, The thicknesses of the first inorganic dielectric layer and the second inorganic dielectric layer are 0.5 ± 10% μm.

15. The packaging structure according to claim 1, characterized in that, Also includes: A metal barrier layer is provided on the bottom surface of the molding layer and the back surface of the first wafer opposite to the front surface. A metal-graphene composite layer is disposed on the surface of the metal barrier layer opposite to the first wafer. The metal-graphene composite layer includes two metal layers and a graphene sheet sandwiched between the two metal layers.

16. The packaging structure according to claim 15, characterized in that, The edges of the metal barrier layer, the two metal layers, and the graphene sheet are aligned with the sidewalls of the molding layer.

17. The packaging structure according to claim 15, characterized in that, The material of the metal barrier layer is Ti, and the material of the two metal layers is Cu.

18. A method for forming an encapsulation structure, characterized in that, include: A first inorganic dielectric layer is formed on the first input / output layer of the first wafer, and a first pad electrically connected to the first input / output layer is formed in the first inorganic dielectric layer. A third inorganic dielectric layer is formed on the second input / output layer of the second wafer, and a second pad electrically connected to the second input / output layer is formed in the third inorganic dielectric layer; A second inorganic dielectric layer is formed on the back side of the second wafer opposite to the back side of the second input / output layer; The second wafer is disposed on the first wafer, the first inorganic dielectric layer and the second inorganic dielectric layer are mixed and bonded, the second wafer is offset relative to the first wafer in the horizontal direction, such that the front side of the first wafer includes a first overlapping region that overlaps with the second wafer in the vertical direction and a first non-overlapping region that is offset from the second wafer in the vertical direction, and the first inorganic dielectric layer is exposed in the first non-overlapping region. A first connector is formed to connect the first pad, and a second connector is formed to connect the second pad; A molding layer is formed that covers the first wafer, the first connector, the first inorganic dielectric layer, the second wafer, the second connector, and the second inorganic dielectric layer, and exposes the first connector and the second connector to the molding layer. A circuit layer is formed on the molding layer, and the circuit layer connects the first connector and the second connector.

19. The method for forming an encapsulation structure according to claim 18, characterized in that, The first inorganic dielectric layer, the second inorganic dielectric layer, and the third inorganic dielectric layer are formed by chemical vapor deposition.

20. The method for forming an encapsulation structure according to claim 18, characterized in that, Also includes: A metal barrier layer is formed on the back side of the first wafer that is exposed relative to the molding layer, and on the molding layer, the back side of the first wafer being opposite to the first input / output layer and flush with the molding layer; A metal-graphene composite layer is formed on the surface of the metal barrier layer opposite to the first wafer. The metal-graphene composite layer includes two metal layers and a graphene sheet sandwiched between the two metal layers.

Images