Method for bonding semiconductor substrates

Abstract

A method of bonding a first semiconductor substrate to a second semiconductor substrate is disclosed, the method comprising: providing a stress relief coating to at least one of the first semiconductor substrate and the second semiconductor substrate; and bonding the first semiconductor substrate to the second semiconductor substrate to form a bonded substrate; wherein the stress relief coating is configured to enhance the bond strength between the first semiconductor substrate and the second semiconductor substrate, and to reduce the amount of stress induced by the bond in the bonded substrate.

Description

Cross-references to related applications

[0001] This application claims priority to EP application 24166666.8, filed on March 27, 2024, and EP application 24176193.1, filed on May 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to methods and apparatus for applying patterns to a substrate, and particularly to methods for bonding semiconductor substrates during photolithography manufacturing. Background Technology

[0003] A photolithography apparatus is a machine that applies a desired pattern onto a substrate, typically onto a target portion of the substrate. Photolithography apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). In this case, a patterning apparatus (or alternatively, a mask or stencil) can be used to generate a circuit pattern that will be formed on a single layer of the IC. This pattern can be transferred to a target portion (e.g., a portion including a die, a die, or multiple dies) on a substrate (e.g., a silicon wafer). Pattern transfer is typically achieved by imaging onto a layer of radiation-sensitive material (resist) disposed on the substrate. Typically, a single substrate will contain a network of adjacent target portions patterned sequentially. Known photolithography apparatuses include so-called steppers, where each target portion is irradiated by exposing the entire pattern onto the target portion at once; and so-called scanners, where each target portion is irradiated by scanning the pattern in a given direction (“scanning” direction) via a radiation beam while simultaneously scanning the substrate parallel or antiparallel to that direction. A pattern can also be transferred from a patterning apparatus to a substrate by imprinting the pattern onto the substrate.

[0004] To monitor the photolithography process, parameters of the patterned substrate are measured. These parameters may include, for example, the overlap error between successive layers formed in or on the patterned substrate, and the critical linewidth (CD) of the developed photoresist. This measurement can be performed on the product substrate and / or a dedicated measurement target. Various techniques exist for measuring the microstructures formed during the photolithography process, including the use of scanning electron microscopy and various specialized tools. One rapid and non-invasive form of specialized inspection tool is a scatterometer, in which a radiation beam is directed onto a target on the substrate surface, and the properties of the scattered or reflected beam are measured. Two main types of scatterometers are known. Spectroscopic scatterometers direct a broadband radiation beam onto the substrate and measure the spectrum of the radiation scattered over a specific narrow angular range (the spectrum being the intensity as a function of wavelength). Angle-resolved scatterometers use a monochromatic radiation beam and measure the intensity of the scattered radiation as a function of angle.

[0005] Examples of known scatterers include angle-resolved scatterers of the type described in US2006033921A1 and US2010201963A1. Such scatterers utilize relatively large gratings for the target, such as 40 μm × 40 μm gratings, and the measurement beam generates spots smaller than the grating (i.e., grating underfill). In addition to reconstructing the shape of the measurement feature, such devices can be used to measure diffraction-based overlap, as described in published patent application US2006066855A1. Diffraction-based overlap measurements using dark-field imaging with diffraction orders enable overlap measurements of smaller targets. Examples of dark-field imaging measurements can be found in international patent applications WO2009 / 078708 and WO2009 / 106279, which are incorporated herein by reference in their entirety. Further developments of this technology have been described in the following published patent publications: US20110027704A, US20110043791A, US2011102753A1, US20120044470A, US20120123581A, US20130258310A, US20130271740A, and WO2013178422A1. These targets can be smaller than the illumination spot and can be surrounded by the product structure on the wafer. Multiple gratings can be measured in a single image using composite grating targets. The contents of all these applications are also incorporated herein by reference.

[0006] Process control methods are used in the fabrication of integrated devices to monitor and control the process of applying or measuring patterns on a substrate. Typically, this process control technique is performed to obtain calibrations for controlling the process. Subsequently, (for some devices) it is sometimes necessary to bond the substrates together. Bonding processes include die-to-die, die-to-wafer, and wafer-to-wafer. Wafer-to-wafer bonding (where the entire wafer is permanently bonded together before dicing) has the potential to provide a high-accuracy and high-throughput bonding solution.

[0007] The aim is to improve process control methods in the manufacturing of integrated devices. Summary of the Invention

[0008] In a first aspect of the invention, a method for bonding a first semiconductor substrate to a second semiconductor substrate is provided, the method comprising: providing a stress-relief coating to at least one of the first semiconductor substrate and the second semiconductor substrate; and bonding the first semiconductor substrate to the second semiconductor substrate to form a bonded substrate; wherein the stress-relief coating is configured to enhance the bonding strength between the first semiconductor substrate and the second semiconductor substrate and reduce the amount of stress in the bonded substrate.

[0009] In a second aspect of the invention, a bonded substrate manufactured using the method of the first aspect is provided.

[0010] Further aspects, features, and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. Note that the invention is not limited to the specific embodiments described herein. These embodiments are for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein. Attached Figure Description

[0011] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 It describes photolithography equipment and other equipment used to form production facilities for semiconductor devices; Figure 2 A schematic diagram of a scatterer for measuring a target according to an embodiment of the present invention is included; Figure 3 This is a flowchart describing the method for manufacturing integrated devices by combining wafers with wafers; Figure 4A The main steps of a method for bonding a first semiconductor substrate to a second semiconductor substrate according to an embodiment are schematically depicted. Figure 4B schematically depicted Figure 4A The main steps of the variation of the method shown; Figure 5A The main steps of a method for bonding a first semiconductor substrate to a second semiconductor substrate according to different embodiments are schematically depicted; and Figure 5B schematically depicted Figure 5A The main steps of the variation of the method shown. Detailed Implementation

[0012] Before describing the embodiments of the present invention in detail, it is illustrative to provide an example environment in which the embodiments of the present invention can be implemented.

[0013] Figure 1 A lithography apparatus LA is shown at 200 as part of an industrial production facility implementing a high-capacity lithography manufacturing process. In this example, the manufacturing process is suitable for manufacturing semiconductor products (integrated circuits) on substrates such as semiconductor wafers. Those skilled in the art will understand that a wide variety of products can be manufactured by processing different types of substrates in variations of this process. The production of semiconductor products is used purely as an example, which has enormous commercial significance today.

[0014] Within the lithography apparatus (or simply "lithography tool" 200), a measurement station MEA is shown at 202, and an exposure station EXP is shown at 204. A control unit LACU is shown at 206. In this example, each substrate accesses both the measurement and exposure stations to be patterned. For example, in an optical lithography apparatus, a projection system is used to transfer a product pattern from a patterning apparatus MA onto a substrate using regulated radiation and a projection system. This is accomplished by forming an image of the pattern within a layer of radiation-sensitive resist material.

[0015] The term "projection system" as used herein should be broadly interpreted to include any type of projection system, including refractive, reflective, antirefractive, magnetic, electromagnetic, and electrostatic optical systems, or any combination thereof, depending on the application of the exposure radiation in use, or other factors such as the use of immersion liquids or vacuum. The patterning apparatus MA can be a mask or stencil that imparts a pattern to a radiation beam transmitted or reflected by the patterning apparatus. Known operating modes include step mode and scan mode. It is well known that the projection system can cooperate in various ways with supports and positioning systems for the substrate and the patterning apparatus to apply a desired pattern to many target portions across the substrate. Programmable patterning apparatuses can be used instead of masks with fixed patterns. Radiation can, for example, include electromagnetic radiation in the deep ultraviolet (DUV) or extreme ultraviolet (EUV) bands. This disclosure also applies to other types of lithography processes, such as imprint lithography and direct write lithography, for example, by electron beams.

[0016] Photolithography equipment has a control unit (LACU) that controls all movements and measurements of various actuators and sensors to receive the substrate (W) and mask (MA) and perform patterning operations. The LACU also includes signal and data processing capabilities to perform desired calculations related to the operation of the equipment. In practice, the LACU is implemented as a system of multiple sub-units, each handling real-time data acquisition, processing, and control of subsystems or components within the equipment.

[0017] Before the pattern is applied to the substrate at the exposure station EXP, the substrate is processed in the measurement station MEA, allowing for various preparation steps to be performed. Preparation steps may include mapping the surface height of the substrate using a level sensor; and measuring the position of alignment marks on the substrate using an alignment sensor. The alignment marks are nominally arranged in a regular grid pattern. However, due to inaccuracies in mark generation and substrate deformation that occurs throughout the substrate processing, the marks deviate from the ideal grid. Therefore, in addition to measuring the position and orientation of the substrate, the alignment sensor must actually measure the position of many marks across a region of the substrate in detail if the equipment is to print product features in the correct positions with very high precision. The equipment can be of a so-called dual-stage type, with two substrate stages, each with a positioning system controlled by a control unit LACU. While one substrate on one stage is exposed at the exposure station EXP, another substrate can be loaded onto the other substrate stage at the measurement station MEA, enabling the performance of various preparation steps. Therefore, the measurement of alignment marks is very time-consuming, and providing two substrate stages allows for a significant increase in equipment throughput. If the position sensor IF cannot measure the position of the substrate stage when it is in the measurement station and the exposure station, a second position sensor can be provided so that the position of the substrate stage can be tracked at both stations. A lithography apparatus LA can, for example, be a so-called dual-stage type, having two substrate stages and two stations (exposure station and measurement station), between which the substrate stages can be exchanged.

[0018] Within the production facility, equipment 200 forms part of a "lithography unit" or "lithography cluster," which also includes coating equipment 208 for applying photoresist and other coatings to a substrate W for patterning via equipment 200. At the output side of equipment 200, baking equipment 210 and developing equipment 212 are provided for developing the exposed pattern into a physical resist pattern. Between all these devices, a substrate handling system is responsible for supporting the substrate and transferring it from one device to the next. These devices, generally referred to collectively as tracks, are under the control of a track control unit, which in turn is controlled by a supervisory control system SCS, which also controls the lithography equipment via a lithography equipment control unit LACU. Therefore, different devices can be operated to maximize throughput and processing efficiency. The supervisory control system SCS receives configuration information R, which provides very detailed specifications for the steps to be performed to produce each patterned substrate.

[0019] Once the pattern has been applied and developed in the photolithography unit, the patterned substrate 220 is transferred to other processing equipment, such as those illustrated at 222, 224, and 226. In typical manufacturing facilities, a wide range of processing steps are performed by various equipment. For example, equipment 222 in this embodiment is an etching station, and equipment 224 performs a post-etch annealing step. Other physical and / or chemical processing steps are applied in other equipment such as 226. Fabricating actual devices may require various types of operations, such as material deposition, modification of surface material properties (oxidation, doping, ion implantation, etc.), chemical mechanical polishing (CMP), etc. In practice, equipment 226 can represent a series of different processing steps performed in one or more equipment. As another example, equipment and processing steps for implementing self-aligned multiple patterning can be provided to generate multiple smaller features based on a precursor pattern laid by the photolithography equipment.

[0020] As is well known, the fabrication of semiconductor devices involves repeated processing to build device structures with appropriate materials and patterns layer by layer on a substrate. Accordingly, the substrates 230 arriving at the photolithographic cluster can be newly prepared substrates, or they can be substrates that have been fully processed previously in that cluster or in another device. Similarly, depending on the required processing, the substrates 232 leaving the device 226 can be returned for subsequent patterning operations in the same photolithographic cluster, they may be designated for patterning operations in different clusters, or they may be finished products to be sent for dicing and packaging.

[0021] Each layer of the product structure requires a different set of process steps, and the equipment 226 used at each layer can be completely different in type. Furthermore, even when the processing steps performed by equipment 226 are nominally the same, in a large facility, there may be several supposedly identical machines operating in parallel to perform step 226 on different substrates. Minor differences in setup or malfunction between these machines may mean that they affect different substrates in different ways. Even for relatively common steps in each layer, such as etching (equipment 222), it can be achieved by several nominally identical but parallel-operating etching devices to maximize throughput. Moreover, in practice, different layers require different etching processes (e.g., chemical etching, plasma etching) depending on the details of the material to be etched and specific requirements such as, for example, anisotropic etching.

[0022] As mentioned earlier, preceding and / or subsequent processes can be performed in other lithography equipment, and even in different types of lithography equipment. For example, device fabrication processes can be performed on some layers with high requirements for parameters (such as resolution and overlap) in more advanced lithography tools compared to other layers with lower requirements. Therefore, some layers can be exposed in immersion lithography tools, while others are exposed in "dry" tools. Some layers can be exposed in tools operating at DUV wavelengths, while other layers are exposed using EUV wavelength radiation.

[0023] To ensure correct and consistent exposure of substrates by photolithography equipment, it is desirable to inspect the exposed substrates to measure properties such as overlap error between subsequent layers, line thickness, and critical dimension (CD). Accordingly, the manufacturing facility where the photolithography unit (LC) is located also includes a metrology system that receives some or all of the substrates (W) already processed in the photolithography unit. The metrology results are provided directly or indirectly to the supervisory control system (SCS). If an error is detected, the exposure of subsequent substrates can be adjusted, especially if the metrology can be performed quickly and sufficiently so that other substrates in the same batch will still be exposed. Furthermore, exposed substrates can be stripped and reprocessed to increase yield, or discarded, thus avoiding further processing of substrates known to be defective. In cases where only some target portions of the substrate are defective, further exposure can be performed only on those good target portions.

[0024] Figure 1 The diagram also shows a metrology device 240, which is provided for measuring parameters of the product at desired stages of the manufacturing process. A common example of a metrology station in modern lithography production facilities is a scatterometer (e.g., a dark-field scatterometer, an angle-resolved scatterometer, or a spectral scatterometer), which can be used to measure the properties of the developed substrate at 220 prior to etching in device 222. Using metrology device 240, it is possible to determine important performance parameters, such as overlap or critical dimensions (CD), that do not meet specified accuracy requirements in the developed resist. Prior to the etching step, there is an opportunity to strip the developed resist and reprocess the substrate 220 through the lithography cluster. By making small adjustments over time through the supervisory control system SCS and / or control unit LACU 206, the metrology results 242 from device 240 can be used to maintain the accurate performance of the patterning operations in the lithography cluster, thereby minimizing the risk of non-conforming products requiring reprocessing.

[0025] Additionally, measurement device 240 and / or other measurement devices (not shown) can be applied to measure the properties of the processed substrates 232, 234 and the incoming substrate 230. The measurement devices can be used on the processed substrates to determine important parameters such as overlap or CD.

[0026] Figure 2 (a) illustrates a measurement device suitable for use in embodiments of the invention. Figure 2 (b) illustrates the target T and the diffracted rays of the measurement radiation used to illuminate the target in more detail. The measurement device illustrated is of the type known as a dark-field measurement device. The measurement device can be a stand-alone device or incorporated into a lithography apparatus LA (e.g., at a measurement station) or a lithography unit LC. The optical axis having several branches throughout the device is indicated by the dashed line O. In this device, light emitted by the light source 11 (e.g., a xenon lamp) is guided onto the substrate W by an optical system including lenses 12, 14 and objective lens 16 via a beam splitter 15. These lenses are arranged in a double sequence of 4F. Different lens arrangements can be used, provided that it still provides an image of the substrate to the detector and simultaneously allows access to the intermediate pupil plane for spatial frequency filtering. Thus, by defining the spatial intensity distribution in the plane presenting the spatial spectrum of the substrate plane (here referred to as the (conjugate) pupil plane), the range of angles at which radiation is incident on the substrate can be selected. Specifically, this can be accomplished by inserting a suitably shaped aperture plate 13 between lenses 12 and 14, in the plane of the rear-projected image that serves as the objective pupil plane. In the illustrated example, the aperture plate 13 has different forms, labeled 13N and 13S, allowing for the selection of different illumination modes. The illumination system in this example forms an off-axis illumination mode. In the first illumination mode, aperture plate 13N provides off-axis illumination relative to a specified direction, designated "North" for descriptive purposes only. In the second illumination mode, aperture plate 13S is used to provide similar illumination, but from the opposite direction, labeled "South". Other illumination modes are also possible by using different apertures. The remainder of the pupil plane is ideally dark, as any unwanted light outside the desired illumination mode will interfere with the desired measurement signal.

[0027] like Figure 2As shown in (b), the target T is positioned such that the substrate W is perpendicular to the optical axis O of the objective lens 16. The substrate W may be supported by a support (not shown). The ray of measurement radiation I striking the target T from an angle offset from the optical axis O produces a zero-order ray (solid line 0) and two first-order rays (dot-chain +1 and double dot-chain -1). It should be remembered that in the case of an overfilled small target, these rays are merely one of many parallel rays covering the area of ​​the substrate that includes the measurement target T and other features. Due to the finite width of the aperture in plate 13 (necessary for allowing a useful amount of light to enter), the incident ray I will actually occupy a certain angular range, and the diffracted rays 0 and +1 / -1 will spread out slightly. According to the point spread function of the small target, each order +1 and -1 will further spread over a certain angular range, rather than a single ideal ray as shown. Note that the grating pitch and illumination angle of the target can be designed or adjusted so that the first-order ray entering the objective lens is closely aligned with the central optical axis. Figure 2 The rays illustrated in (a) and 2(b) are shown slightly off the optical axis, simply to make them easier to distinguish in the illustrations.

[0028] At least the 0th and +1st orders of diffraction from the target T on the substrate W are collected by objective lens 16 and guided back by beam splitter 15. (Back) Figure 2 (a) The first and second illumination modes are illustrated by specifying the relative apertures on the diameters marked North (N) and South (S). When the incident ray I for measuring radiation comes from the north side of the optical axis (i.e., when the first illumination mode is applied using aperture plate 13N), the +1 diffraction ray marked +1 (N) enters the objective lens 16. Conversely, when the second illumination mode is applied using aperture plate 13S, the -1 diffraction ray (marked -1 (S)) is the diffraction ray entering the lens 16.

[0029] The second beam splitter 17 divides the diffracted beam into two measurement branches. In the first measurement branch, the optical system 18 uses the zeroth-order and first-order diffracted beams to form the diffraction spectrum (pupil plane image) of the target on the first sensor 19 (e.g., a CCD or CMOS sensor). Each diffraction order hits a different point on the sensor, allowing image processing to compare and contrast multiple orders. The pupil plane image captured by the sensor 19 can be used for many measurement purposes, such as the reconstruction used in the methods described herein. The pupil plane image can also be used for focusing measurement devices and / or intensity measurements of the normalized first-order beam.

[0030] In the second measurement branch, optical systems 20 and 22 form an image of the target T on sensor 23 (e.g., a CCD or CMOS sensor). In this second measurement branch, an aperture stop 21 is positioned in a plane conjugate to the pupil plane. The aperture stop 21 blocks the zero-order diffraction beam, ensuring that the target image formed on sensor 23 is formed only by a first-order beam of either -1 or +1 order. The image captured by sensors 19 and 23 is output to a processor PU that processes the image; the functionality of the processor PU will depend on the specific type of measurement performed. Note that the term "image" as used herein is broad. If only one of the -1 or +1 orders is present, an image with such grating lines will not be formed.

[0031] Figure 2 The specific forms of the aperture plate 13 and field stop 21 shown are merely examples. In another embodiment of the invention, on-axis illumination of the target is used, and an aperture stop with an off-axis aperture is used to essentially deliver only a single first-order diffracted beam to the sensor. In other embodiments, second-, third-, and higher-order beams can be used in measurements instead of a first-order beam or in addition to a first-order beam. Figure 2 (Not shown in the image).

[0032] The target T may include multiple gratings with different offsets to facilitate the measurement of overlap between multiple layers, where different portions of a composite grating are formed in the multiple layers. The gratings may also differ in their orientation to diffract incident radiation in the X and Y directions. In one example, the target may include two X-direction gratings with offsets of +d and -d, and a Y-direction grating with offsets of +d and -d. Separate images of these gratings can be identified in the image captured by sensor 23. Once the separate images of these gratings have been identified, the intensity of these individual images can be measured, for example, by averaging or summing the intensity values ​​of selected pixels within the identified regions. The intensity and / or other properties of the images can be compared with each other. These results can be combined to measure different parameters of the photolithography process.

[0033] Various techniques can be used to improve the accuracy of pattern reproduction on a substrate. Accurate pattern reproduction on a substrate is not the only concern in IC manufacturing. Another concern is yield, which typically measures how many functional devices a device manufacturer or device manufacturing process can produce per substrate. Various methods can be employed to increase yield. One such method attempts to make device production (e.g., imaging a portion of a design layout onto a substrate using a lithography apparatus such as a scanner) more tolerant of perturbations in at least one of the processing parameters during substrate processing (e.g., during the process of imaging a portion of the design layout onto a substrate using a lithography apparatus). The concept of an Overlapping Process Window (OPW) is a useful tool for this approach. Device (e.g., IC) production may include other steps such as substrate measurement before, after, or during imaging; substrate loading or unloading; loading or unloading of the patterning apparatus; positioning the die under the projection optics before exposure; stepping from one die to another; and so on. Furthermore, various patterns on the patterning apparatus can have different process windows (i.e., a space of processing parameters under which patterns within specifications will be produced). Examples of pattern specifications related to potential system defects include inspections for necking, line pullback, line thinning, CD, edge placement, overlap, resist top loss, resist undercut, and / or bridging. Process windows for all or some patterns (typically patterns within a specific region) on a patterning apparatus can be obtained by merging (e.g., overlapping) the process windows of each individual pattern. Therefore, these process windows are referred to as overlapping process windows. The boundary of the OPW may contain the boundaries of the process windows of some individual patterns. In other words, these individual patterns constrain the OPW. These individual patterns may be referred to as “hot spots” or “process window-limited patterns (PWLP),” and these terms are used interchangeably herein. Focusing on hot spots is possible and generally economical when controlling the lithography process. When there are no defects in the hot spots, it is likely that all patterns are also defect-free. Imaging becomes more tolerant of perturbations when the processing parameter values ​​are closer to the OPW if they are outside the OPW, or when they are further away from the OPW boundary if they are within the OPW.

[0034] The values ​​of the processing parameters can be selected such that they are far from the boundaries of the OPW or the fitted OPW, in order to reduce the chance of the processing parameters moving outside the OPW and thus causing defects and reducing yield. One method of selecting the values ​​of the processing parameters includes: (1) optimizing the lithography equipment (e.g., optimizing the source and projection optics) and optimizing the design layout before actual imaging, (2) determining the OPW or the fitted OPW (e.g., by simulation), and (3) determining a point in the space of the processing parameters that is as far away as possible from the boundaries of the OPW or the fitted OPW (this point may be referred to as the "center" of the OPW or the "center" of the fitted OPW).

[0035] During or prior to actual imaging, processing parameters may be perturbed by a point that deviates as far as possible from the boundary of the OPW (Optically Surface-Mounted Work) or the boundary of the fitted OPW. For example, focus may change due to the topography of the substrate to be exposed, stage drift, deformation of the projection optics, etc.; dose may change due to drift in source intensity, dwell time, etc. Perturbations may be large enough to cause processing parameters to fall outside the OPW and thus potentially lead to defects. Various techniques can be used to identify and correct perturbed processing parameters. For example, if focus is perturbed, for instance, because a slightly elevated area of ​​the substrate relative to the rest of the substrate is exposed, the stage can be moved or tilted to compensate for the perturbation.

[0036] The control of the photolithography process is typically based on feedback or feedforward measurements, and then modeled using, for example, inter-field (cross-substrate fingerprint) or intra-field (cross-field fingerprint) models. Within the die, separate functional regions can exist, such as memory regions, logic regions, contact regions, etc. Each different functional region, or different functional region type, can have a different process window, and each process window has a different process window center. For example, different functional region types can have different heights, and therefore different optimal focus settings. Moreover, different functional region types may have different structural complexities, and therefore different focus tolerances (focus process windows) around each optimal focus. However, due to limitations in control grid resolution, each of these different functional regions will typically be formed using the same focus (or dose or position, etc.) settings.

[0037] Figure 3 A device fabrication arrangement for manufacturing a bonded substrate (and thus an IC based on the bonded substrate) including a first fabrication lithography unit LC1 and a second fabrication lithography unit LC2 is shown. Within each lithography unit are pairs of lithography processing systems 300a, 300b and first measurement systems 310a, 310b. The lithography processing systems 300a, 300b may include a fully patterned system. For example, such a system may include: such as regarding Figure 1 The described optical lithography apparatus or scanner, tracking tool, deposition tool, etching tool, any other equipment used in the patterning process, or any combination thereof. The system may also each include software applications 320a, 320b communicating with their respective lithography processing systems 300a, 300b and metrology systems 310a, 310b, such that the results, designs, data, etc., of the lithography processing systems 300a, 300b and / or metrology devices 310a, 310b can be stored and analyzed by the software applications 320a, 320b simultaneously or at different times.

[0038] Once a substrate pair or wafer pair is completed from each of the lithography units LC1 and LC2, they can be bonded within the bonding tool 330 to obtain a bonded wafer. In this context, bonding is wafer-to-wafer bonding, where entire wafers are aligned and bonded together such that the individual dies on each wafer are aligned. The concept of wafer-to-wafer bonding is known and used in many IC manufacturing processes. The bonding tool 330 may include bonding alignment means for aligning wafers together for bonding. For example, the bonding tool 330 may use frame-like markings provided to the wafers (e.g., one frame on each wafer) to perform pre-alignment, where alignment quality / position control is performed using visual inspection of the markings. Another method uses two imaging sensors (e.g., face-to-face), first calibrating the two imaging sensors together to find their relative positions; then using each sensor individually to align the respective wafers to be bonded.

[0039] The lithography units LC1 and LC2 can be: identical lithography units; different lithography units that include one or more shared tools and components; or completely different lithography units with entirely different sets of equipment and tools, even possibly at different sites or factories. For example, one or more tools or devices of the lithography processing systems 300a and 300b can include different tools or the same tools within each respective system. Similarly, the measurement devices 310 and 310b can be the same devices or different devices. Software applications 320a and 320b can be included in one or both of the respective lithography processing systems 300a and 300b, and / or included in one or both of the first measurement systems 310a and 310b, or included elsewhere.

[0040] Once bonded, the bonded wafers can undergo further photolithographic patterning and processing. Therefore, alignment will be performed on the bonded wafers; for example, to align the substrate and determine feedforward correction based on measured mesh deformation. Furthermore, post-exposure measurements (such as overlap measurements) can be performed on the bonded wafers after exposure; for example, to determine feedback correction for subsequent wafers.

[0041] Currently, various bonding techniques have been implemented to bond semiconductor substrates (commonly referred to as wafers). Among existing bonding techniques, fusion bonding and hybrid bonding are widely used for bonding semiconductor substrates. Fusion bonding enables permanent connections via dielectric layers on each bonded semiconductor substrate and provides good bond strength with high bonding yield. Typically, the fusion bonding process includes three main steps: 1) wafer surface preparation, which may include surface planarization, cleaning, and activation; 2) pre-bonding at room temperature, which may include aligning the two bonding surfaces; and 3) annealing (or heat treatment) at elevated temperatures (e.g., 200°C to 500°C). During fusion bonding, spontaneous adhesion of the two bonding surfaces occurs at room temperature via hydrogen bridging of chemisorbed water molecules, which react during the annealing step to form covalent siloxane bonds. Further information on fusion bonding technology can be found in the book “Handbook of Wafer Bonding”, edited by Peter Ramm, James J.-Q. Lu, and Maaike MV Taklo, and published by Wiley-VCH on January 11, 2012, with ISBN 9783527326464, which is incorporated herein by reference.

[0042] Hybrid bonding combines fusion bonding and metal diffusion bonding into a single bonding process, enabling the simultaneous formation of dielectric-to-dielectric and metal-to-metal bonds between two bonding surfaces. This is achieved by embedding metal (e.g., copper, gold) pads in the dielectric layer of each bonding semiconductor substrate. Similar to fusion bonding, hybrid bonding also includes three main steps: 1) wafer surface preparation; 2) pre-bonding at room temperature; and 3) annealing (or heat treatment) at a high temperature. The surface preparation step of hybrid bonding also includes forming metal pads on the surface of each bonding semiconductor substrate, typically by etching the dielectric layer on the semiconductor substrate (e.g., to create vias to the underlying metal) and electroplating (or electrochemical deposition (ECD)) at at least a portion of the etched dielectric layer to form the metal pads therein. In hybrid bonding, the dielectric layers of the two bonding substrates are first bonded at low temperature via hydrogen bridging bonds of chemisorbed water molecules (see fusion bonding above). The subsequent annealing step transforms these hydrogen bridges into covalent siloxane bonds, while simultaneously forming metal diffusion bonds. Further information on hybrid bonding techniques can be found in the book "Handbook of Wafer Bonding," edited by Peter Ramm, James J.-Q. Lu, and Maaike MV Taklo, and published by Wiley-VCH on January 11, 2012, under ISBN 9783527326464, which is incorporated herein by reference.

[0043] In many fusion bonding or hybrid bonding applications, interlayers (e.g., silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON)) are used to enhance bond strength. However, even with interlayers, existing bonding techniques (e.g., fusion bonding) can still introduce high-order wafer distortion and significant variations in wafer-to-wafer distortion, which can adversely affect the overlap performance of the bonded wafers when further photolithographic patterning (e.g., patterning interconnects) is performed on one or both of the back sides of the bonded wafers. This is primarily due to the fact that these interlayers are rigid layers and therefore cannot absorb the stress introduced into the bonded wafers during the bonding process. The term "back side" refers to the unbonded side of one of the two bonded wafers. Therefore, a bonded wafer comprises two back sides, each belonging to one of the two bonded wafers. The order and magnitude of this bonding-induced wafer distortion are significantly influenced by the coating deposition techniques already used to deposit the interlayers onto the wafers. This is because different coating deposition techniques may require, for example, different operating temperatures, different pressures, different coating materials, and / or different coating times, and may produce different coating uniformities, all of which can lead to wafer distortion. Therefore, the purpose of this disclosure is to provide solutions to the problems associated with technologies combined with the prior art.

[0044] One aspect of this disclosure provides a method for bonding a first semiconductor substrate to a second semiconductor substrate, the method comprising: providing a stress-relief coating to at least one of the first and second semiconductor substrates; and bonding the first semiconductor substrate to the second semiconductor substrate to form a bonded substrate; wherein the stress-relief coating is configured to enhance the bonding strength between the first and second semiconductor substrates and reduce the amount of bonding-induced stress in the bonded substrate. Advantageously, the proposed method can minimize or mitigate the adverse effects of wafer distortion, such as that caused by unoptimized bonding parameters and / or process variability, on the overlap performance of the bonded wafer during subsequent wafer back-side patterning and processing. This is achieved by using at least one stress-relief coating to eliminate or minimize bonding-induced stress within the bonded substrate.

[0045] The proposed method is applicable to various semiconductor substrate bonding techniques. Preferably, the proposed method can be used to bond two semiconductor substrates via fusion bonding or hybrid bonding (as described above).

[0046] The amount of stress caused by bonding in the bonded substrate may include the amount of stress caused by bonding in one or more of the following: a stress-relief coating deposited on at least one of a first semiconductor substrate and a second semiconductor substrate, the first semiconductor substrate, and the second semiconductor substrate.

[0047] In an embodiment, the step of providing a stress-relieving coating to at least one of the first semiconductor substrate and the second semiconductor substrate may include: depositing a stress-relieving coating onto at least one of the first semiconductor substrate and the second semiconductor substrate. One or both stress-relieving coatings (if deposited onto two semiconductor substrates) may each have the following material properties at room temperature: Young's modulus E < 5×10 -2 gigapascals (GPa); Complex modulus G < 5×10 -3 gigapascals (GPa); Viscosity 10 3 < μ < 10 5 Pascal-second (Pa•s). Each stress-relief coating can serve as a “soft” interlayer located between a first semiconductor substrate and a second semiconductor substrate. As described above, in existing fusion bonding or hybrid bonding methods, an interlayer (e.g., SiO2 or SiCN) is deposited onto one or both of the two bonded semiconductor substrates to enhance the bond strength between the two substrates. However, typically, existing interlayers are deposited onto semiconductor substrates via chemical vapor deposition (CVD) or physical vapor deposition (PVD). Therefore, these interlayers are rigid layers and cannot be used to absorb or relieve stress caused by bonding in the bonded substrates. Further information on chemical vapor deposition and physical vapor deposition can be found in the book “Handbook of Thin Film Deposition Processes and Techniques”, edited by Krishna Seshan and published by Noyes Publications in 2002 with ISBN: 0-8155-1442-5, which is incorporated herein by reference.

[0048] In contrast, the “soft” interlayer used in the proposed bonding method not only enhances the bonding strength between the two semiconductor substrates, but also allows for the elimination or minimization of bonding-induced stress in the bonded substrates.

[0049] Figure 4A The proposed combination method 400 according to an embodiment is schematically depicted. In this embodiment, method 400 may include the following three main steps 410 to 430.

[0050] In step 410, a first wafer WA1 and a second wafer WA2 may be provided for bonding.

[0051] In an embodiment, method 400 may include: preparing a first surface WS1 of a first semiconductor substrate WA1 and a second surface WS2 of a second semiconductor substrate WA2. How the first surface WS1 and the second surface WS2 are prepared may depend on the coating deposition technique used to coat one or both of the semiconductor substrates WA1 and WA2, and / or on the bonding technique used to bond the semiconductor substrates WA1 and WA2 (e.g., fusion bonding or hybrid bonding) (see below). This is because different coating deposition techniques or different bonding techniques may impose different requirements on the surface conditions of the semiconductor substrates WA1 and WA2.

[0052] In step 420, a stress-relieving coating may be provided to at least one of the first bonding surface WS1 and the second bonding surface WS2. One or both stress-relieving coatings may each be deposited onto the respective semiconductor substrate via a spin-coating deposition process and may each have the following material properties at room temperature: Young's modulus E < 5×10 -2 GPa Complex modulus G < 5×10 -3 GPa Viscosity 10 3 < μ < 10 5 Pa•s. Further information on spin coating deposition can be found in the book “Handbook of Thin Film Deposition Processes and Techniques”, edited by Krishna Seshan and published by Noyes Publications in 2002 with ISBN: 0-8155-1442-5, which is incorporated herein by reference.

[0053] exist Figure 4A In the illustrated embodiment, a first stress-relief coating SC1 can be deposited on a first surface WS1 of a first semiconductor substrate WA1, and a second stress-relief coating SC2 can be deposited on a second surface WS2 of a second semiconductor substrate WA2.

[0054] The stress-relieving coating SC1 or SC2 may include a dielectric layer. For example, the dielectric layer may be a layer of SiO2 or SiCN. This stress-relieving coating may be suitable for fusion bonding.

[0055] In an alternative embodiment, the stress-relieving coating SC1 or SC2 may include a dielectric layer and a plurality of conductive (e.g., metal, such as copper, gold) pads or interconnects embedded within the dielectric layer. Such a stress-relieving coating may be suitable for hybrid bonding. In this alternative embodiment, step 420 may further include etching the deposited dielectric layer and electroplating at least a portion of the etched dielectric layer to form a plurality of conductive (e.g., metal, such as copper, gold) pads on at least one of the first bonding surface WS1 and the second bonding surface WS2.

[0056] While a thicker stress-relief coating SC1 or SC2 can reduce or absorb a greater amount of stress in the bonded substrate BS1, it is preferable to maintain a balance between the thickness and stiffness of the stress-relief coating SC1 or SC2. This is because if the stress-relief coating SC1 or SC2 becomes too thick, the resulting bonded substrate BS1 may not provide sufficient stiffness for subsequent photolithographic patterning and / or processing. Therefore, the overlap performance of the bonded substrate BS1 may be adversely affected. Preferably, the stress-relief coating SC1 or SC2 may have a thickness, for example, between 1 nm and 1000 nm, between 1 nm and 100 nm, or between 10 nm and 50 nm.

[0057] In step 430, the first semiconductor substrate WA1 and the second semiconductor substrate WA2 can be bonded to form a bonded substrate BS1. The two semiconductor substrates WA1 and WA2 can be bonded by fusion bonding or hybrid bonding.

[0058] Continue to refer to Figure 4A The first semiconductor substrate WA1 and the second semiconductor substrate WA2 can be bonded by connecting or joining the first outer surface (not shown) of the first stress-relieving coating SC1 and the second outer surface (not shown) of the second stress-relieving coating SC2 to obtain a bonded substrate BS1. The first outer surface of the first stress-relieving coating SC1 and the second outer surface of the second stress-relieving coating SC2 can be bonded together by fusion bonding or hybrid bonding. After being bonded together, the first stress-relieving coating SC1 and the second stress-relieving coating SC2 can form a bonding interface layer BL1 between the first semiconductor substrate WA1 and the second semiconductor substrate WA2.

[0059] In an alternative embodiment, a stress-relief coating may be deposited onto a first surface WS1 of a first semiconductor substrate WA1, and no stress-relief coating may be deposited onto a second surface WS2 of a second semiconductor substrate WA2. In this case, the first semiconductor substrate WA1 and the second semiconductor substrate WA2 can be bonded together by connecting the outer surface of the stress-relief coating deposited on the first surface WS1 of the first semiconductor substrate WA1 to the second surface WS2 of the second semiconductor substrate WA2 to obtain a bonded substrate BS1. A single stress-relief coating may form a bonding interface layer between the first semiconductor substrate WA1 and the second semiconductor substrate WA2.

[0060] Optionally, after bonding step 430, method 400 may further include: hardening the bonding layer BL1 by subjecting the bonded substrate BS1 to a heat treatment process. This optional hardening step may improve the stiffness of the bonded substrate BS1, which may be necessary for subsequent photolithographic patterning and / or processing on the back side of the bonded substrate BS1.

[0061] Figure 4B schematically depicted Figure 4A The main steps of a variation 400' of method 400 are shown. In addition to steps 410 to 430 of method 400, method 400' may also include steps 440 and 450, which may be performed before and after step 430, respectively.

[0062] In step 440, after the “soft” stress-relieving coating has been deposited onto at least one of the first semiconductor substrate WA1 and the second semiconductor substrate WA2, the “soft” coating can be hardened.

[0063] exist Figure 4B In the illustrated embodiment, after being deposited onto the first surface WS1 of the first semiconductor substrate WA1 and the second surface WS2 of the second semiconductor substrate WA2, the first stress relief coating SC1 and the second stress relief coating SC2 can be subjected to a heat treatment process (e.g., baking the stress relief coating at a temperature between 180°C and 300°C) so that both stress relief coatings SC1 and SC2 can be hardened.

[0064] Subsequently, in step 430, by connecting the first outer surface (not shown) of the first hardened stress-relieving coating SC1' to the second outer surface (not shown) of the second stress-relieving coating SC2', the first semiconductor substrate WA1 and the second semiconductor substrate WA2 can be bonded to obtain a bonded substrate BS2. After being bonded together, the first hardened stress-relieving coating SC1' and the second hardened stress-relieving coating SC2' can form a bonding interface layer BL2 between the first semiconductor substrate WA1 and the second semiconductor substrate WA2.

[0065] While hardened coatings SC1' and SC2' may be preferred for some applications, they may not reduce or minimize bonding-induced stress in the bonded substrate BS2 as effectively as the "soft" stress-relieving coatings SC1 and SC2. Therefore, after bonding step 430, in step 450, the bonded substrate BS2 may be subjected to another heat treatment process (e.g., baking the stress-relieving coating at a temperature above 800°C), which can soften the bonding layer BL2 between the first semiconductor substrate WA1 and the second semiconductor substrate WA2, thereby reducing or minimizing bonding-induced stress in the bonded substrate BS2.

[0066] After reducing or minimizing the stress caused by bonding in step 450, method 400' may further include cooling the bonded substrate BS1 to room temperature, thereby hardening the bonding layer BL2. Hardening of the bonding layer BL2 can improve the stiffness of the bonded substrate BS2, which may be necessary for subsequent photolithographic patterning and / or processing on the back side of the bonded substrate BS2.

[0067] While the foregoing embodiments rely on using at least one “soft” stress-relieving coating to reduce or minimize bonding-induced stress in the bonded substrate, the same or similar technical effects can be achieved by using at least one patterned coating. For example, in an embodiment, a coating may first be deposited onto at least one of a first semiconductor substrate and a second semiconductor substrate. Subsequently, at least one coating may be patterned to reduce or minimize bonding-induced stress in the bonded substrate. For example, prior to patterning, the coating may comprise a “hard” coating, for instance, having material properties at room temperature such as: Young's modulus E > 5×10 -2 GPa Complex modulus G > 5 × 10 -3 GPa Viscosity μ > 10 5 Pa•s. Therefore, each patterned (e.g., "hard") coating can perform the same or similar function as the "soft" stress-relieving coating, namely, reducing or minimizing stress in the bonded substrate (as described above).

[0068] Figure 5A The main steps of the proposed combining method 500 according to different embodiments are schematically depicted. Method 500 may include the following four main steps 510 to 540.

[0069] In step 510, a first wafer WA1 and a second wafer WA2 may be provided for bonding.

[0070] In an embodiment, method 500 may include: preparing a first surface WS1 of a first semiconductor substrate WA1 and a second surface WS2 of a second semiconductor substrate WA2. How the first surface WS1 and the second surface WS2 are prepared may depend on the coating deposition technique used to coat one or both of the first semiconductor substrate WA1 and the second semiconductor substrate WA2, and / or on the bonding technique used to bond the two semiconductor substrates WA1 and WA2 (e.g., fusion bonding or hybrid bonding) (see below).

[0071] In step 520, a "hard" coating HC1, HC2 may be provided to at least one of the first bonding surface WS1 and the second bonding surface WS2. One or both "hard" coatings HC1, HC2 may each have the following material properties at room temperature: Young's modulus E > 5×10 -2 GPa Complex modulus G > 5 × 10 -3 GPa Viscosity μ > 10 5 Pa•s.

[0072] One or two “hard” coatings HC1 and HC2 can be deposited onto the corresponding semiconductor substrates WA1 and WA2 via CVD or PVD processes, respectively.

[0073] exist Figure 5A In the illustrated embodiment, a first “hard” coating HC1 can be deposited on a first surface WS1 of a first semiconductor substrate WA1, and a second “hard” coating HC2 can be deposited on a second surface WS2 of a second semiconductor substrate WA2.

[0074] The “hard” coating HC1 or HC2 may include a dielectric layer. For example, this dielectric layer may be a layer of SiO2 or SiCN. This stress-relieving coating may be suitable for fusion bonding.

[0075] In an alternative embodiment, the "hard" coating HC1 or HC2 may include a dielectric layer and a plurality of conductive (e.g., metal, such as copper, gold) pads or interconnects embedded within the dielectric layer. This "hard" coating may be suitable for hybrid bonding. In this alternative embodiment, step 520 may further include etching the deposited dielectric layer and electroplating at least a portion of the etched dielectric layer to form a plurality of conductive (e.g., metal, such as copper, gold) pads on at least one of the first bonding surface WS1 and the second bonding surface WS2.

[0076] For example, the “hard” coating HC1 or HC2 can have a thickness between 1 nanometer and 1000 nanometers, between 1 nanometer and 100 nanometers, or between 10 nanometers and 50 nanometers.

[0077] In step 530, at least one of the first "hard" coating HC1 and the second "hard" coating HC2 can be patterned into a specific pattern. Figure 5A In the illustrated embodiment, only the second "hard" coating HC2 can be patterned to form a single patterned coating PHC2; while Figure 5B In the illustrated embodiment, both the first "hard" coating HC1 and the second "hard" coating HC2 can be patterned to form a first patterned "hard" coating PHC1 and a second patterned "hard" coating PHC2, respectively. The "hard" coatings can be patterned using techniques such as photolithography or dry etching. The first patterned "hard" coating PHC1 and the second patterned "hard" coating PHC2 can each be used as a stress-relieving coating.

[0078] exist Figure 5A In the illustrated embodiments, the patterned "hard" coating PHC2 may include a plurality of spatially separated protrusions projecting outward from the corresponding semiconductor substrate WA1 or WA2. In embodiments, the protrusions may be in the form of pillars, which may have, for example, a rectangular or circular cross-section. In embodiments, the plurality of spatially separated protrusions (e.g., pillars) may be arranged as a two-dimensional (2D) array of protrusions (e.g., pillars). In different embodiments, each patterned "hard" coating may include a different coating pattern / structure.

[0079] In step 540, by connecting the first outer surface of the first unpatterned "hard" coating to the second outer surface of the second patterned "hard" coating, the first semiconductor substrate WA1 and the second semiconductor substrate WA2 can be bonded to obtain a bonded substrate BS3. After being bonded together, the first unpatterned "hard" coating HC1 and the second patterned coating PHC2 can form a bonding interface layer BL3 between the first semiconductor substrate WA1 and the second semiconductor substrate WA2. Similar to... Figure 4A and Figure 4B The embodiments shown can be achieved by fusion bonding or hybrid bonding of two semiconductor substrates WA1 and WA2.

[0080] Figure 5B schematically depicted Figure 5A The main steps of variant 500' of the method shown are as follows. Method 500' may differ from method 500 in the patterning and bonding steps.

[0081] Specifically, in step 530' of method 500', instead of... Figure 5AThe illustration shows only the second "hard" coating HC2 being patterned, but both the first "hard" coating HC1 and the second "hard" coating HC2 can be patterned into a specific pattern. For example, the pattern could include a plurality of spatially separated protrusions projecting outward from the respective semiconductor substrates WA1 or WA2.

[0082] In step 540', by connecting the first outer surface of the first patterned "hard" coating PHC1 and the second outer surface of the second patterned "hard" coating PHC2, the first semiconductor substrate WA1 and the second semiconductor substrate WA2 can be bonded to form a bonded substrate BS4. After being bonded together, the first patterned "hard" coating PHC1 and the second patterned "hard" coating PHC2 can form a bonding interface layer BL4 between the first semiconductor substrate WA1 and the second semiconductor substrate WA2. Similar to the above embodiment, the two semiconductor substrates WA1 and WA2 can be bonded by fusion bonding or hybrid bonding.

[0083] In an embodiment, prior to the bonding step 540', method 500' may further include aligning the first patterned "hard" coating PHC1 with the second patterned "hard" coating PHC2. This optional step ensures that the protrusions of the first patterned "hard" coating PHC1 are accurately aligned with the protrusions of the second patterned "hard" coating PHC2, which enhances the bonding between the two semiconductor substrates WA1 and WA2.

[0084] Once bonded, methods 400, 400', 500, 500' may further include performing photolithographic patterning and / or processing on one or both back sides of the bonded substrates BS1, BS2, BS3, BS4.

[0085] and Figure 4A and Figure 4B Compared to the embodiments shown, Figure 5A and Figure 5B The illustrated embodiments can be advantageous because Figure 5A and Figure 5B The illustrated embodiment avoids the need to perform a final hardening step to improve the stiffness of the bonded substrate prior to any subsequent photolithographic patterning and / or processing.

[0086] Other embodiments are disclosed in the following list of numbered entries: 1. A method of bonding a first semiconductor substrate to a second semiconductor substrate, the method comprising: providing a stress-relief coating to at least one of the first semiconductor substrate and the second semiconductor substrate; and bonding the first semiconductor substrate to the second semiconductor substrate to form a bonded substrate; wherein the stress-relief coating is configured to enhance the bonding strength between the first semiconductor substrate and the second semiconductor substrate and reduce the amount of bonding-induced stress in the bonded substrate. 2. The method according to item 1, wherein the first semiconductor substrate and the second semiconductor substrate are bonded by melt bonding or hybrid bonding. 3. The method according to clause 1 or 2, wherein the amount of stress caused by bonding in the bonded substrate includes the amount of stress caused by bonding from one or more of the following: a stress-relieving coating deposited on at least one of the first semiconductor substrate and the second semiconductor substrate, the first semiconductor substrate, and the second semiconductor substrate. 4. The method according to any one of the preceding clauses, wherein the providing step comprises: depositing a stress-relief coating onto at least one of the first semiconductor substrate and the second semiconductor substrate, each stress-relief coating having the following material properties at room temperature: Young's modulus E < 5 × 10⁻⁶ -2 GPa; complex modulus G < 5×10 -3 GPa; viscosity 10 3 <μ < 10 5 Pa•s. 5. The method according to item 4, wherein the providing step further comprises: prior to the bonding step, hardening a stress-relief coating deposited on at least one of the first semiconductor substrate and the second semiconductor substrate. 6. The method according to item 5, further comprising: after the bonding step, softening a stress-relieving coating deposited on at least one of the first semiconductor substrate and the second semiconductor substrate to reduce the amount of bonding-induced stress in the bonded substrate. 7. The method according to any one of clauses 4 to 6, wherein the stress-relief coating is deposited on at least one of the first semiconductor substrate and the second semiconductor substrate via a spin-coating deposition process. 8. The method according to any one of clauses 1 to 3, wherein the providing step comprises: depositing a coating onto at least one of the first semiconductor substrate and the second semiconductor substrate; and patterning the coating deposited onto at least one of the first semiconductor substrate and the second semiconductor substrate to provide the stress-relieving coating. 9. The method according to clause 8, wherein the deposited coating at room temperature has the following material properties: Young's modulus E > 5 × 10⁻⁶. -2 GPa; Complex modulus G > 5 × 10 -3 GPa; viscosity μ > 10 5 Pa•s. 10. The method according to clause 8 or 9, wherein each patterned stress-relief coating includes a plurality of spatially separated protrusions projecting outward from the first semiconductor substrate and / or the second semiconductor substrate. 11. The method according to clause 10, wherein each of the plurality of spatially separated protrusions comprises a column having a rectangular cross-section. 12. The method according to clause 10, wherein each of the plurality of spatially separated protrusions comprises a column having a circular or polygonal cross-section. 13. The method according to clauses 10, 11 or 12, wherein the plurality of spatially separated protrusions are arranged in a two-dimensional array. 14. The method according to any one of clauses 8 to 13, wherein the coating is deposited on at least one of the first semiconductor substrate and the second semiconductor substrate via a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. 15. The method according to any one of the preceding clauses, wherein each stress-relieving coating comprises a dielectric layer. 16. The method according to clause 15, wherein the dielectric layer is a layer of silicon dioxide (SiO2). 17. The method according to clause 15, wherein the dielectric layer is a silicon carbonitride (SiCN) layer. 18. The method according to any one of the preceding clauses, wherein each stress-relieving coating comprises a dielectric layer and a plurality of conductive pads embedded within the dielectric layer. 19. The method according to claim 18, wherein the providing step comprises: depositing the dielectric layer onto at least one of the first semiconductor substrate and the second semiconductor substrate; etching the deposited dielectric layer; and electroplating at least a portion of the etched dielectric layer to form a plurality of embedded conductive pads. 20. The method according to clause 18 or 19, wherein the conductive pad comprises metal. 21. The method according to any one of the preceding clauses, wherein each stress-relieving coating has a thickness between 1 nanometer and 1000 nanometers. 22. The method according to any one of the preceding clauses, wherein each stress-relieving coating has a thickness between 1 nanometer and 100 nanometers. 23. The method according to any one of the preceding clauses, wherein each stress-relieving coating has a thickness between 10 nanometers and 50 nanometers. 24. The method according to any one of the preceding clauses further comprises: preparing a first surface of the first semiconductor substrate and a second surface of the second semiconductor substrate, and providing the stress-relieving coating to at least one of the first bonding surface and the second bonding surface. 25. The method according to clause 24, wherein the providing step comprises: providing a stress-relieving coating to the first surface of the first semiconductor substrate, and not providing a stress-relieving coating to the second surface of the second semiconductor substrate. 26. The method according to claim 25, wherein the bonding step comprises: bonding an outer surface of a stress-relief coating provided to the first surface of the first semiconductor substrate to the second surface of the second semiconductor substrate to obtain the bonded substrate. 27. The method according to claim 24, wherein the providing step comprises: providing a first stress-relieving coating to the first surface of the first semiconductor substrate and providing a second stress-relieving coating to the second surface of the second semiconductor substrate. 28. The method according to item 27, wherein the bonding step comprises: connecting a first outer surface of the first stress-relieving coating to a second outer surface of the second stress-relieving coating to obtain the bonded substrate. 29. The method according to any one of the preceding clauses further comprises performing photolithographic patterning and / or processing on one or both of the back sides of the bonded substrate. 30. A bonded substrate manufactured using the method according to any one of the preceding clauses.

[0087] The terms “radiation” and “beam” used in relation to lithography equipment cover all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., having wavelengths of 365 nm, 355 nm, 248 nm, 193 nm, 157 nm, or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having wavelengths in the range of 5 nm to 20 nm), as well as particle beams (such as ion beams or electron beams).

[0088] Where the context permits, the term “lens” can refer to any one or a combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic, and electrostatic optical components.

[0089] The above description of specific embodiments will fully reveal the general nature of the invention. Various applications of these specific embodiments can be easily modified and / or adapted without departing from the general concept of the invention, using knowledge in the art, without excessive experimentation. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology in this specification is for the purpose of description by way of example and not for limitation, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0090] The breadth and scope of this invention should not be limited by any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for bonding a first semiconductor substrate to a second semiconductor substrate, the method comprising: A stress-relief coating is provided to at least one of the first semiconductor substrate and the second semiconductor substrate; as well as The first semiconductor substrate is bonded to the second semiconductor substrate to form a bonded substrate; The stress-relieving coating is configured to enhance the bonding strength between the first semiconductor substrate and the second semiconductor substrate, and to reduce the amount of bonding-induced stress in the bonded substrate.

2. The method according to claim 1, wherein, The providing step includes: depositing a stress-relieving coating onto at least one of the first semiconductor substrate and the second semiconductor substrate, each stress-relieving coating comprising the following material properties at room temperature: Young's modulus E < 5×10 -2 GPa; Complex modulus G < 5×10 -3 GPa; Viscosity 10 3 < μ < 10 5 Pa•s.

3. The method according to claim 2, wherein, The providing step further includes: prior to the bonding step, hardening the stress-relief coating deposited on at least one of the first semiconductor substrate and the second semiconductor substrate.

4. The method according to claim 3, further comprising: After the bonding step, the stress-relieving coating deposited on at least one of the first semiconductor substrate and the second semiconductor substrate is softened to reduce the amount of stress caused by bonding in the bonded substrate.

5. The method according to claim 2, wherein, The stress-relief coating is deposited onto at least one of the first semiconductor substrate and the second semiconductor substrate via a spin-coating deposition process.

6. The method according to claim 1, wherein, The providing step includes: depositing a coating onto at least one of the first semiconductor substrate and the second semiconductor substrate; and patterning the coating deposited onto at least one of the first semiconductor substrate and the second semiconductor substrate to provide the stress-relieving coating.

7. The method according to claim 6, wherein, The deposited coating has the following material properties at room temperature: Young's modulus E > 5×10 -2 GPa; Complex modulus G > 5 × 10 -3 GPa; Viscosity μ > 10 5 Pa•s.

8. The method according to claim 6, wherein, Each patterned stress-relief coating includes a plurality of spatially separated protrusions projecting outward from the first semiconductor substrate and / or the second semiconductor substrate.

9. The method according to claim 8, wherein, The multiple spatially separated protrusions are arranged in a two-dimensional array.

10. The method according to claim 1, wherein, Each stress-relieving coating includes a dielectric layer.

11. The method according to claim 10, wherein, The dielectric layer is a layer of silicon dioxide (SiO2) or silicon carbonitride (SiCN).

12. The method according to claim 1, wherein, Each stress-relieving coating includes a dielectric layer and a plurality of conductive pads embedded within the dielectric layer.

13. The method according to claim 12, wherein, The providing steps include: The dielectric layer is deposited onto at least one of the first semiconductor substrate and the second semiconductor substrate; Etching the deposited dielectric layer; and Electroplating at least a portion of the etched dielectric layer to form a plurality of embedded conductive pads.

14. The method according to claim 1, further comprising: Photolithographic patterning and / or processing are performed on one or both of the back sides of the bonded substrates.

15. A bonded substrate manufactured using the method according to claim 1.

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