Component for semiconductor manufacturing apparatus and method for manufacturing the same

Abstract

The present application provides a manufacturing method of a second semiconductor manufacturing device member using a first semiconductor manufacturing device member as a raw material. In the manufacturing method, a second semiconductor manufacturing device member provided with a second ceramic substrate is manufactured using a first semiconductor manufacturing device member provided with a first ceramic substrate provided with an upper surface having a plurality of protrusions capable of placing a wafer and a built-in electrode, and the second ceramic substrate provided with an upper surface having a plurality of protrusions capable of placing a wafer and a built-in electrode. The manufacturing method includes: process A, processing the upper surface of the first ceramic substrate to form a flat surface from which the plurality of protrusions are removed; process B1, joining the flat surface of the first ceramic substrate to a lower surface of a ceramic plate at room temperature to form a second ceramic substrate formed by joining the first ceramic substrate and the ceramic plate; and process C, forming a plurality of protrusions capable of placing a wafer on an upper surface of the ceramic plate before or after the implementation of process B1.

Description

Technical Field

[0001] This invention relates to components for semiconductor manufacturing apparatuses. Furthermore, this invention relates to a method for manufacturing components for semiconductor manufacturing apparatuses. Background Technology

[0002] Previously, components for semiconductor manufacturing apparatuses, used for holding, temperature control, and transporting wafers, were known. These components, also known as wafer stages, electrostatic chucks, or bases, typically have the function of applying electrostatic power to built-in electrodes and adsorbing wafers using electrostatic force.

[0003] As a component for a semiconductor manufacturing apparatus, a component is known, for example, comprising: a ceramic substrate having an upper surface and a lower surface capable of supporting a wafer, and having electrodes built in thereon; and a base plate located on the lower surface side of the ceramic substrate, and having a refrigerant flow path built in thereon. A plurality of protrusions supporting the wafer are provided on the upper surface capable of supporting the wafer.

[0004] Such protrusions are generally small, and during dry cleaning using plasma, the ceramic particles constituting the protrusions sometimes detach, a phenomenon known as granulation. These detached ceramic particles become contaminated wafers, etc. Therefore, in order to suppress the detachment of ceramic particles constituting the protrusions, Patent Document 1 describes methods for controlling the size and surface roughness of the ceramic particles.

[0005] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2023-31112 Summary of the Invention

[0006] The technical problem that the invention aims to solve The shedding of ceramic particles that make up the protrusions can occur not only during dry cleaning processes, but also when wafers are electrostatically attached to an electrostatic chuck, or when the wafer slides due to thermal expansion upon contact with the protrusions. While delamination can occur due to a combination of factors such as wear and corrosion, it is unavoidable with prolonged use of components in semiconductor manufacturing equipment. Furthermore, due to reasons other than delamination, the protrusions can also deteriorate, potentially reducing the performance of components in semiconductor manufacturing equipment.

[0007] When the quality of components used in semiconductor manufacturing equipment deteriorates, it is possible to discard these deteriorated components. However, from the perspective of reducing waste, making efficient use of resources, and promoting a circular economy, it is desirable to repair and reuse these components.

[0008] In view of the above, in one embodiment of the present invention, the objective is to provide a method for manufacturing a second semiconductor manufacturing apparatus component using a first semiconductor manufacturing apparatus component as a raw material. Furthermore, in another embodiment of the present invention, the objective is to provide a semiconductor manufacturing apparatus component that can be manufactured by the manufacturing method according to one embodiment of the present invention.

[0009] Technical solutions for solving technical problems In order to solve the above-mentioned problems, the inventors conducted in-depth research and created the present invention as illustrated below.

[0010] [Method 1] A manufacturing method is a method of manufacturing a second semiconductor manufacturing apparatus component using a first semiconductor manufacturing apparatus component. The first semiconductor manufacturing apparatus component includes a first ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having internal electrodes. The second semiconductor manufacturing apparatus component includes a second ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having internal electrodes. The manufacturing method includes: Step A: The upper surface of the first ceramic substrate is processed to form a flat surface with the plurality of protrusions removed; Step B1 involves bonding the flat surface of the first ceramic substrate to the lower surface of the ceramic plate at room temperature to form a second ceramic substrate formed by bonding the first ceramic substrate and the ceramic plate; and Step C, before or after step B1, involves forming multiple protrusions on the upper surface of the ceramic plate that can support the wafer.

[0011] [Method 2] According to the manufacturing method described in [Method 1], the ceramic plate contains the same material as the ceramic constituting the first ceramic substrate.

[0012] [Method 3] According to the manufacturing method described in [Method 1] or [Method 2], the ceramic plate and the first ceramic substrate each contain one or two selected from alumina and aluminum nitride.

[0013] [Method 4] According to any one of [Method 1] to [Method 3], the lower surface of the ceramic plate is bonded to the flat surface of the first ceramic substrate via an amorphous layer.

[0014] [Method 5] According to any one of [Method 1] to [Method 4], the arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.

[0015] [Method 6] A manufacturing method is a method of manufacturing a second semiconductor manufacturing apparatus component using a first semiconductor manufacturing apparatus component. The first semiconductor manufacturing apparatus component includes a first ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having internal electrodes. The second semiconductor manufacturing apparatus component includes a second ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having internal electrodes. The manufacturing method includes: Step A involves processing the upper surface of the first ceramic substrate to form a flat surface with the plurality of protrusions removed; and In step B2, the flat surface of the first ceramic substrate is bonded to the lower end surface of a plurality of protrusion forming components at room temperature to form a second ceramic substrate formed by bonding the first ceramic substrate and the plurality of protrusion forming components.

[0016] [Method 7] According to the manufacturing method described in [Method 6], the plurality of protrusion forming components contain the same material as the ceramic constituting the first ceramic substrate.

[0017] [Method 8] According to the manufacturing method described in [Method 6] or [Method 7], the plurality of protrusion forming components and the first ceramic substrate each contain one or two selected from alumina and aluminum nitride.

[0018] [Method 9] According to any one of [Method 6] to [Method 8], the lower end face of the plurality of protrusion forming components is bonded to the flat surface of the first ceramic substrate via an amorphous layer.

[0019] [Method 10] According to any one of [method 6] to [method 9], the arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.

[0020] [Method 11] A component for a semiconductor manufacturing apparatus, comprising: Ceramic substrate with built-in electrodes; and A ceramic plate having: a lower surface bonded to the upper surface of the ceramic substrate via an amorphous layer; and an upper surface having a plurality of protrusions capable of supporting a wafer.

[0021] [Method 12] A component for a semiconductor manufacturing apparatus, comprising: Ceramic substrate with built-in electrodes; and Multiple protrusions have: a lower end face bonded to the upper surface of the ceramic substrate via an amorphous layer; and an upper end face for mounting a wafer.

[0022] [Method 13] According to the semiconductor manufacturing apparatus component described in [Method 11], the ceramic plate contains the same material as the ceramic constituting the ceramic substrate.

[0023] [Method 14] According to the semiconductor manufacturing apparatus component described in [Method 12], the plurality of protrusions contain the same material as the ceramic constituting the ceramic substrate.

[0024] Method 15 According to the semiconductor manufacturing apparatus component described in [Method 11] or [Method 13], the ceramic plate and the ceramic substrate each contain one or both selected from alumina and aluminum nitride.

[0025] [Method 16] According to the semiconductor manufacturing apparatus component described in [Method 12] or [Method 14], the plurality of protrusions and the ceramic substrate each contain one or two selected from alumina and aluminum nitride.

[0026] Invention Effects According to one embodiment of the present invention, a method for manufacturing a component for a semiconductor manufacturing apparatus can manufacture a second component for a semiconductor manufacturing apparatus using a first component for a semiconductor manufacturing apparatus as raw material. Therefore, even if the quality of the first component for a semiconductor manufacturing apparatus deteriorates due to factors such as delamination of ceramic particles constituting the wafer mounting surface, it is not necessary to remanufacture the component for the semiconductor manufacturing apparatus from the beginning. Thus, this manufacturing method greatly contributes to reducing waste and promoting a circular economy through efficient resource utilization. Attached Figure Description

[0027] Figure 1A This is a schematic partial longitudinal sectional view of a component for a semiconductor manufacturing apparatus according to Embodiment A of the present invention (a partial sectional view cut by a plane including the central axis of the component for a semiconductor manufacturing apparatus).

[0028] Figure 1BThis is a schematic partial longitudinal sectional view of a component for a semiconductor manufacturing apparatus according to Embodiment B of the present invention (a partial sectional view cut by a plane including the central axis of the component for a semiconductor manufacturing apparatus).

[0029] Figure 2A It is by Figure 1A The diagram shows a schematic enlarged view of the vicinity, surrounded by a thick frame.

[0030] Figure 2B It is by Figure 1B The diagram shows a schematic enlarged view of the vicinity, surrounded by a thick frame.

[0031] Figure 3A This is a schematic top view of the wafer mounting surface of the ceramic substrate according to Embodiment A of the present invention.

[0032] Figure 3B This is a schematic top view of the wafer mounting surface of the ceramic substrate according to Embodiment B of the present invention.

[0033] Figure 4A This is a manufacturing process diagram of a component for a semiconductor manufacturing apparatus according to Embodiment A of the present invention.

[0034] Figure 4B This is a manufacturing process diagram of a component for a semiconductor manufacturing apparatus according to Embodiment B of the present invention.

[0035] Figure 5 This is a schematic perspective view of a polishing apparatus used for polishing and grinding. Detailed Implementation

[0036] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the present invention is not limited to the following embodiments, and appropriate design changes and improvements can be made based on the common knowledge of those skilled in the art without departing from the spirit of the invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to indicate the relative positional relationship when the upper surface of the ceramic substrate of the semiconductor manufacturing apparatus component is set to the upper side and placed on a horizontal plane, and do not indicate an absolute positional relationship. Therefore, depending on the orientation of the semiconductor manufacturing apparatus component, "upper" and "lower" may become "lower" and "upper," or "left" and "right," or "front" and "rear."

[0037] <1. Structure of components used in semiconductor manufacturing equipment> (1-1. Implementation method A) Reference Figure 1AThe partial longitudinal sectional view shown illustrates that the semiconductor manufacturing apparatus component 10A according to Embodiment A of the present invention can be used in processes such as CVD and etching of a wafer W using plasma. The semiconductor manufacturing apparatus component 10A includes: a ceramic substrate 20 with built-in electrodes 26a; and a ceramic plate 70 having: a lower surface 73 bonded to the upper surface 21 of the ceramic substrate 20 via an amorphous layer 80; and an upper surface 71 having a plurality of protrusions 72 capable of supporting the wafer W. Furthermore, the semiconductor manufacturing apparatus component 10A includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a refrigerant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0038] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 when viewed from above, and an outer peripheral portion 20b having an annular upper surface 27 on the outer periphery of the central portion 20a when viewed from above. The central portion 20a of the ceramic substrate 20 can, for example, have a diameter of 130 mm to 450 mm and a thickness of 1 mm to 5 mm. A wafer W can be mounted on the upper surface 71 of a ceramic plate 70 bonded to the upper surface 21 of the central portion 20a. Furthermore, a focusing ring (not shown) can be mounted on the upper surface 27 of the outer peripheral portion 20b of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 20b is one level lower than the upper surface 21 of the central portion 20a. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b can also be on the same plane. The illustrated ceramic substrate 20 can also be configured to have a central portion 20a but not an outer peripheral portion 20b, i.e., without the lower upper surface 27.

[0039] A plurality of protrusions 72 for mounting the wafer W are provided on the upper surface 71 of the ceramic plate 70. Alternatively, the upper surface 71 may also have a sealing strip 75 formed along its outer edge. In this case, the wafer W may be supported by the upper end face 71c of the sealing strip 75 and the upper end faces 71a of the plurality of protrusions 72. The sealing strip 75 and the plurality of protrusions 72 are preferably set to the same height. Figure 3A As shown, in one embodiment, an annular sealing strip 75 is formed along the outer edge of the upper surface 71 of the ceramic plate 70, and a plurality of protrusions 72 are formed on the entire surface covering the inner side of the sealing strip 75.

[0040] Figure 2A yes Figure 1A The schematic enlarged view, enclosed by a thick frame, shows a schematic structure of the protrusion 72 disposed on the upper surface 71 of the ceramic plate 70. The number density of the protrusions 72 per unit area, viewed from above, can be set, for example, to 1 protrusion / mm². 2 ~150 pieces / mm 2 It can be set to 10 pieces / mm 2 ~150 pieces / mm 2The shape of protrusion 72 is not limited; for example, it can be a cylinder, prism, or other prism shape. The height h of protrusion 72 is, for example, 5. μ m~100 μ m, typically can be set to 10 μ m~30 μ m. Furthermore, the diameter d of the protrusion 72 is, for example, 0.3 mm to 3.0 mm, and typically can be set to 0.8 mm to 2.2 mm. Here, the diameter d of the protrusion 72 refers to the equivalent circle diameter when viewed from above. Furthermore, the portion of the upper surface 71 of the ceramic plate 70 without the sealing strip 75 and the protrusion 72 is referred to as the reference surface 71b.

[0041] The plurality of protrusions 72 may also have at least their upper surfaces 71a covered by a coating film. Similarly, at least their upper surfaces 71c of the sealing strip 75 may also be covered by a coating film. Examples of coating films include at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0042] From the viewpoint of improving thermal shock resistance by making their coefficients of thermal expansion similar, the ceramic plate 70 preferably contains the same material as the ceramic constituting the ceramic substrate 20. Specifically, in one embodiment, both the ceramic plate 70 and the ceramic substrate 20 contain one or both selected from alumina and aluminum nitride. In a preferred embodiment, both the ceramic plate 70 and the ceramic substrate 20 contain 80% by mass or more of one or both selected from alumina and aluminum nitride. In a more preferred embodiment, the ceramic plate 70 and the ceramic substrate 20 contain 95% by mass or more of one or both selected from alumina and aluminum nitride.

[0043] The upper surface 21 of the ceramic substrate 20 and the lower surface 73 of the ceramic plate 70 can be bonded via an amorphous layer 80. In this case, the amorphous layer 80 preferably contains at least one element constituting the ceramic substrate 20 and at least one element constituting the ceramic plate 70.

[0044] When observing a longitudinal section near the interface between the ceramic substrate 20 and the ceramic plate 70 of the semiconductor manufacturing apparatus component 10A using a transmission electron microscope (TEM) at 4 millionx magnification, the amorphous layer 80 is observed as a thin strip-like portion. The amorphous layer 80 is sometimes formed as a single layer, but sometimes it is formed as multiple layers (e.g., 3 layers). To improve the bonding strength between the ceramic substrate 20 and the ceramic plate 70, the average thickness of the amorphous layer 80 is preferably 0.1 nm or more, more preferably 1 nm or more. Furthermore, to prevent the incorporation of dissimilar materials, the average thickness of the amorphous layer 80 is preferably 30 nm or less, more preferably 20 nm or less. Therefore, the average thickness of the amorphous layer 80 is preferably, for example, 0.1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less. Furthermore, when the amorphous layer 80 is composed of multiple layers, the thickness of the amorphous layer 80 refers to the total thickness of those multiple layers.

[0045] The average thickness of the amorphous layer 80 at the interface between the ceramic plate 70 and the ceramic substrate 20, as measured by TEM, was determined according to the following steps. In a TEM image (magnification: 4 millionx) of a longitudinal section including the interface, the thickness of the amorphous layer 80 was measured at five points every 10 nm along the interface, and the average thickness of the amorphous layer in that field of view was calculated. This thickness measurement by TEM was performed on three fields of view: near the center, near the outer perimeter, and near the center of the radius when viewing the ceramic plate 70 from above. The average thickness of the amorphous layer 80 in the three fields of view was then taken as the measured value.

[0046] The fact that the fine bands observed by TEM are amorphous layer 80 can be confirmed by observing a peak that is wider than that of the ceramic substrate 20 and ceramic plate 70, which are sufficiently far from the bonding interface, inside the fine bands when obtaining the X-ray diffraction pattern obtained by XRD.

[0047] The fact that the amorphous layer 80 contains at least one element constituting the ceramic substrate 20 and at least one element constituting the ceramic plate 70 can be confirmed by methods such as EDS (Energy Dispersive X-ray Spectroscopy) or EPMA (Electron Probe Micro Analyzer). In a preferred embodiment, the amorphous layer 80 contains at least one amorphous material (e.g., amorphous aluminum nitride, amorphous alumina, etc.) constituting the ceramic substrate 20 and the ceramic plate 70.

[0048] Thus, the semiconductor manufacturing apparatus component 10A according to one embodiment of the present invention can make the bonding layer (amorphous layer 80) between the ceramic substrate 20 and the ceramic plate 70 extremely thin, thereby reducing the thermal resistance between the ceramic substrate 20 and the ceramic plate 70.

[0049] Electrode 26a is a planar electrode used as an electrostatic electrode, connected to an external DC power supply via a power supply component (not shown). Electrode 26a is formed, for example, of a material containing W, Mo, WC, MoC, etc. A low-pass filter may also be disposed in the middle of the power supply component. The power supply component is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26a, the wafer W is attracted and fixed to the wafer mounting surface, specifically the upper end surface 71c of the sealing strip 75 and the upper end surface 71a of the protrusion 72, by electrostatic attraction. When the DC voltage is released, the attraction and fixation of the wafer W to the wafer mounting surface is released.

[0050] As an electrode, it can replace the electrode used for electrostatic adsorption or the electrode (resistive heating element) 26b for building a heater, or it can build an RF electrode for plasma generation. In this case, the heater electrode 26b is connected to a heater power supply, and the RF electrode is connected to an RF power supply. The ceramic substrate 20 can have one layer of electrodes built in it, or two or more layers of electrodes can be built in it at intervals.

[0051] The base plate 30 can be, for example, circular. The base plate 30 may also have an annular flange on its lower surface, which serves as a clamp to hold the semiconductor manufacturing apparatus component 10A within the cavity. The thickness of the base plate 30 can be 20 mm to 40 mm, typically 25 mm to 35 mm. The base plate 30 can also be connected to a high-frequency (RF) power supply and used as an RF electrode.

[0052] The base plate 30 can be a circular plate with good electrical and thermal conductivity (a circular plate with the same diameter as or larger than that of the ceramic substrate 20). A refrigerant flow path 32 for refrigerant circulation can also be formed inside the base plate 30. The refrigerant flowing in the refrigerant flow path 32 is preferably a liquid, and preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant flow path 32 can, for example, be formed in a single stroke from one end (inlet) to the other end (outlet) of the entire base plate 30 when viewed from above. A supply port and a return port (not shown) of an external refrigerant device are connected to one end and the other end of the refrigerant flow path 32, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 returns to the return port of the external refrigerant device from the other end of the refrigerant flow path 32 after passing through the refrigerant flow path 32, and after being temperature-adjusted, is supplied back to one end of the refrigerant flow path 32 from the supply port.

[0053] The base plate 30 can be made of, for example, a metallic material or a composite material of metal and ceramic. Examples of metallic materials include Al, Ti, Mo, or alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMC) and ceramic matrix composites (CMC). Specific examples of such composite materials include materials containing Si, SiC, and Ti (also called SiSiCTi), materials formed by impregnating Al and / or Si in a porous SiC body, and composite materials of Al2O3 and TiC. Materials formed by impregnating Al in a porous SiC body are called AlSiC, and materials formed by impregnating Si in a porous SiC body are called SiSiC. As the material of the base plate 30, it is preferable to select a material whose coefficient of thermal expansion is close to that of the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, whose coefficient of thermal expansion is close to that of alumina.

[0054] like Figure 1A As shown, the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may, for example, be a metal layer formed by solder or brazing filler metal. The bonding layer 40 may be formed, for example, by TCB (Thermal Compression Bonding). TCB refers to a known method in which a metal bonding material is sandwiched between two components to be bonded, and the two components are pressure-bonded at a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of a metal layer. The resin bonding layer may, for example, be composed of cured products of silicone resin adhesives, epoxy resin adhesives, acrylic resin adhesives, or polyurethane resin adhesives.

[0055] At least one portion of the side surface of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered by the insulating film 35. Examples of insulating films 35 include sprayed films of alumina, yttrium oxide, etc.

[0056] In the above embodiment, the semiconductor manufacturing apparatus component 10A may also have a plurality of holes penetrating the ceramic plate 70 and the ceramic substrate 20 in the vertical direction. These holes include a plurality of vent holes 50 opening on the upper surface 71 and a lifting pin hole for inserting a lifting pin, which is used to move the wafer W vertically relative to the upper surface 21. When viewed from above, the plurality of vent holes 50 can be provided at appropriate locations (see reference...). Figure 3AThe vent 50 communicates with a gas flow path provided inside the base plate 30, and can supply a heat-conducting gas such as He gas that has passed through the gas flow path. Typically, the vent 50 can be provided with an opening in a portion (reference surface 71b) of the upper surface 71 where the sealing strip 75 and multiple protrusions 72 are not provided. Furthermore, the vent 50 is formed in a position that does not overlap with the electrode 26. When heat-conducting gas is supplied to the vent 50, the heat-conducting gas fills the space on the back side of the wafer W placed on the upper surface 71. A plug 55 having a gas flow path can also be embedded in the vent 50. Multiple lifting pin holes can be provided at equal intervals along concentric circles of the upper surface 71 when viewed from above.

[0057] (1-2. Implementation method B) Reference Figure 1B The partial longitudinal sectional view shown illustrates that the semiconductor manufacturing apparatus component 10B according to Embodiment B of the present invention can be used in processes such as CVD and etching of a wafer W using plasma. The semiconductor manufacturing apparatus component 10B includes: a ceramic substrate 20 with built-in electrodes 26a; and a plurality of protrusions 92 having: a lower end face 92b bonded to the upper surface 21 of the ceramic substrate 20 via an amorphous layer 80; and an upper end face 92a for mounting the wafer W. Furthermore, the semiconductor manufacturing apparatus component 10B includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and having a built-in coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0058] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 when viewed from above, and an outer peripheral portion 20b having an annular upper surface 27 on the outer periphery of the central portion 20a when viewed from above. The central portion 20a of the ceramic substrate 20 can, for example, have a diameter of 190 mm to 450 mm and a thickness of 1 mm to 5 mm. A wafer W can be mounted on the upper end surface 92a of a plurality of protrusions 92 bonded to the upper surface 21 of the central portion 20a. Furthermore, a focusing ring (not shown) can be mounted on the upper surface 27 of the outer peripheral portion 20b of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 20b is one level lower than the upper surface 21 of the central portion 20a. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b can also be on the same plane. The illustrated ceramic substrate 20 can also be configured to have a central portion 20a but not an outer peripheral portion 20b, that is, it can also omit the lower upper surface 27.

[0059] A plurality of protrusions 92 for mounting the wafer W are bonded to the upper surface 21 of the ceramic substrate 20 via an amorphous layer 80. Alternatively, a sealing strip 95 formed along its outer edge may be bonded to the upper surface 21 via the amorphous layer 80. In this case, the wafer W can be supported by the upper end face 95a of the sealing strip 95 and the upper end faces 92a of the plurality of protrusions 92. Preferably, the sealing strip 95 and the plurality of protrusions 92 have the same height. Figure 3B As shown, in one embodiment, an annular sealing strip 95 is joined along the outer edge of the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 92 are joined on the entire inner surface of the sealing strip 95.

[0060] Figure 2B yes Figure 1B The schematic enlarged view, enclosed by a thick frame, shows a schematic structure of the protrusion 92 bonded to the upper surface 21 of the ceramic substrate 20. The number density of the protrusions 92 per unit area, viewed from above, can be set, for example, to 1 protrusion / mm². 2 ~150 pieces / mm 2 It can be set to 10 pieces / mm 2 ~150 pieces / mm 2 The shape of protrusion 92 is not limited; for example, it can be a cylinder, prism, or other prism shape. The height h of protrusion 92 is, for example, 5. μ m~100 μ m, typically can be set to 10 μ m~30 μ m. Furthermore, the diameter d of the protrusion 92 is, for example, 0.3 mm to 3.0 mm, and typically can be set to 0.8 mm to 2.2 mm. Here, the diameter d of the protrusion 92 refers to the equivalent circle diameter when viewed from above.

[0061] The multiple protrusions 92 may also be covered at least on their upper surfaces by a coating film. Similarly, at least the upper surface 95a of the sealing strip 95 may also be covered by a coating film. Examples of coating films include those comprising at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0062] From the viewpoint of improving thermal shock resistance by making their coefficients of thermal expansion similar, the plurality of protrusions 92 preferably contain the same material as the ceramic constituting the ceramic substrate 20. Similarly, the sealing strip 95 preferably contains the same material as the ceramic constituting the ceramic substrate 20. Specifically, in one embodiment, both the protrusions 92 and the ceramic substrate 20 contain one or both selected from alumina and aluminum nitride. In another embodiment, the protrusions 92, the sealing strip 95, and the ceramic substrate 20 each contain one or both selected from alumina and aluminum nitride. In a preferred embodiment, both the protrusions 92 and the ceramic substrate 20 each contain 80% by mass or more of one or both selected from alumina and aluminum nitride. In another preferred embodiment, the protrusions 92, the sealing strip 95, and the ceramic substrate 20 each contain 80% by mass or more of one or both selected from alumina and aluminum nitride. In a more preferred embodiment, the protrusions 92 and the ceramic substrate 20 contain 95% by mass or more of one or both selected from alumina and aluminum nitride. In another preferred embodiment, the protrusion 92, the sealing strip 95, and the ceramic substrate 20 contain more than 95% by mass of one or both selected from alumina and aluminum nitride.

[0063] The upper surface 21 of the ceramic substrate 20 and the lower end face 92b of the plurality of protrusions 92 can be bonded via an amorphous layer 80. In this case, the amorphous layer 80 preferably includes at least one element constituting the ceramic substrate 20 and at least one element constituting the plurality of protrusions 92. Similarly, the upper surface 21 of the ceramic substrate 20 and the lower end face 95b of the sealing strip 95 can be bonded via an amorphous layer 80. In this case, the amorphous layer 80 preferably includes at least one element constituting the ceramic substrate 20 and at least one element constituting the sealing strip 95.

[0064] When observing a longitudinal section near the interface between the ceramic substrate 20 of the semiconductor manufacturing apparatus component 10A and the plurality of protrusions 92 or sealing strips 95 using a transmission electron microscope (TEM) at 4 millionx, the amorphous layer 80 is observed as a thin strip-like portion. The amorphous layer 80 is sometimes formed as a single layer, but sometimes it is formed as multiple layers (e.g., 3 layers). To improve the bonding strength between the ceramic substrate 20 and the plurality of protrusions 92 or sealing strips 95, the average thickness of the amorphous layer 80 is preferably 0.1 nm or more, more preferably 1 nm or more. Furthermore, to prevent the incorporation of dissimilar materials, the average thickness of the amorphous layer 80 is preferably 30 nm or less, more preferably 20 nm or less. Therefore, the average thickness of the amorphous layer 80 is preferably, for example, 0.1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less. Furthermore, when the amorphous layer 80 is composed of multiple layers, the thickness of the amorphous layer 80 refers to the total thickness of the multiple layers.

[0065] The average thickness of the amorphous layer 80 at the interface between each protrusion 92 and the ceramic substrate 20, as measured by TEM, was determined according to the following steps. A TEM image of a longitudinal section including the interface near the center of the protrusion 92 to be measured was obtained. Then, on a TEM image of one field of view (magnification: 4 millionx), the thickness of the amorphous layer 80 was measured at three locations every 10 nm along the interface, and the average thickness of the amorphous layer in one field of view was calculated as the measured value.

[0066] The average thickness of the amorphous layer 80 at the interface between the sealing strip 95 and the ceramic substrate 20, as measured by TEM, was determined according to the following steps. In a TEM image (magnification: 4 millionx) of a longitudinal section including the interface, the thickness of the amorphous layer 80 was measured at five points every 10 nm along the interface, and the average thickness of the amorphous layer in one field of view was calculated. This thickness measurement by TEM was performed at equal intervals (every 120°) along the circumference of the sealing strip 95 for three fields of view. The average thickness of the amorphous layer 80 in the three fields of view was then taken as the measured value.

[0067] The fact that the fine band observed by TEM is an amorphous layer 80 can be confirmed by the following: when obtaining the X-ray diffraction pattern by XRD, a peak wider than that of the ceramic substrate 20 and the protrusion 92 (sealing strip 95) that is sufficiently far from the bonding interface is observed on the inner side of the fine band.

[0068] The fact that the amorphous layer 80 comprises at least one element constituting the ceramic substrate 20 and at least one element constituting the plurality of protrusions 92 (or sealing strips 95) can be confirmed by methods such as EDS (Energy Dispersive X-ray Spectroscopy) or EPMA (Electron Probe Micro Analyzer). In a preferred embodiment, the amorphous layer 80 comprises at least one amorphous material (e.g., amorphous aluminum nitride, amorphous alumina, etc.) constituting the ceramic substrate 20 and the plurality of protrusions 92 (or sealing strips 95).

[0069] Thus, the semiconductor manufacturing apparatus component 10B according to one embodiment of the present invention can make the bonding layer (amorphous layer 80) between the ceramic substrate 20 and the plurality of protrusions 92 (or sealing strips 95) extremely thin, thereby reducing the thermal resistance between the ceramic substrate 20 and the plurality of protrusions 92 (or sealing strips 95).

[0070] Other structures such as electrodes 26a, 26b, base plate 30, and bonding layer 40 are as described in Embodiment A, therefore repeated descriptions are omitted.

[0071] <2. Manufacturing Method of Components for Semiconductor Manufacturing Apparatus> According to one embodiment of the present invention, a method is provided for manufacturing a second semiconductor manufacturing apparatus component using a first semiconductor manufacturing apparatus component. The first semiconductor manufacturing apparatus component includes a first ceramic substrate having an upper surface having a plurality of protrusions (first plurality of protrusions) capable of mounting a wafer and having internal electrodes. The second semiconductor manufacturing apparatus component includes a second ceramic substrate having an upper surface having a plurality of protrusions (second plurality of protrusions) capable of mounting a wafer and having internal electrodes. In one embodiment, the second semiconductor manufacturing apparatus component corresponds to the semiconductor manufacturing apparatus component 10A according to embodiment A. Furthermore, in another embodiment, the second semiconductor manufacturing apparatus component corresponds to the semiconductor manufacturing apparatus component 10B according to embodiment B.

[0072] (2-1. Method for manufacturing a component for a semiconductor manufacturing apparatus according to Embodiment A) Reference Figure 4A The manufacturing method of a component for a semiconductor manufacturing apparatus according to Embodiment A is illustrated by way of example.

[0073] First, a first semiconductor manufacturing apparatus component 100 is prepared. As the first semiconductor manufacturing apparatus component 100, any known semiconductor manufacturing apparatus component having a first ceramic substrate 120 can be used. The first ceramic substrate 120 has an upper surface 22 having a plurality of protrusions 22a (first plurality of protrusions) capable of supporting a wafer W, and has built-in electrodes 26a. The first semiconductor manufacturing apparatus component 100 can be an unused product or a used product (a product used in a semiconductor manufacturing process). The first semiconductor manufacturing apparatus component 100 is typically a used product, such as a used product whose protrusions 22a are of inferior quality to unused products, or a defective product that, although unused, does not exhibit the given characteristics.

[0074] The first ceramic substrate 120 can be manufactured, for example, by a manufacturing method including the following steps: a step of forming a shaped body as ceramic powder and having an embedded electrode; a step of forming a sintered ceramic body by hot pressing and sintering the shaped body; and a step of forming a plurality of protrusions on the upper surface of the sintered ceramic body by laser processing or sandblasting. The shaped body can be made by stacking multiple strip-shaped bodies, by mold casting, or by compacting ceramic powder.

[0075] Furthermore, the component 100 for the first semiconductor manufacturing apparatus may have a base plate 30 bonded to the lower surface of the first ceramic substrate 120 via a bonding layer 40. The bonding method between the first ceramic substrate 120 and the base plate 30 is not limited; for example, TCB (Thermal Compression Bonding) can be used. As the bonding material used to form the bonding layer 40, metal bonding materials such as Al-Mg based bonding materials and Al-Si-Mg based bonding materials can be used. When using an Al-Si-Mg based bonding material for TCB, the laminate is pressurized under a vacuum atmosphere while in a heated state. The metal bonding material preferably has a thickness of 100 mm. μ Materials around m in size.

[0076] Furthermore, the base plate 30 may include a refrigerant flow path 32. The base plate 30 with the refrigerant flow path 32 can be manufactured, for example, by joining multiple MMC plate components with grooves and holes corresponding to the refrigerant flow path 32 formed by machining using a method such as TCB (Thermal Compression Bonding). Alternatively, a gas flow path can be formed, extending from the upper surface to the lower surface of the base plate 30 and having an opening on the lower surface. The gas flow path can be formed by machining the base plate 30 after the refrigerant flow path 32 has been formed.

[0077] As a component for the first semiconductor manufacturing apparatus, the component for the semiconductor manufacturing apparatus according to Embodiment A above can be used, or the component for the semiconductor manufacturing apparatus according to Embodiment B can be used.

[0078] In one embodiment, the manufacturing method includes the following steps: Step A: The upper surface 22 of the first ceramic substrate 120 is processed to form a flat surface 24 with multiple protrusions 22a (first multiple protrusions) removed. In step B1, the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 are bonded at room temperature to form a second ceramic substrate 220 formed by bonding the first ceramic substrate 120 and the ceramic plate 70; and In step C, before or after step B1, a plurality of protrusions 72 (a second plurality of protrusions) capable of supporting the wafer W are formed on the upper surface 71 of the ceramic plate 70.

[0079] In step A, the upper surface 22 of the first ceramic substrate 120 is processed to form a flat surface 24 with the plurality of protrusions 22a (the first plurality of protrusions) removed. The processing method is not particularly limited; for example, polishing is preferred. Furthermore, it is preferable to process the surface to a position above the location of the embedded electrodes. The flat surface 24 of the first ceramic substrate 120 is preferably processed such that the surface roughness (arithmetic mean roughness) Ra, measured according to ISO 25178 using a non-contact surface roughness meter, is less than 1 nm (e.g., 0.2 nm to 1 nm).

[0080] Polishing and grinding are, for example, using Figure 5 The polishing apparatus 60 shown describes a method for polishing the upper surface 22 of a first ceramic substrate 120. The polishing apparatus 60 includes: a disc-shaped polishing platform 62 with a large diameter, which has a polishing pad 64; a disc-shaped carrier 66 with a small diameter; and a tube 68 that supplies a slurry containing abrasive grains to the polishing pad 64. The polishing platform 62 has a shaft 67 at the center of its lower surface, which rotates by a drive motor (not shown). The carrier 66 has a shaft 69 at the center of its upper surface, which rotates by a drive motor (not shown). The carrier 66 is positioned off-center from the polishing platform 62.

[0081] To grind the upper surface 22 of the first ceramic substrate 120 using the grinding apparatus 60, a first semiconductor manufacturing apparatus component 100 is mounted on the lower surface of the carrier 66. The first semiconductor manufacturing apparatus component 100 is sandwiched between the grinding pad 64 of the grinding platform 62 and the carrier 66, so that the upper surface 22 of the first ceramic substrate 120 contacts the grinding pad 64. Then, a slurry containing abrasive grains is supplied to the grinding pad 64 through the tube 68. Thus, the slurry is supplied between the first ceramic substrate 120 and the grinding pad 64 of the grinding platform 62. In this state, while pressing the first semiconductor manufacturing apparatus component 100 against the grinding pad 64 by the carrier 66, the grinding platform 62 and the carrier 66 rotate to perform grinding.

[0082] Next, in step B1, the flat surface 24 of the first ceramic substrate 120 is bonded to the lower surface 73 of the ceramic plate 70 at room temperature to form a second ceramic substrate 220 formed by bonding the first ceramic substrate 120 and the ceramic plate 70. Room temperature bonding is a method in which the bonding surface is activated by irradiation with a fast atomic beam (FAB) without heating, and bonding is performed while an amorphous layer is formed on the surface. Therefore, typically the lower surface 73 of the ceramic plate 70 and the flat surface 24 of the first ceramic substrate 120 are bonded via an amorphous layer.

[0083] From the viewpoint of improving thermal shock resistance by making their coefficients of thermal expansion similar, the ceramic plate 70 preferably contains the same material as the ceramic constituting the first ceramic substrate 120. Specifically, in one embodiment, both the ceramic plate 70 and the first ceramic substrate 120 contain one or both selected from alumina and aluminum nitride. In a preferred embodiment, both the ceramic plate 70 and the first ceramic substrate 120 contain 80% by mass or more of one or both selected from alumina and aluminum nitride. In a more preferred embodiment, both the ceramic plate 70 and the first ceramic substrate 120 contain 95% by mass or more of one or both selected from alumina and aluminum nitride.

[0084] The thickness of the ceramic plate 70 can be set to, for example, 0.1 mm to 1 mm.

[0085] The surface roughness (arithmetic mean roughness) Ra of the lower surface 73 of the ceramic plate 70, measured according to ISO 25178 standard using a non-contact surface roughness meter, is preferably less than 1 nm, for example, it can be set to 0.2 nm to 1 nm. In order to make the lower surface 73 of the ceramic plate 70 such a flat surface, it is preferable to perform polishing and grinding in the same way as the first ceramic substrate 120.

[0086] Next, surface activation treatment (FAB or plasma activation treatment) is performed on the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 under high vacuum. For example, the FAB conditions are set to a voltage of 0.5kV to 2kV, a current of 50mA to 200mA, and an irradiation time of 30 to 300 seconds. As a result, oxides and adsorbed molecules on the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 are removed, and an amorphous layer is formed and activated on these surfaces. Then, while maintaining high vacuum conditions, the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 are aligned, and room temperature bonding is performed while applying pressure. The load during pressure application can be set to, for example, 0.1kN to 50kN. After room temperature bonding, to improve the bonding strength, the second ceramic substrate 220 can be heated at approximately 100°C for more than 1 hour.

[0087] In step C, a plurality of protrusions 72 (second plurality of protrusions) capable of supporting the wafer W are formed on the upper surface 71 of the ceramic plate 70. The plurality of protrusions 72 formed here may or may not be arranged in the same manner as the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120. Furthermore, the height and diameter of each of the second plurality of protrusions may or may not be the same as the height and diameter of the first plurality of protrusions. Step C may be performed before or after step B1. The plurality of protrusions 72 can be formed on the upper surface 71 of the ceramic plate 70 by laser processing or sandblasting. Furthermore, since the upper surfaces of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120 deteriorate due to use, the upper surfaces of the plurality of protrusions 72 (second plurality of protrusions) on the upper surface 71 of the ceramic plate 70 in the second ceramic substrate 220 typically have a different surface roughness Ra than the upper surfaces of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120.

[0088] (2-2. Method for manufacturing components for a semiconductor manufacturing apparatus according to Embodiment B) Next, refer to Figure 4B The manufacturing method of a component for a semiconductor manufacturing apparatus according to Embodiment B is illustrated by way of example.

[0089] First, a component 100 for a first semiconductor manufacturing apparatus is prepared. Regarding the component 100 for the first semiconductor manufacturing apparatus, as described in the manufacturing method of a component for a semiconductor manufacturing apparatus according to Embodiment A, repeated descriptions are omitted.

[0090] In one embodiment, the manufacturing method includes the following steps: Step A involves processing the upper surface 22 of the first ceramic substrate 120 to form a flat surface 24 with multiple protrusions 22a (the first plurality of protrusions) removed; and In step B2, the flat surface 24 of the first ceramic substrate 120 is bonded to the lower end surface 192a of the plurality of protrusion forming components 192 at room temperature to form a second ceramic substrate 220 formed by bonding the first ceramic substrate 120 and the plurality of protrusion forming components 192.

[0091] Process A is as described in the method for manufacturing a component for a semiconductor manufacturing apparatus according to Embodiment A, therefore repeated descriptions are omitted.

[0092] Next, in step B2, the flat surface 24 of the first ceramic substrate 120 is bonded to the lower end surface 192a of the plurality of protrusion forming members 192 at room temperature to form a second ceramic substrate 220 formed by bonding the first ceramic substrate 120 and the plurality of protrusion forming members 192. In this case, typically the lower end surface 192a of the plurality of protrusion forming members 192 is bonded to the flat surface 24 of the first ceramic substrate 120 via an amorphous layer. Furthermore, since the upper end surfaces of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120 deteriorate due to use, typically the upper end surfaces of the plurality of protrusion forming members 192 have a different surface roughness Ra than the upper end surfaces of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120.

[0093] The multiple protrusion forming components 192 are components that ultimately become protrusions 72 (the second plurality of protrusions), and can be set to a cylindrical, prism, or other columnar shape corresponding to the protrusions 72. The height h of the protrusion forming components 192 is, for example, 5. μ m~100 μ m, typically can be set to 10 μ m~30 μ m. In addition, the diameter d of the protrusion forming component 192 is, for example, 0.3 mm to 3.0 mm, and can typically be set to 0.8 mm to 2.2 mm.

[0094] Alternatively, the flat surface 24 of the first ceramic substrate 120 can be bonded to the lower end surface 195a of the sealing strip forming member 195 at room temperature to form a second ceramic substrate 220 formed by bonding the first ceramic substrate 120 and the sealing strip forming member 195. In this case, typically, the lower end surface 195a of the sealing strip forming member 195 and the flat surface 24 of the first ceramic substrate 120 are bonded via an amorphous layer. The sealing strip forming member 195 is the component that ultimately becomes the sealing strip 95 and can have an annular (typically circular) shape corresponding to the sealing strip 95. The thickness is preferably the same as that of the protrusion forming member 192.

[0095] From the viewpoint of improving thermal shock resistance by making their coefficients of thermal expansion similar, the protrusion forming component 192 preferably contains the same material as the ceramic constituting the first ceramic substrate 120. Similarly, the sealing strip forming component 195 preferably contains the same material as the ceramic constituting the first ceramic substrate 120. Specifically, in one embodiment, both the protrusion forming component 192 and the first ceramic substrate 120 contain one or both selected from alumina and aluminum nitride. In another embodiment, the protrusion forming component 192, the sealing strip forming component 195, and the first ceramic substrate 120 all contain one or both selected from alumina and aluminum nitride. In a preferred embodiment, both the protrusion forming component 192 and the first ceramic substrate 120 contain 80% by mass or more of one or both selected from alumina and aluminum nitride. In another preferred embodiment, the protrusion forming component 192, the sealing strip forming component 195, and the first ceramic substrate 120 all contain 80% by mass or more of one or both selected from alumina and aluminum nitride. In a more preferred embodiment, the protrusion forming component 192 and the first ceramic substrate 120 contain 95% by mass or more of one or both selected from alumina and aluminum nitride. In another more preferred embodiment, the protrusion forming component 192, the sealing strip forming component 195, and the first ceramic substrate 120 contain 95% by mass or more of one or both selected from alumina and aluminum nitride.

[0096] The surface roughness (arithmetic mean roughness) Ra of the lower end face 192a of the plurality of protrusion forming components 192, measured according to ISO 25178 standard using a non-contact surface roughness meter, is preferably 1 nm or less, for example, it can be set to 0.2 nm to 1 nm. In order to make the lower end face 192a of the plurality of protrusion forming components 192 such a flat surface, it is preferable to perform polishing and grinding in the same manner as the first ceramic substrate 120. As a method for manufacturing the plurality of protrusion forming components 192 having such a flat lower end face 192a, an example is to perform polishing and grinding on the lower surface of the ceramic plate, and then cut out the plurality of protrusion forming components 192 by laser processing.

[0097] Similarly, the surface roughness (arithmetic mean roughness) Ra of the lower end surface 195a of the sealing tape forming component 195, measured according to ISO 25178 standard using a non-contact surface roughness meter, is preferably 1 nm or less, for example, it can be set to 0.2 nm to 1 nm. In order to make the lower end surface 195a of the sealing tape forming component 195 such a flat surface, it is preferable to perform polishing and grinding in the same way as the first ceramic substrate 120.

[0098] Next, surface activation treatment (high-speed atomic beam (FAB) or plasma activation treatment) is performed on the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 195a of the plurality of protrusion forming members 192 under high vacuum. For example, the FAB conditions are set to a voltage of 0.5 kV to 2 kV, a current of 50 mA to 200 mA, and an irradiation time of 30 to 300 seconds. As a result, oxides and adsorbed molecules on the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 192a of the plurality of protrusion forming members 192 are removed, and an amorphous layer is formed and activated on these surfaces. Then, while maintaining high vacuum conditions, the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 192a of the plurality of protrusion forming members 192 are aligned, and room temperature bonding is performed while applying pressure. The load during pressure application can be set to, for example, 0.1 kN to 50 kN. When aligning the flat surface 24 of the first ceramic substrate 120 with the lower end face 192a of the plurality of protrusion forming members 192, the following method can be employed: A die is prepared with a plurality of holes corresponding to the portions where the plurality of protrusion forming members 192 are to be positioned, so that the plurality of protrusion forming members 192 are positioned at a given location. After the plurality of protrusion forming members 192 are positioned in the plurality of holes, the die is removed, and then room temperature bonding is performed. After room temperature bonding, to improve the bonding strength, the second ceramic substrate 220 may be heated at approximately 100°C for at least one hour.

[0099] When bonding the flat surface 24 of the first ceramic substrate 120 to the lower end surface 195a of the sealing tape forming member 195 at room temperature, the same steps can be performed. That is, the flat surface 24 of the first ceramic substrate 120 and the lower end surface 195a of the sealing tape forming member 195 are subjected to surface activation treatment (high-speed atomic beam (FAB) or plasma activation treatment) under high vacuum. Then, while maintaining high vacuum conditions, the flat surface 24 of the first ceramic substrate 120 and the sealing tape forming member 195 are aligned and bonded at room temperature while applying pressure. The FAB conditions and the room temperature bonding conditions are the same as those when bonding the flat surface 24 of the first ceramic substrate 120 and the lower end surface 195a of the plurality of protrusion forming members 192 at room temperature.

[0100] In this embodiment, even though there are pores and lifting pin holes on the upper surface 22 of the first ceramic substrate 120, there is no process to block them, thus having the advantage that these holes do not need to be formed again.

[0101] <3. Usage of Components for Semiconductor Manufacturing Equipment> Next, an illustrative description of the usage method of the semiconductor manufacturing apparatus component 10A (10B) will be provided. First, the semiconductor manufacturing apparatus component 10A (10B) is placed in a chamber (not shown). A focusing ring is mounted on the upper surface 27 of the semiconductor manufacturing apparatus component 10A (10B), and a disk-shaped wafer W is placed on the wafer mounting surface, namely the upper end surface 71a of the protrusion 72 (upper end surface 92a of the protrusion 92) and the upper end surface 71c of the sealing strip 75 (upper end surface 95a of the sealing strip 95). Then, the vacuum level in the chamber is adjusted to a given level by depressurizing the vacuum chamber using a vacuum pump, and a voltage is applied to the electrode 26a of the ceramic substrate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface.

[0102] Next, a process gas is supplied from a spray head (not shown) to create a reactive gas atmosphere at a given pressure (tens to hundreds of Pa) inside the chamber. In this state, a high-frequency voltage, such as an RF voltage, is applied between an upper electrode (not shown) located at the top of the chamber and the base plate 30 of the semiconductor manufacturing apparatus component 10A (10B). Plasma is then generated between the wafer W and the spray head. The wafer W is then processed using this plasma (CVD deposition or etching is performed).

[0103] The refrigerant circulates in the refrigerant flow path 32 of the base plate 30. One end of the refrigerant flow path 32 is connected to the supply port and the return port of an external refrigerant device (not shown) via refrigerant piping. Refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 returns to the return port of the external refrigerant device from the other end of the refrigerant flow path 32 after passing through it. After being temperature-adjusted, it is then supplied back to one end of the refrigerant flow path 32 from the supply port.

[0104] A gas flow path (not shown) is formed inside the base plate 30, allowing back-side gas to be introduced from a gas storage bottle (not shown). A heat-conducting gas (such as He gas) can be used as the back-side gas. After passing through the gas flow path inside the base plate 30, the back-side gas flows out through the vent 50 and fills the space on the back side of the wafer W.

[0105] In addition, the focusing ring 78 is also consumed as the wafer W is plasma processed, but since the focusing ring 78 is thicker than the wafer W, the focusing ring 78 is replaced after multiple wafers W have been processed.

[0106] Example The following experimental data demonstrates the superior bonding strength of amorphous layers.

[0107] (Experimental Example 1: Formation of AD membrane) A SiSiCTi plate (20mm × 20mm × 5mm) was prepared as a type of MMC. An aerosol-deposited film (AD film) was formed on the entire upper surface of the plate using alumina powder (99.9% purity) via aerosol deposition. Next, the plate was cut along its thickness direction through a cut line near the center of the upper surface, exposing a longitudinal section. The thickness of the AD film was measured using a scanning electron microscope (SEM) at 3000x magnification, and the result was 3. μ Approximately m.

[0108] (Experimental Example 2: Formation of Spray-coated Film) Prepare a SiSiCTi plate identical to that used in Experimental Example 1. Spray-coat the entire upper surface of the plate with alumina powder (99.9% purity) to form a sprayed film. Next, cut the plate along its thickness direction through a cutting line near the center of the upper surface to expose a longitudinal section. The thickness of the sprayed film was measured using a scanning electron microscope (SEM) at 500x magnification, and the result was 50 mm. μ Approximately m.

[0109] (Experimental Example 3: Formation of Amorphous Layers) Prepare two dense alumina plates, each 10 mm in diameter and 1 mm thick, with a purity of 99.9% or higher. Next, use a grinding device to grind the two dense alumina plates until the surface roughness Ra is 0.7. μ The grinding process was carried out using a method less than m. Next, each ground surface was irradiated with an Ar beam (FAB) under high vacuum. Then, the two plates were overlapped with their respective ground surfaces facing each other, and bonding was performed while applying pressure to obtain a bond. The plate was then cut along its thickness direction through a cutting line near the center of the upper surface of the bond, exposing a longitudinal section. The section was observed using a transmission electron microscope (TEM) at 4 millionx magnification to determine the thickness of the amorphous layer, which was found to be approximately 5 nm.

[0110] (Tension test) On the upper surfaces of the plates with AD film, the plates with spray-coated film, and the pair of plates bonded by amorphous layers, prepared in Experimental Examples 1, 2, and 3, anti-slip nails were fixed with adhesive. φ The anti-slip pin (2.7 mm in diameter and 15 mm in length) was then stretched in a direction perpendicular to the upper surface of the board (vertically upward) using a tensile testing apparatus (manufactured by Shimadzu Corporation) to peel it off from the board. As a result, in both Experimental Example 1 and Experimental Example 2, the anti-slip pin detached at a tensile stress of approximately 60 MPa. After the tensile test, the fracture location was visually inspected. It was found that in both Experimental Example 1 and Experimental Example 2, the fracture did not occur at the interface between the anti-slip pin and the adhesive, but rather was observed within the film.

[0111] On the other hand, in the plate of Experimental Example 3, the anti-slip studs detached under tensile stress of approximately 70 MPa. After the tensile test, the fracture location was visually confirmed, and it was found to have broken at the interface between the anti-slip stud and the adhesive. Even when a tensile stress higher than that of the AD film and the sprayed film was applied, no fracture occurred in the amorphous layer, thus confirming that the bonding strength through the amorphous layer was higher than that of the AD film and the sprayed film.

[0112] Explanation of reference numerals in the attached figures 10A: Components for semiconductor manufacturing equipment 10B: Components for semiconductor manufacturing equipment 20: Ceramic substrate 20a: Central Department 20b: Peripheral part 21: Upper surface 22: Upper surface 22a: protrusion 23: Lower surface 24: Flat surface 26a: Electrode 26b: Electrode 27: Upper surface 30: Base plate 31: Upper surface 32: Refrigerant Flow Path 35: Insulating film 40: Bonding layer 50: Stomata 55: Plug 60: Grinding device 62: Grinding platform 64: Grinding pad 66: Carrier 67: Axis 68: pipe 69: Axis 70: Ceramic slab 71: Upper surface 71a: Top surface 71b: Reference plane 71c: Top surface 72: Protrusion 73: Lower surface 75: Sealing tape 78: Focusing ring 80: Amorphous layer 92: Protrusion 92a: Top surface 92b: Lower end face 95: Sealing tape 95a: Top surface 95b: Lower end face 100: Components for a first semiconductor manufacturing apparatus 120: First ceramic substrate 192: Components for forming protrusions 192a: Lower end face 195: Components for forming sealing strips 195a: Lower end face 220: Second ceramic substrate.

Claims

1. A manufacturing method, characterized in that, The manufacturing method is a method of manufacturing a second semiconductor manufacturing apparatus component using a first semiconductor manufacturing apparatus component. The first semiconductor manufacturing apparatus component includes a first ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having built-in electrodes. The second semiconductor manufacturing apparatus component includes a second ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having built-in electrodes. The manufacturing method includes: Step A: The upper surface of the first ceramic substrate is processed to form a flat surface with the plurality of protrusions removed; Step B1 involves bonding the flat surface of the first ceramic substrate to the lower surface of the ceramic plate at room temperature to form a second ceramic substrate formed by bonding the first ceramic substrate and the ceramic plate; and Step C, before or after step B1, involves forming multiple protrusions on the upper surface of the ceramic plate that can support the wafer.

2. The manufacturing method according to claim 1, wherein, The ceramic plate contains the same material as the ceramic that constitutes the first ceramic substrate.

3. The manufacturing method according to claim 2, wherein, Both the ceramic plate and the first ceramic substrate contain one or both selected from alumina and aluminum nitride.

4. The manufacturing method according to claim 1, wherein, The lower surface of the ceramic plate is bonded to the flat surface of the first ceramic substrate via an amorphous layer.

5. The manufacturing method according to claim 1, wherein, The arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.

6. A manufacturing method, characterized in that, The manufacturing method is a method of manufacturing a second semiconductor manufacturing apparatus component using a first semiconductor manufacturing apparatus component. The first semiconductor manufacturing apparatus component includes a first ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having built-in electrodes. The second semiconductor manufacturing apparatus component includes a second ceramic substrate having an upper surface with a plurality of protrusions capable of supporting a wafer and having built-in electrodes. The manufacturing method includes: Step A involves processing the upper surface of the first ceramic substrate to form a flat surface with the plurality of protrusions removed; and In step B2, the flat surface of the first ceramic substrate is bonded to the lower end surface of a plurality of protrusion forming components at room temperature to form a second ceramic substrate formed by bonding the first ceramic substrate and the plurality of protrusion forming components.

7. The manufacturing method according to claim 6, wherein, The plurality of protrusion-forming components contain the same material as the ceramic constituting the first ceramic substrate.

8. The manufacturing method according to claim 6, wherein, The plurality of protrusion-forming components and the first ceramic substrate each contain one or both selected from alumina and aluminum nitride.

9. The manufacturing method according to claim 6, wherein, The lower end face of the plurality of protrusion forming components is bonded to the flat surface of the first ceramic substrate via an amorphous layer.

10. The manufacturing method according to claim 6, wherein, The arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.

11. A component for a semiconductor manufacturing apparatus, characterized in that, The component for the semiconductor manufacturing apparatus includes: A ceramic substrate with built-in electrodes; and A ceramic plate having: a lower surface bonded to the upper surface of the ceramic substrate via an amorphous layer; and an upper surface having a plurality of protrusions capable of supporting a wafer.

12. A component for a semiconductor manufacturing apparatus, characterized in that, The component for the semiconductor manufacturing apparatus includes: A ceramic substrate with built-in electrodes; as well as Multiple protrusions have: a lower end face bonded to the upper surface of the ceramic substrate via an amorphous layer; and an upper end face for mounting a wafer.

13. The component for a semiconductor manufacturing apparatus according to claim 11, wherein, The ceramic plate contains the same material as the ceramic that constitutes the ceramic substrate.

14. The component for a semiconductor manufacturing apparatus according to claim 12, wherein, The plurality of protrusions contain the same material as the ceramic constituting the ceramic substrate.

15. The component for a semiconductor manufacturing apparatus according to claim 11, wherein, Both the ceramic plate and the ceramic substrate contain one or both selected from alumina and aluminum nitride.

16. The component for a semiconductor manufacturing apparatus according to claim 12, wherein, The plurality of protrusions and the ceramic substrate each contain one or both selected from alumina and aluminum nitride.

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