Stacked body for semiconductor device formation and method for manufacturing semiconductor device

Abstract

The semiconductor device formation stacked body (L1) has: a support (1); a preliminary rewiring layer (3) provided on one side of the support (1); and a seed layer (5) provided on one side of the preliminary rewiring layer (3).

Description

Technical Field

[0001] The present invention relates to a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] In recent years, with the miniaturization of electronic devices, the demand for miniaturization / hyperintegration of semiconductor packages mounted on electronic devices has become stronger. As the current packaging technology, FCBGA (Flip Chip-Ball Grid Array) with solder bumps on the semiconductor chip and connected to the circuit board is mainstream. However, as an alternative to this technology, FOWLP (Fan-Out Wafer Level Packaging) is being researched, which does not use a circuit board but directly sets solder balls on the semiconductor chip via a re-distribution layer (RDL) (for example, see Patent Document 1).

[0003] FOWLP mainly includes the Die-First method and the RDL-First method. The Die-First method involves placing a semiconductor chip on a support via a release layer, sealing the semiconductor chip, and then peeling the support from the semiconductor chip to form a rewiring layer. The RDL-First method involves forming a rewiring layer on a support via a release layer, further forming a semiconductor chip, sealing it, and then peeling the support from the rewiring layer (for example, see Patent Document 2).

[0004] Previous technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. WO2020 / 105485

[0007] Patent Document 2: Japanese Patent Application Publication No. 2015-35551 Summary of the Invention

[0008] The technical problem to be solved by the invention

[0009] In the Die-First method, the semiconductor chip is sealed before the rewiring layer is formed. Therefore, if there are defects in the rewiring layer, even qualified semiconductor chips must be discarded. In the RDL-First method, the rewiring layer is formed before sealing the semiconductor chip, thus solving this problem. On the other hand, it requires that the already formed rewiring layer not be damaged, and that the support can be easily peeled off from the rewiring layer.

[0010] The present invention was made to solve the above-mentioned problems, and its object is to provide a semiconductor device forming laminate and a method for manufacturing a semiconductor device that can easily peel off the support from the redistribution layer.

[0011] means for solving technical problems

[0012] The gist of this invention is as follows.

[0013] [1] A semiconductor device forming laminate comprising: a support; a pre-rewiring layer disposed on one side of the support; and a seed layer disposed on one side of the pre-rewiring layer.

[0014] In this semiconductor device forming laminate, a pre-rewiring layer is provided on one side of the support, and a seed layer is provided on one side of the pre-rewiring layer. When manufacturing a semiconductor device using this laminate, after forming a plating layer in a predetermined pattern on the rewiring lines stacked on the pre-rewiring layer, and performing semiconductor chip mounting and sealing, the support can be easily peeled off from the rewiring layer. By easily peeling off the support from the rewiring layer, damage to the rewiring layer can be suppressed, and the reliability of the manufactured semiconductor device can be improved.

[0015] [2] A laminate for forming a semiconductor device as described in [1], wherein,

[0016] A metal layer is provided between the support and the pre-rewiring layer. In this case, for example, the support can be easily peeled off from the rewiring layer by irradiating the metal layer with incoherent light and heating the pre-rewiring layer through the metal layer.

[0017] [3] A laminate for forming a semiconductor device as described in [1], wherein,

[0018] The pre-rewiring layer is directly disposed on one side of the support. In this case, for example, the pre-rewiring layer can be irradiated with coherent light to divide it, thereby making it easy to peel the support from the rewiring layer.

[0019] [4] A method for manufacturing a semiconductor device includes: a preparation step of preparing a support; a pre-rewiring layer forming step of forming a pre-rewiring layer on one side of the support; a seed layer forming step of forming a seed layer on one side of the pre-rewiring layer; a plating layer forming step of forming a plating layer on the seed layer in the rewiring layer on the pre-rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; a sealing step of sealing the semiconductor chip; and a peeling step of peeling the support from the pre-rewiring layer.

[0020] In this semiconductor device manufacturing method, a pre-rewiring layer is formed on one side of a support, and a seed layer is formed on the other side of the pre-rewiring layer. As a result, after a plating layer is formed on the rewiring lines stacked on the pre-rewiring layer in a predetermined pattern, and after the semiconductor chip is mounted and sealed, the support can be easily peeled off from the rewiring layer. By enabling easy peeling of the support from the rewiring layer, damage to the rewiring layer can be suppressed, and the reliability of the manufactured semiconductor device can be improved.

[0021] [5] The method for manufacturing a semiconductor device as described in [4], wherein,

[0022] Between the preparation step and the pre-rewiring layer formation step, there is a metal layer formation step that forms a metal layer on one side of the support. In the peeling step, the metal layer is irradiated with incoherent light to peel the support from the pre-rewiring layer. In this case, for example, by irradiating the metal layer with incoherent light and heating the pre-rewiring layer via the metal layer, the support can be easily peeled from the rewiring layer.

[0023] [6] The method for manufacturing a semiconductor device as described in [4], wherein,

[0024] In the pre-rewiring formation process, the pre-rewiring layer is formed directly on one side of the support. In the stripping process, coherent light is irradiated onto the pre-rewiring layer to peel the support from the pre-rewiring layer. In this case, by irradiating the pre-rewiring layer with coherent light, the pre-rewiring layer is divided, thereby making it easy to peel the support from the rewiring layer.

[0025] [7] A method for manufacturing a semiconductor device, comprising:

[0026] The process includes: a process for preparing a laminate for forming a semiconductor device as described in [1]; a plating layer forming process for forming a plating layer on the seed layer in the rewiring layer on the pre-rewiring layer; a mounting process for mounting a semiconductor chip on the plating layer; a sealing process for sealing the semiconductor chip; and a peeling process for peeling the support from the pre-rewiring layer.

[0027] In this semiconductor device manufacturing method, a semiconductor device forming laminate is used, in which a pre-rewiring layer is formed on one side of a support, and a seed layer is formed on one side of the pre-rewiring layer. Therefore, after a plating layer is formed on the rewiring lines stacked on the pre-rewiring layer in a predetermined pattern, and after the semiconductor chip is mounted and sealed, the support can be easily peeled off from the rewiring layer. By enabling easy peeling of the support from the rewiring layer, damage to the rewiring layer can be suppressed, and the reliability of the manufactured semiconductor device can be improved.

[0028] [8] A method for manufacturing a semiconductor device as described in [7], wherein,

[0029] In a semiconductor device lamination prepared to have a metal layer disposed between the support and the pre-rewiring layer, in the stripping process, incoherent light is irradiated onto the metal layer to peel the support from the pre-rewiring layer. In this case, by irradiating the metal layer with incoherent light and heating the pre-rewiring layer via the metal layer, the support can be easily peeled from the rewiring layer.

[0030] [9] The method for manufacturing a semiconductor device as described in [7], wherein,

[0031] In a semiconductor device forming laminate in which the pre-rewiring layer is directly disposed on one side of the support, coherent light is irradiated onto the pre-rewiring layer during the stripping process to peel the support from the pre-rewiring layer. In this case, irradiating the pre-rewiring layer with coherent light and dividing the pre-rewiring layer by irradiating with coherent light allows for easy peeling of the support from the rewiring layer.

[0032] Invention Effects

[0033] According to the present invention, the support can be easily peeled off from the redistribution layer. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0035] Figure 2 (a) is a schematic cross-sectional view showing the preparation process. Figure 2 (b) is a schematic cross-sectional view showing the metal layer formation process.

[0036] Figure 3 (a) is a schematic cross-sectional view showing the process of forming the pre-rewiring layer. Figure 3 (b) is a schematic cross-sectional view showing the semiconductor device stack obtained after the seed layer formation process.

[0037] Figure 4 (a) ~ Figure 4 (c) is a schematic cross-sectional view showing the plating layer formation process.

[0038] Figure 5 (a) is a schematic cross-sectional view showing the seed layer removal process performed after the plating layer formation process. Figure 5 (b) is a schematic cross-sectional view showing the process of forming the next rewiring layer.

[0039] Figure 6 It is a schematic cross-sectional view of the structure after the repeated implementation of the seed layer formation process, the plating layer formation process, and the formation of the next rewiring layer.

[0040] Figure 7 (a) is a schematic sectional view showing the installation process. Figure 7 (b) is a schematic cross-sectional view showing the sealing process.

[0041] Figure 8 (a) and Figure 8 (b) is a schematic cross-sectional view showing the stripping process.

[0042] Figure 9 (a) is a schematic sectional view showing the processing steps. Figure 9 (b) is a schematic cross-sectional view showing the ball-planting process.

[0043] Figure 10 (a) is a schematic cross-sectional view showing a modified example of a semiconductor device stack obtained after the seed layer formation process. Figure 10 (b) and Figure 10 (c) is a schematic cross-sectional view showing the stripping process in this case. Detailed Implementation

[0044] Hereinafter, with reference to the accompanying drawings, a preferred embodiment of a semiconductor device forming laminate and a method for manufacturing a semiconductor device according to one aspect of the present invention will be described in detail.

[0045] In the following description, the numerical range represented by "~" indicates the range encompassed by the values ​​recorded before and after "~" as the minimum and maximum values, respectively. Furthermore, within a range of numerical values ​​recorded in stages, the upper or lower limit value recorded in one range can be replaced by the upper or lower limit value of other ranges of numerical values ​​recorded in stages. The upper or lower limit value of the numerical range can be replaced by the values ​​shown in the embodiments.

[0046] [First Implementation]

[0047] Figure 1This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Figure 1 The semiconductor device manufacturing method shown belongs to the FOWLP (Fan-Out Wafer Level Packaging) method, which involves placing solder balls directly on the semiconductor chip via a re-distribution layer (RDL) without using a circuit board. Here, the RDL-First method is used in FOWLP, where the re-distribution layer is formed before sealing the semiconductor chip.

[0048] like Figure 1 As shown, the semiconductor device manufacturing method of the first embodiment is configured with the following steps: preparation step S01, metal layer formation step S02, pre-rewiring layer formation step S03, seed layer formation step S04, plating layer formation step S05, mounting step S06, sealing step S07, stripping step S08, processing step S09, and ball-mounting step S10.

[0049] like Figure 2 As shown in (a), preparation step S01 is the step of preparing the support 1. There are no particular limitations on the support 1, but for example, a glass substrate, resin substrate, silicon wafer, metal thin film, etc., can be used. Figure 2 In example (a), the support 1 is made of a glass substrate. The thickness of the support 1 is, for example, about 0.1 mm to 2.0 mm. By setting the thickness of the support 1 to 0.1 mm or more, the operability of the support 1 can be sufficiently ensured. By setting the thickness of the support 1 to 2.0 mm or less, the material cost of the support 1 can be reduced.

[0050] like Figure 2 As shown in (b), the metal layer forming process S02 is a process of forming a metal layer 2 on one side of the support 1. The metal layer 2 is the layer used to peel off the support 1 from the redistribution layer 4 in the peeling process S09, which is a subsequent process. The metal layer 2 is formed, for example, by sputtering or lamination of metal foil. As for the forming material of the metal layer 2, there are no particular limitations as long as it is a conductive material that generates heat by absorbing light. Examples include metals such as chromium, copper, titanium, silver, platinum, gold, and tungsten; alloys such as nickel-chromium, titanium-tungsten, copper-zinc, and stainless steel; and metal oxides such as indium tin oxide (ITO), zinc oxide, and niobium oxide. They can be used individually or in combination of two or more. When two or more metals are combined, a structure in which the metals are stacked can be used.

[0051] From the viewpoint of improving peelability, the thickness of metal layer 2 can be, for example, 1 nm to 5000 nm, or 50 nm to 3000 nm. When two metals are stacked together, the thickness of the first metal layer formed on the support 1 can be 1 nm to 1000 nm, 5 nm to 500 nm, or 10 nm to 100 nm. By setting the thickness of the first metal layer to 1 nm or more, defects in the metal layer can be suppressed; by setting it to 1000 nm or less, a decrease in peelability can be suppressed. The thickness of the second metal layer formed on the first metal layer can be 1 nm to 5000 nm, 10 nm to 500 nm, or 50 nm to 200 nm. By setting the thickness of the second metal layer to 1 nm or more, defects in the metal layer can be suppressed; by setting it to 5000 nm or less, a decrease in peelability can be suppressed.

[0052] like Figure 3 As shown in (a), the pre-rewiring layer forming step S03 is a step in which a pre-rewiring layer 3 is formed on one side of the support 1. The pre-rewiring layer 3 is the layer used to peel off the support 1 from the rewiring layer 4 in the peeling step S08, which is a subsequent step. Here, the pre-rewiring layer 3 is formed on the metal layer 2 on one side of the support 1. The pre-rewiring layer 3 is formed, for example, by coating and curing a rewiring material on the metal layer 2. Examples of rewiring materials include, for example, photosensitive resin materials with electrical insulation properties. Examples of resin materials include, for example, polyimide, polybenzoxazole, phenolic varnish, polyhydroxystyrene, etc. The thickness of the pre-rewiring layer 3 is, for example, about 5 μm to 20 μm. By setting the thickness of the pre-rewiring layer 3 to 5 μm or more, it is possible to suppress the generation of defects in the pre-rewiring layer 3. By setting the thickness of the pre-rewiring layer 3 to less than 20 μm, deviations in the thickness of the pre-rewiring layer 3 can be suppressed.

[0053] like Figure 3 As shown in (b), the seed layer formation process S04 is a process of forming a seed layer 5 on one side of the pre-rewiring layer 3. The seed layer 5 is a layer used to supply power to the growth of the plating layer 7 formed in the subsequent plating layer formation process S05. Figure 3 In example (b), the seed layer 5 is formed flatly on one side of the prepared rewiring layer 3. The seed layer 5 is formed, for example, by sputtering. Examples of materials used to form the seed layer 5 include titanium, copper, tungsten, nickel, and silver. The thickness of the seed layer 5 is, for example, about 1 nm to 100 nm. By setting the thickness of the seed layer 5 to 1 nm or more, defects in the seed layer can be suppressed. By setting the thickness of the seed layer 5 to 100 nm or less, the sputtering processing time can be shortened, and deviations in the thickness of the seed layer 5 can be suppressed.

[0054] By forming the seed layer 5, a semiconductor device forming laminate L1 can be obtained. That is, a semiconductor device forming laminate L1 comprising a support 1, a pre-rewiring layer 3 disposed on one side of the support 1, and a seed layer 5 disposed on one side of the pre-rewiring layer 3 can be obtained. Figure 3 In example (b), a metal layer 2 is provided between the support 1 and the pre-rewiring layer 3 in the semiconductor device forming laminate L1. In the semiconductor device manufacturing method of this embodiment, the semiconductor device forming laminate L1 can be prepared in advance and subsequent processes can be performed.

[0055] The plating layer formation process S05 is the process of forming the plating layer 7 on the seed layer 5. In the plating layer formation process S05, firstly, as... Figure 4 As shown in (a), resist 6 is formed on seed layer 5 in a prescribed pattern. Then, as... Figure 4 As shown in (b), a plating layer 7 is formed on the seed layer 5 exposed from the resist 6. The plating layer 7 is formed, for example, by electroplating. Copper can be used as a material for forming the plating layer 7. After forming the plating layer 7, as... Figure 4 As shown in (c), remove the resist 6.

[0056] After removing resist 6, as Figure 5 As shown in (a), the seed layer 5 remaining on the redistribution layer 4 is removed. The removal of the seed layer 5 is performed, for example, by etching. After removing the seed layer 5, as... Figure 5 As shown in (b), the next rewiring layer 4 is formed. The next rewiring layer 4 is formed, for example, by coating and curing a rewiring material onto the pre-rewiring layer 3. Here, the rewiring layer 4 is patterned so that the plating layer 7 formed in the plating layer formation step S05 is exposed from the rewiring layer 4. In this embodiment, the rewiring layer 4 and the pre-rewiring layer 3 are made of the same rewiring material, but they may also be made of different rewiring materials. The rewiring material is appropriately selected from the viewpoint of pattern formation and reliability. The thickness of the rewiring layer 4 may be the same as or different from the thickness of the pre-rewiring layer 3. The thickness of the rewiring layer 4 is appropriately selected from the viewpoint of workability and reliability.

[0057] Subsequently, the seed layer formation process S04, the plating layer formation process S05, and the formation of the next rewiring layer 4 are repeated, as follows: Figure 6 As shown, plating layers 7 with a specified pattern are formed in the redistribution layers 4 of the desired number of layers. The plating layers 7 are electrically connected to each other in the stacking direction of the redistribution layers 4, forming a connection to the semiconductor chip W (reference). Figure 7 (a) Wiring section with externally removed electrodes (not shown).

[0058] like Figure 7 As shown in (a), mounting step S06 is the step of mounting the semiconductor chip W onto the plating layer 7. The semiconductor chip W is formed by cutting a semiconductor wafer to a specified size and monolithically assembling it into a chip shape. From the viewpoints of miniaturization / thinning of semiconductor devices and crack suppression during handling / processing, the thickness of the semiconductor chip W can be 1μm to 1000μm, 10μm to 500μm, or 20μm to 200μm. Solder bumps 8 are provided on the semiconductor chip W. Figure 7 As shown in (a), by attaching solder bumps 8 to the outermost plating layer 7 exposed from the outermost rewiring layer 4, it is possible to mount the semiconductor chip W onto the plating layer 7.

[0059] like Figure 7 As shown in (b), sealing process S07 is a process for sealing the semiconductor chip W. In sealing process S07, for example, a sealing layer 9 is formed on the outermost rewiring layer 4 to cover the semiconductor chip W and solder bumps 8. There are no particular restrictions on the materials used to make the sealing layer 9, but from the viewpoint of heat resistance and reliability, thermosetting resin compositions can be used. The composition of the sealing layer 9 may include fillers, flame retardants, and other additives.

[0060] Stripping process S08 is the process of stripping the support 1 from the rewiring layer 4. In this embodiment, a metal layer 2 disposed between the support 1 and the pre-rewiring layer 3 is used, such as... Figure 8 As shown in (a), incoherent light P1 is irradiated onto the metal layer 2 to peel the support 1 from the rewiring layer 4. A xenon lamp can be used as a light source for outputting the incoherent light P1. Figure 8 In example (a), incoherent light P1 from a light source is irradiated from the support 1 side toward the metal layer 2. The metal layer 2 is heated by irradiating it with incoherent light P1, and the rewiring layer 3 prepared via the metal layer 2 is also heated.

[0061] Heating the pre-rewiring layer 3 causes the resin components constituting the pre-rewiring layer to cure, such as... Figure 8 As shown in (b), the support 1 and the metal layer 2 can be easily peeled off from the pre-rewiring layer 3 by peeling off the metal layer 2. The irradiation conditions of the incoherent light P1 can be arbitrarily set. It can be set to a condition that the support 1 and the metal layer 2 can be peeled off from the pre-rewiring layer 3 with one irradiation, or it can be set to a condition that the support 1 and the metal layer 2 can be peeled off from the pre-rewiring layer 3 with two or more irradiations. From the viewpoint of further reducing damage to the rewiring layer 4, the plating layer 7, and the semiconductor chip W, it is preferable to set the irradiation conditions of the incoherent light P1 to a condition that the support 1 and the metal layer 2 can be peeled off from the pre-rewiring layer 3 with one irradiation.

[0062] like Figure 9 As shown in (a), processing step S09 is a process of processing the pre-rewiring layer 3 in a manner that exposes the plating layer 7. In processing step S09, for example, by irradiation with a laser, the pre-rewiring layer 3 on the side opposite to the semiconductor chip W is processed with an opening in a predetermined pattern, so that the plating layer 7 (seed layer 5) in the pre-rewiring layer 3 is exposed.

[0063] like Figure 9 As shown in (b), the ball-mounting process S10 is the process of mounting solder balls 10 onto the plating layer 7. In the ball-mounting process S10, solder balls 10 are bonded to each plating layer 7 (seed layer 5) that has been exposed from the pre-rewiring layer 3 on the opposite side of the semiconductor chip W by the processing process S09, in a manner that protrudes from the pre-rewiring layer 3. Through the above processes, a semiconductor device D1 with a structure in which solder balls 10 are directly mounted on the semiconductor chip W via the pre-rewiring layer 3 and the rewiring layer 4 can be obtained.

[0064] As explained above, in the semiconductor device forming laminate L1 and the semiconductor device manufacturing method, a pre-rewiring layer 3 is formed on one side of the support 1, and a seed layer 5 is formed on one side of the pre-rewiring layer 3. Therefore, after a plating layer 7 is formed in a predetermined pattern on the rewiring layer 4 stacked on the pre-rewiring layer 3, and after the semiconductor chip W is mounted and sealed, the support 1 can be easily peeled off from the rewiring layer 4 in the pre-rewiring layer 3 portion. By being able to easily peel the support 1 off from the rewiring layer 4, damage to the rewiring layer 4 can be suppressed, and the reliability of the manufactured semiconductor device D1 can be improved.

[0065] In this embodiment, a metal layer 2 is provided between the support 1 and the pre-rewiring layer 3. Therefore, by irradiating the metal layer 2 with incoherent light P1, the pre-rewiring layer 3 is heated via the metal layer 2, allowing the support 1 to be easily peeled off from the rewiring layer 4. Because the support 1 can be easily peeled off from the rewiring layer 4, stress applied to the rewiring layer 4 during peeling can be suppressed, and peeling of the rewiring layers 4 to each other can be prevented.

[0066] [Variation Example]

[0067] In the above embodiment, a metal layer 2 is provided between the support 1 and the pre-rewiring layer 3, but the formation of the metal layer 2 can be omitted. In this case, such as Figure 10 As shown in (a), in the semiconductor device forming laminate L1 obtained by forming the seed layer 5, a pre-rewiring layer 3 is directly formed on one side of the support 1. With this structure, in the stripping process S08, as... Figure 10As shown in (b), coherent light P2 is irradiated onto the pre-rewiring layer 3. For example, a light source that outputs ultraviolet laser light can be used as the source for outputting coherent light P2. The coherent light P2 is scanned along the in-plane direction of the pre-rewiring layer 3, as shown... Figure 10 As shown in (c), the support 1 can be easily peeled off from the redistribution layer 4 by dividing the pre-redistribution layer 3.

[0068] Symbol Explanation

[0069] 1-Support, 2-Metal layer, 3-Prepared redistribution layer, 4-Redistribution layer, 5-Seed layer, 7-Patent layer, L1, L2-Laminated structure for semiconductor device formation, W-Semiconductor chip, P1-Incoherent light, P2-Coherent light.

Claims

1. A laminate for forming a semiconductor device, comprising: Support structure; A rewiring layer is prepared and disposed on one side of the support; and A seed layer is disposed on one side of the prepared rewiring layer.

2. The laminate for forming a semiconductor device according to claim 1, wherein, A metal layer is provided between the support and the pre-rewiring layer.

3. The laminate for forming a semiconductor device according to claim 1, wherein, The pre-rewiring layer is directly disposed on one side of the support.

4. A method for manufacturing a semiconductor device, comprising: Preparation process, preparation of the support structure; The process of forming a pre-rewiring layer involves forming a pre-rewiring layer on one side of the support. In the seed layer formation process, a seed layer is formed on one side of the prepared rewiring layer; The plating layer forming process involves forming a plating layer on the seed layer within the rewiring layer on the prepared rewiring layer. The mounting process involves mounting the semiconductor chip onto the plating layer; The semiconductor chip is sealed using a sealing process. The stripping process involves stripping the support from the prepared rewiring layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein, Between the preparation step and the pre-rewiring layer formation step, there is a metal layer formation step that forms a metal layer on one side of the support. In the stripping process, the metal layer is irradiated with incoherent light to peel the support from the pre-rewiring layer.

6. The method for manufacturing a semiconductor device according to claim 4, wherein, In the process of forming the pre-rewiring layer, the pre-rewiring layer is formed directly on one side of the support. In the stripping process, coherent light is irradiated onto the pre-rewiring layer to peel the support from the pre-rewiring layer.

7. A method for manufacturing a semiconductor device, comprising: The process of preparing a laminate for forming a semiconductor device as described in claim 1; The plating layer forming process involves forming a plating layer on the seed layer within the rewiring layer on the prepared rewiring layer. The mounting process involves mounting the semiconductor chip onto the plating layer; The semiconductor chip is sealed using a sealing process. The stripping process involves stripping the support from the prepared rewiring layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein, A laminate for forming a semiconductor device, wherein a metal layer is disposed between the support and the pre-rewiring layer. In the stripping process, the metal layer is irradiated with incoherent light to peel the support from the pre-rewiring layer.

9. The method for manufacturing a semiconductor device according to claim 7, wherein, Prepare a semiconductor device forming laminate in which the pre-rewiring layer is directly disposed on one side of the support. In the stripping process, coherent light is irradiated onto the pre-rewiring layer to peel the support from the pre-rewiring layer.

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