Circuit board and semiconductor package comprising the same

Abstract

Disclosed in an embodiment of the present invention is a circuit board, comprising: a package substrate including a first core layer; a circuit substrate including a second core layer and arranged on the package substrate; and a semiconductor device mounted on the circuit substrate, wherein a thickness of the package substrate is greater than a thickness of the circuit substrate, and a thickness of the first core layer is greater than a thickness of the second core layer.

Description

Technical Field

[0001] According to embodiments of the present invention, there is a circuit board and a semiconductor package. Background Technology

[0002] As the performance of electrical / electronic products continues to improve, techniques for attaching a greater number of semiconductor chips to substrates of limited size have been proposed and researched. However, since typical packaging is based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or packaging substrate has the form in which a processor package containing a processor chip and a memory package containing a memory chip attached thereto are connected to form a single unit. The advantage of this type of packaging substrate is that by manufacturing the processor chip and memory chip as a single integrated package, the chip mounting area can be reduced, and high-speed signal transmission can be achieved through a shortened path. Due to these advantages, the aforementioned packaging substrate is widely used in mobile devices and the like.

[0004] Meanwhile, in recent years, as electronic devices such as mobile devices, servers, and personal computers (PCs) have become increasingly complex and high-bandwidth memory (HBM) has been adopted, package sizes have increased with the increase in semiconductor chip area or with multiple semiconductor chips mounted on a single package substrate in order to shorten the electrical connection distance between semiconductor chips. Furthermore, as the functions required by application processors increase, it is necessary to form a separate processor chip for each function and provide circuit boards on which these processor chips can be mounted.

[0005] In this scenario, even when the application processor is divided into two processor chips for each function, the number of (input / output) terminals provided in each processor chip increases.

[0006] Furthermore, due to advancements in 5G, the Internet of Things (IoT), higher display resolutions, and increased communication speeds, the number of power lines and signal lines has increased, leading to a tendency for processor chips to have more terminals. Consequently, the area and thickness of circuit boards, as well as the density of circuit patterns, are also increasing. Moreover, increased circuit board area and thickness can lead to issues such as difficulties in miniaturizing products, reliability problems related to circuit board warping, and increased product costs.

[0007] Furthermore, in recent years, there has been a trend to prevent problems such as circuit board warping by increasing the thickness of the core layer of the circuit board. However, when using a thick core layer, ensuring yield and improving productivity can become difficult during the process of forming via electrodes in the core layer and achieving fine spacing between via electrodes. Additionally, to gain processing advantages and reduce manufacturing difficulty, devices such as bridges are mounted in the build-up layer rather than in the core layer. Moreover, in the case of the interposer layer, embedding devices such as bridges in the core layer rather than in the build-up layer allows for the regular formation of signal paths, including circuit routing and circuit structure, thereby preventing signal integrity degradation. However, the problem is that the accuracy of embedded devices such as bridges in the core layer is significantly reduced.

[0008] In particular, when a circuit board with a bridge installed therein is mounted on a package to form a semiconductor package, there is a problem that warping may occur due to thickness differences, for example, caused by thinning. Summary of the Invention

[0009] Technical issues

[0010] An embodiment of the present invention provides a circuit board and a semiconductor package including the circuit board, wherein reliability is improved by adjusting the thickness of the core layer of the circuit board, which serves as an interposer, and the core layer of the package substrate, which have different thicknesses, thereby suppressing warping caused by differences in the coefficients of thermal expansion.

[0011] Alternatively, an embodiment may provide a circuit board and a semiconductor package including the circuit board, wherein reliability is improved by adjusting the height between the upper surface of the connecting member mounted in the circuit board and the upper surface of the core layer and mounting the connecting member in a cavity of the core layer, thereby allowing the connecting member to be easily mounted regardless of its size and without the need for vias through the interfaces between the multiple insulating layers formed for mounting the connecting member.

[0012] Alternatively, the implementation may provide a circuit board and a semiconductor package including the circuit board, wherein connecting members are disposed in the core layer to allow the stacked electrode portion in the upper stacked layer to be easily formed into a fine pattern or electrode pattern, thereby reducing the alignment error between the stacked electrode portion and the electrodes of the device disposed on the circuit board and improving electrical reliability.

[0013] The objectives to be solved by the implementation methods are not limited to the objectives described above, and may include objectives and effectiveness that can be identified by the solutions to the objectives and the implementation methods described below.

[0014] Technical solutions

[0015] A circuit board according to an embodiment of the present invention includes: a packaging substrate including a first core layer; a circuit board including a second core layer and disposed on the packaging substrate; and a semiconductor device mounted on the circuit board, wherein the thickness of the packaging substrate is greater than the thickness of the circuit board, and the thickness of the first core layer is greater than the thickness of the second core layer.

[0016] The circuit board may include an upper layer disposed on the second core layer, a lower layer disposed below the second core layer, and connecting members disposed in cavities in the circuit board.

[0017] The cavity can pass through at least one of the upper lamination, the core layer, and the lower lamination.

[0018] The connecting member can overlap with the second core layer in the horizontal direction.

[0019] The first core layer may include a first through-hole, and the second core layer may include a second through-hole.

[0020] The width of the first through hole can be the same on its upper surface, lower surface and center portion, and the width of the second through hole can decrease towards the center portion of the second through hole.

[0021] The outer surface of the connecting member may face the first surface of the cavity in the second core layer.

[0022] The central portion of the first surface may protrude toward the outer surface of the connecting member in the stacking direction.

[0023] The gap between the first surface and the connecting member can be minimized at the center.

[0024] The packaging substrate may include a first core electrode portion, which includes a first core via electrode passing through a first core layer and a first core wiring portion disposed on the first core layer, and the circuit board may include a second core electrode portion, which includes a second core via electrode passing through a second core layer and a second core wiring portion disposed on the second core layer.

[0025] The width of the first via electrode can be the same in the stacking direction, and the width of the second via electrode can increase from its center portion toward the upper or lower surface in the stacking direction.

[0026] The upper surface of the second core wiring portion can be coplanar with the upper surface of the upper wiring portion provided on the upper surface of the connecting member.

[0027] Beneficial effects

[0028] According to an embodiment of the present invention, a circuit board and a semiconductor package including the circuit board can be realized, wherein reliability is improved by adjusting the thickness of the core layer of the circuit board serving as an interposer and the core layer of the package substrate, which have different thicknesses, so as to suppress warping caused by differences in the coefficient of thermal expansion.

[0029] Furthermore, according to an embodiment, a circuit board and a semiconductor package including the circuit board can be realized, wherein reliability is improved by adjusting the height between the upper surface of the connecting member mounted in the circuit board and the upper surface of the core layer and mounting the connecting member in a cavity of the core layer, so as to allow the connecting member to be easily installed regardless of its size and without needing to pass through vias between the interfaces between the multiple insulating layers formed for mounting the connecting member.

[0030] Furthermore, according to the embodiments, a circuit board and a semiconductor package including the circuit board can be realized, wherein the connecting members are disposed in the core layer to allow the stacked electrode portion in the upper stacked layer to be easily formed into a fine pattern or electrode pattern, thereby reducing the alignment error between the stacked electrode portion and the electrodes of the device disposed on the circuit board and improving electrical reliability.

[0031] The various advantages and effects of the present invention are not limited to those described above, and can be more easily understood through the description of specific embodiments of the present invention. Attached Figure Description

[0032] Figure 1 This is a plan view of the package according to an embodiment of the present invention.

[0033] Figure 2 This is a perspective view of the packaging according to an embodiment of the present invention.

[0034] Figure 3 It is along Figure 1 The view captured by I-I' in the image.

[0035] Figure 4 This is a cross-sectional view of the package according to the first embodiment of the present invention.

[0036] Figure 5 yes Figure 4 A magnified view of K1 in the image.

[0037] Figure 6 yes Figure 4 A magnified view of K2 in the image.

[0038] Figure 7 It shows Figure 6 Example of modification.

[0039] Figure 8 yes Figure 4A magnified view of K3 in the image.

[0040] Figures 9 to 15 This is a view illustrating a method for manufacturing a circuit board and a package according to an embodiment of the present invention. Detailed Implementation

[0041] While the invention is readily adaptable to various modifications and alternatives, specific embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. However, this does not constitute a limitation of the invention.

[0042] It should be understood that these embodiments are not intended to limit the invention to the specific forms disclosed, but rather, the invention covers all modifications, equivalents and alternatives that fall within the spirit and scope of the invention.

[0043] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0044] However, the spirit of the present invention is not limited to the embodiments described, and can be implemented in various forms, and one or more elements in the embodiments can be selectively combined and replaced for use within the scope of the spirit of the present invention.

[0045] Furthermore, unless specifically defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having the meaning commonly understood by those skilled in the art, and commonly used terms, such as those defined in dictionaries, may be understood taking into account their contextual meaning in the relevant field.

[0046] Furthermore, the terminology used in the embodiments of the present invention is for descriptive purposes only and not for limiting purposes. In this specification, unless the context clearly indicates otherwise, the singular form includes its plural form, and where “at least one (or one or more) of A, B, and C” is described, this may include at least one of all combinations that can combine A, B, and C.

[0047] It should be understood that although the terms "second," "first," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the invention, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. These terms are used only to distinguish one component from another, and the corresponding components are not limited by these terms in their nature, order, sequence, etc.

[0048] Furthermore, when a component is described as “connected,” “coupled,” or “linked” to another component, the component may include not only cases where it is directly connected, coupled, or linked to another component, but also cases where it is connected, coupled, or linked through yet another component between the component and the other component.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood in this application that, when used in this specification, the terms “comprise,” “comprising,” “include,” and / or “including” specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0050] Furthermore, when a component is described as being formed "above" or "below" another component, the terms "above" or "below" include cases where the two components are in direct contact with each other and cases where one or more components are (indirectly) disposed between the two components. Additionally, when an element is described as being disposed "above" or "below" another element, such a description can include cases where the element is disposed on the upper or lower side relative to the other element.

[0051] Furthermore, the expression that component A is positioned between component B and component C should be understood to encompass a configuration in which component A is positioned to at least partially overlap with component B and component C in the horizontal and / or vertical directions.

[0052] The expression indicating direction can include horizontal and vertical directions, and the horizontal direction can include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. According to the Cartesian coordinate system, directions can be referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis). The expression "overlap in the horizontal direction" should be understood to encompass overlap in the first horizontal direction and / or overlap in the second horizontal direction.

[0053] Furthermore, the statement that component A is exposed from component B should be understood as meaning that component A is exposed from component B, rather than that component A is exposed from the entire product. In other words, when component A is described as being exposed from component B, component A can be understood as being at least partially covered by component C.

[0054] Furthermore, when component A is described as "in contact" with component B, this contact can include not only the case where component A is in direct contact with component B, but also the case where component A is in contact with component B through another component located between component A and component B. Therefore, component A is described as "in direct contact" with component B when it is intended to be understood as only being in direct contact with component B.

[0055] Furthermore, when component A is described as being "covered" by component B, it should be understood that the extent to which component A is covered by component B is limited to the portion necessary to achieve the intended function and purpose. Unless there are special circumstances, this expression is not necessarily interpreted as meaning that component A is entirely covered by component B.

[0056] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It should also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0057] Before describing the embodiments, an electronic device with a circuit board and semiconductor package in which the embodiments are applied will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to a semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor devices, and the semiconductor devices may be mounted on the circuit board.

[0058] Semiconductor devices can include active and / or passive devices. Active devices can be semiconductor chips in the form of integrated circuits (ICs), where hundreds to millions or more devices are integrated into a single chip. Semiconductor chips can be logic chips, memory chips, etc. Logic chips can be non-memory chips, such as central processing units (CPUs), graphics processing units (GPUs), or field-programmable gate arrays (FPGAs). For example, a logic chip can be an application processor (AP) chip, which includes at least one of a CPU, GPU, digital signal processor, cryptographic processor, microprocessor, and microcontroller. Alternatively, a logic chip can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., or a chipset that includes a specific combination of those listed so far.

[0059] Memory chips can be stacked memories such as high-bandwidth memory (HBM). Furthermore, memory chips can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0060] Meanwhile, the semiconductor packaging products using this embodiment can be any of the following: Chip Scale Package (CSP), flip chip-chip scale package (FC-CSP), flip chip ball grid array (FC-BGA), Package On Package (PoP), and System In Package (SiP), but the present invention is not limited thereto.

[0061] Furthermore, electronic devices can be smartphones, personal digital assistants, digital cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video game consoles, smartwatches, automotive electronics, and so on. However, electronic devices are not limited to these, and can be any other electronic device that processes data.

[0062] Figure 1 This is a plan view of the package according to an embodiment of the present invention. Figure 2 This is a perspective view of the package according to an embodiment of the present invention, and Figure 3 It is along Figure 1 The view captured by I-I' in the image.

[0063] Reference Figures 1 to 3 In addition to semiconductor devices DI1 and DI2 and circuit board 100, the package (or semiconductor package) 1000 according to the embodiment may also include a package substrate 200. For example, the package substrate 200 may be an FPGA substrate. In particular, the circuit board 100 according to the embodiment may be a substrate in which connection members are embedded.

[0064] The circuit board 100 according to the embodiment may include a first semiconductor device DI1, a second semiconductor device DI2, and a connection member BR. Alternatively, the circuit board 100 may include the connection member BR. Furthermore, the first semiconductor device DI1 and the second semiconductor device DI2 may be mounted on the circuit board 100.

[0065] Furthermore, as described above, the first semiconductor device DI1 and the second semiconductor device DI2 may include logic chips or memory chips. Furthermore, as described above, the first semiconductor device DI1 and the second semiconductor device DI2 may be heterogeneous semiconductor devices. Additionally, the connection member BR may be embedded in the circuit board 100. Specifically, the connection member BR may be embedded in a cavity of the circuit board 100. Any circuit board described below can be used as circuit board 100.

[0066] Additionally, the connection member BR may include an upper wiring BE that contacts an upper electrode portion on the connection member located in the circuit board. Therefore, the upper wiring BE can be electrically connected to the upper electrode portion. Furthermore, the upper wiring BE can be electrically connected via the upper electrode portion to a first semiconductor device and a second semiconductor device disposed above it, and can be used as a bridge.

[0067] Furthermore, the circuit board may include a conductive member SB for connecting the first semiconductor device and the second semiconductor device to an electrode portion disposed in the upper portion of the circuit board 100, particularly an electrode portion in the upper stack of the circuit board 100. Additionally, the circuit board may include a conductive member SB disposed between the connecting member BR and the first and second semiconductor devices, rather than a conductive member SB disposed between the stack and the first and second semiconductor devices. Furthermore, the connecting member BR can electrically connect at least two semiconductor devices to each other. However, hereinafter, the connecting member BR will be described as electrically connecting two semiconductor devices to each other.

[0068] Furthermore, the underfill UF can be located between the circuit board 100 and the first semiconductor device DI1 and the second semiconductor device DI2. The underfill UF can cover the conductive component SB.

[0069] Furthermore, when the connecting member BR does not include a via electrode, the core via electrode located in the core layer of the circuit board 100 may not overlap with the connecting member BR in the vertical direction. However, when the connecting member BR includes a via electrode, the connecting member BR may overlap with the via electrode in the core layer of the circuit board 100 in the vertical direction and may be electrically connected to the via electrode.

[0070] Furthermore, the via electrodes of the stacked layer can overlap with the connecting member BR in the vertical direction. Additionally, the connecting member BR and the via electrodes of the stacked layer can be electrically connected to each other. Furthermore, the connecting member BR can at least partially overlap with the first semiconductor device DI1 and the second semiconductor device DI2 in the vertical direction.

[0071] Additionally, as mentioned above, the connection member BR can be an organic or inorganic connection member. For example, the connection member BR can be an inorganic connection member. When the connection member BR includes a via electrode, the connection member BR may be advantageous in transferring power from the circuit board 100 to the first semiconductor device DI1 and the second semiconductor device DI2.

[0072] Furthermore, the aforementioned packaging substrate 200 can be disposed below the circuit board 100. The packaging substrate 200 and the circuit board 100 can be electrically connected to each other via conductive components or the like.

[0073] For example, the packaging substrate 200 can be a flip-chip ball grid array (FC-BGA). Alternatively, the packaging substrate 200 can be a multilayer PCB.

[0074] The circuit board 100 can serve as an intermediary layer between the semiconductor device and the packaging substrate 200, and can transmit signals and power between them.

[0075] Figure 4 This is a cross-sectional view of the package according to the first embodiment of the present invention. Figure 5 yes Figure 4 A magnified view of K1 in the image. Figure 6 yes Figure 4 A magnified view of K2 in the image. Figure 7 It shows Figure 6 The modified example, and Figure 8 yes Figure 4 A magnified view of K3 in the image.

[0076] Reference Figure 4 According to the embodiment, the package 1000 may include a package substrate 200, a circuit board 100, and semiconductor devices DI1 and DI2. The package substrate 200, the circuit board 100, and the semiconductor devices DI1 and DI2 may be arranged sequentially in a stacking direction. Therefore, the circuit board 100 may be located between the semiconductor devices DI1 and DI2 and the package substrate 200.

[0077] The packaging substrate 200 may include a packaging insulating layer 210 and packaging electrode portions. The packaging insulating layer 210 may include a first core layer 211, an upper insulating layer 212, and a lower insulating layer 213. The upper insulating layer 212 may be located above the first core layer 211. The lower insulating layer 213 may be located below the first core layer 211.

[0078] The encapsulated electrode portion may include a first core electrode portion 221, an upper encapsulated electrode portion 222, and a lower encapsulated electrode portion 223.

[0079] The first core electrode portion 221 may include a first core wiring portion 221a disposed on the first core layer 211 and a first core via electrode 221b passing through the first core layer 211. For example, the first core wiring portion 221a may be disposed on one surface (i.e., the upper surface and / or the lower surface) of the first core layer 211.

[0080] The upper electrode portion 222 of the package may be disposed on the upper insulating layer 212. The upper electrode portion 222 of the package may include the upper wiring portion of the package disposed on the upper insulating layer 212 and the upper via electrode of the package passing through the upper insulating layer 212.

[0081] Furthermore, the lower electrode portion 223 of the package may be disposed in the lower insulating layer 213. The lower electrode portion 223 of the package may include a lower package wiring portion disposed on the lower insulating layer 213 and a lower package via electrode passing through the lower insulating layer 213.

[0082] In addition, the circuit board 100 may include an insulating layer 110, an electrode portion 120, and a connecting member BR.

[0083] In this embodiment, the insulating layer 110 may be configured as a structure with multiple insulating layers stacked. The electrode portion 120 may be configured to be embedded in each of the multiple insulating layers 110 and may be used to transmit signals and / or power from a motherboard (not shown) to a semiconductor device.

[0084] Furthermore, when the circuit board includes a core layer, the circuit board may include stacked insulating portions stacked on the core layer. Specifically, as shown, the circuit board 100 may include a second core layer 111, stacked insulating portions 112 and 113, a second core electrode portion 121, and stacked electrode portions 122 and 123. Additionally, the circuit board 100 may also include a protective layer SR and a bump portion BP. Furthermore, in the embodiments of the invention described below, each of the stacked insulating portions 112 and 113 may include multiple insulating layers and may have a structure of stacked multiple insulating layers. Moreover, this structure of insulating layers can be applied to the encapsulation insulating layer of the aforementioned packaging substrate. The stacked electrode portions 122 and 123 may be configured to be embedded in each layer (e.g., an insulating layer) of the stacked insulating portions 112 and 113 and may be used to transmit signals and / or power from a motherboard (not shown) to a semiconductor device.

[0085] Furthermore, the insulating layer 110 of the circuit board may include a second core layer 111, an upper stacked layer 112, and a lower stacked layer 113. The upper stacked layer 112 may be located on the second core layer 111. In addition, the lower stacked layer 113 may be located below the second core layer 111.

[0086] Additionally, electrode portion 120 may include via electrodes and wiring portions, as described below.

[0087] In an embodiment, the insulating layer 110 may include a second core layer 111 and laminated insulating portions 112 and 113 respectively disposed on and below the second core layer 111, each of the laminated insulating portions 112 and 113 including at least one insulating layer. Therefore, the laminated insulating portions 112 and 113 stacked on the core layer may include multiple vertically stacked insulating layers. The laminated insulating portions may include an upper laminate 112 and a lower laminate 113. As shown, the upper laminate 112 may be disposed on the second core layer 111, and the lower laminate 113 may be disposed below the second core layer 111. Each of the upper and lower laminates may include multiple stacked insulating layers. Furthermore, the laminate (or laminated insulating portion) may also be referred to as a laminated structure, laminated insulating portion, etc. The following description will be based on these terms.

[0088] In one embodiment, the insulating layer 110 may include a second core layer 111, an upper laminate 112, and a lower laminate 113. Furthermore, a protective layer SR may be disposed on the outside of the insulating layer 110.

[0089] Furthermore, the upper laminate 112 can be an "upper laminate structure," and the lower laminate 113 can be a "lower laminate structure." In this embodiment, the second core layer 111 can be disposed at the center portion of the insulating layer 110 in the vertical direction. When the laminates are stacked on opposite surfaces of the second core layer 111, the second core layer 111 can be located at the center of the insulating layer 110. That is, the upper laminate 112 can be disposed above the second core layer 111, and the lower laminate 113 can be located below the second core layer 111.

[0090] Furthermore, the insulating layer 110 of the circuit board 100 can be rigid or flexible. For example, the insulating layer 110 of the circuit board 100 can include glass or plastic. For example, the insulating layer 110 of the circuit board, or each insulating layer constituting the insulating layer 110, can include chemically strengthened glass / chemically semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer 110 of the circuit board can include rigid or flexible plastics, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the circuit board can include sapphire. For example, the insulating layer 110 of the circuit board can include an optically isotropic film. For example, the insulating layer 110 of the circuit board can include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 of the circuit board can be formed of a material including fillers and insulating resins. For example, the insulating layer 110 of the circuit board may have a structure in which silica or alumina fillers are disposed in a thermosetting resin or a thermoplastic resin.

[0091] The insulating layer 110 may have a structure in which various different insulating materials are stacked. Exemplary arrangements thereof will be described in more detail below.

[0092] In one embodiment, the insulating layer 110 may include a second core layer 111, which includes reinforcing members. Here, the second core layer 111 may include reinforcing members and may have a thickness in the vertical direction (Y-axis direction or stacking direction) ranging from tens to hundreds of micrometers. Furthermore, an upper stacked layer 112 and a lower stacked layer 113 may be disposed above and below the second core layer 111, respectively, and may each include multiple layers without reinforcing members. The reinforcing members may also be referred to as reinforcing fibers or glass fibers embedded in the core layer. The reinforcing members may refer to glass fiber material extending in the horizontal direction (X-axis direction) of the insulating layer and may have a meaning different from that of fillers that are discretely separated from each other. For example, the insulating layer 110 may include resin, fillers, and reinforcing members (e.g., glass fibers), or it may include resin and fillers.

[0093] The second core layer 111 can be formed of various insulating materials. For example, the second core layer 111 can be part of a copper clad laminate (CCL). Alternatively, the core layer can correspond to a copper clad laminate. Furthermore, the second core layer 111 can include multiple layers, and the multiple layers can be formed of the same material or different materials. Additionally, the second core layer 111 can include via electrodes extending from the upper surface of the second core layer 111 through the lower surface of the second core layer 111.

[0094] Furthermore, the upper laminate 112 or the lower laminate 113 can be formed from any insulating resin, such as a thermosetting resin and / or a photocurable resin. As a thermosetting resin, Ajinomoto Build-up Film (ABF) manufactured by Ajinomoto Co., Ltd. can be used, and prepreg (PPG) including glass fibers can also be used. As a photocurable resin, an insulating resin such as a photoimageable dielectric (PID) can be used. The aforementioned insulating resin can be, for example, epoxy resin, bismaleimide triazine (BT) resin, phenolic resin, etc., and can include inorganic fillers such as silica. When the insulating resin is used as a core, the insulating resin can include reinforcing materials or reinforcing members, such as glass fibers or aramid fibers. For example, when manufacturing the insulating layer 110, ABF manufactured by Ajinomoto Co., Ltd. can be used, and FR-4, BT, PID resin, BT, etc., can also be used. For example, when the circuit board 100 is a coreless board, the insulating layer 110 can have an ABF stack structure without a core layer.

[0095] Furthermore, the upper layer 112 may include a plurality of insulating layers configured to contact the second core layer 111. These insulating layers may contain fillers of different sizes. For example, the size of the filler may decrease towards the upper side of the plurality of insulating layers. Additionally, the width or spacing of the upper electrode portions may decrease towards the uppermost layer of the plurality of insulating layers.

[0096] Furthermore, the wiring or electrode portion 120 according to the embodiment can be configured to provide an electrical connection between a chip (or semiconductor device or die) and a motherboard, etc. The electrode portion 120 may include wiring portions (e.g., circuit patterns, circuit pattern layers, pads or pattern portions) and via portions (or via electrodes).

[0097] For example, the wiring portion of electrode portion 120 may include patterns and pads disposed on the upper surface of the insulating layer. Hereinafter, the term "wiring portion" may be used interchangeably with the terms "circuit pattern" and "pattern portion". Furthermore, electrode portion 120 may also include via portions or via electrodes passing through the insulating layer. Therefore, in this embodiment, electrode portion 120 will be described as including wiring portions (circuit patterns) and via electrodes in each insulating layer. Furthermore, the wiring portions of electrode portion 120 may be designed in various forms to transmit signals and / or power to and from semiconductor devices, and may be disposed in each insulating layer of the stacked multilayer insulating portions 112 and 113.

[0098] In electrode portion 120, via electrodes (or via portions) may be configured to pass through at least a portion of each insulating layer of multilayer insulating portions 112 and 113 to vertically connect circuit patterns disposed in each insulating layer. Via electrodes can electrically connect multiple circuit patterns (wiring portions) to each other. Multiple via electrodes can be provided when multiple wiring portions are present. That is, the insulating layer may include vias for arranging the via electrodes. Furthermore, the width of the via electrode may be greater than the width of the circuit pattern for impedance optimization or heat dissipation, but is not limited to this, and can be freely designed.

[0099] In electrode portion 120, wiring portions (circuit patterns) can be provided in each insulating layer. Furthermore, the circuit patterns can be electrically connected to each other. Additionally, the wiring portions (or circuit patterns) can be connected to corresponding via electrodes. Furthermore, the circuit patterns provided on the upper and lower surfaces of the insulating layers in the stacked insulating portions 112 and 113 can be electrically connected to semiconductor devices and / or motherboards, substrates, etc. For example, electrode portion 120 can be located in each of the second core layer 111, upper stacked layer 112, and lower stacked layer 113 (insulating layers).

[0100] In this embodiment, the electrode portion 120 may include a second core electrode portion 121, an upper electrode portion 122, and a lower electrode portion 123. The upper electrode portion 122 and the lower electrode portion 123 may be multilayer electrode portions. Furthermore, the upper electrode portion 122 may be disposed in each insulating layer of the upper multilayer 112, and may be an "upper multilayer electrode portion". Similarly, the lower electrode portion 123 may be disposed in each insulating layer of the lower multilayer 113, and may be a "lower multilayer wiring portion electrode".

[0101] The second core electrode portion 121 may include a second core wiring portion 121a disposed on the upper and lower surfaces of the second core layer 111 and a second core via electrode 121b passing through the second core layer 111.

[0102] The upper electrode portion 122 may include an upper wiring portion 122a and an upper via electrode 122b. The upper wiring portion 122a is a wiring portion disposed on the upper and lower surfaces of each insulating layer of the upper stacked layer 112, and the upper via electrode 122b is a via electrode. The upper via electrode 122b can pass through each insulating layer of the upper stacked layer 112.

[0103] Furthermore, the lower electrode portion 123 may include a lower wiring portion 123a and a lower via electrode 123b. The lower wiring portion 123a is a wiring portion disposed on the upper and lower surfaces of the lower stacked layer 113, and the lower via electrode 123b is a via electrode. Additionally, the lower via electrode 123b may pass through each insulating layer of the lower stacked layer 113.

[0104] In an embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion with a fine pitch (a first wiring portion) and a wiring portion with a pitch larger than that of the first wiring portion (a second wiring portion).

[0105] The second wiring portion can refer to a line with a line width and spacing comparable to the circuit patterns used in conventional circuit boards. The first wiring portion can refer to a fine line with a line width and spacing smaller than the patterns conventionally used in circuit boards, and can be used for interconnection between semiconductor devices, impedance matching, or inductor formation. For example, the first wiring portion can have a line width of a few micrometers (μm) or less, or a spacing of tens of micrometers or less. For example, the first wiring portion can have a width of 30 μm or less. For example, the first wiring portion can have a spacing of 55 μm or less. A detailed description is provided below.

[0106] Furthermore, the circuit board 100 according to the first embodiment may also include a protective layer SR and a bump portion BP.

[0107] Specifically, the protective layer SR can be used to protect the pads from external moisture or contaminants. To prevent short-circuit problems during the bonding process between the circuit board and the semiconductor device and / or motherboard, the protective layer SR can be formed of, for example, a solder resist. Specifically, the semiconductor device and / or motherboard can have multiple terminals to be connected to the circuit board. Furthermore, the multiple terminals can be arranged in a high density. Solder can be used as an example when the multiple terminals are bonded to the pads of the circuit board. When using solder, solder short-circuit problems may occur between the high-density terminals, and to solve this short-circuit problem, a solder resist with poor solder wetting properties can be provided. In addition, the protective layer SR can be formed of a material having insulating properties with respect to electrical connections. The protective layer SR can include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acryloyl monomers, etc. In addition, the protective layer SR can include any of a photoresist layer, a capping layer, and a polymer material. The protective layer SR can have at least one opening for the connection between the terminals of the semiconductor device and the pads of the circuit board. For example, in this embodiment, the protective layer SR can be formed of a resin and a filler as a reinforcing member.

[0108] A protective layer SR may be disposed on the insulating layer 110. Furthermore, the protective layer SR may contain various fillers. Specifically, the protective layer SR may include a first protective layer SR1 disposed above the upper stack 112 and a second protective layer SR2 disposed below the lower stack 113. The first protective layer SR1 and the second protective layer SR2 may be spaced apart from each other in the stacking direction and may have different thicknesses to account for board warping. The protective layer will be described below based on the first protective layer SR1.

[0109] A bump portion BP may be disposed on the protective layer SR. For example, the bump portion BP may be disposed on the upper surface of the protective layer SR. The bump portion BP may be located further outward than the multilayer electrode portions 122 and 123. For example, the bump portion BP may be located on the multilayer electrode portions 122 and 123 relative to the upper multilayer 112. Furthermore, the bump portion BP may include a protrusion PP disposed on the upper surface of the protective layer SR and a via portion TP passing through the protective layer SR. In an embodiment, each of the via portion TP and the protrusion PP may include a plurality of protrusions or projections protruding toward the adjacent protective layer SR. For example, on the first protective layer SR1, the via portion TP and the protrusion PP may include a plurality of protrusions (or projections) protruding toward the first protective layer SR1.

[0110] Furthermore, a metal layer can be additionally disposed on the bump portion BP and electrically connected to the bump portion BP. Therefore, the durability and reliability of the bump portion BP can be further improved. For example, the metal layer may include at least one metal layer. The metal layer can be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or combinations thereof. Therefore, the bonding strength between the metal layer and the bump portion BP can be improved, the corrosion resistance and durability of the bump portion BP can be enhanced, and the loss of electrical signals can be minimized. The metal layer can be formed on the bump portion BP using deposition, electroplating, or other methods with various metals.

[0111] Furthermore, semiconductor devices can be disposed on the upper layer 112. The semiconductor devices can be electrically connected to a first wiring portion, which is the aforementioned fine pattern, etc. The circuit board can be configured to have a high wiring density for signal connections with the semiconductor devices. Furthermore, the first wiring portion, as a fine pattern, can provide a signal path for signal connections with the semiconductor devices, or can provide a signal connection for each semiconductor device (e.g., a signal connection with the lower substrate). Therefore, unnecessary increases in the size of the semiconductor devices can be prevented, thereby improving the yield of the semiconductor devices.

[0112] Furthermore, based on their function, circuit boards can be classified as packaging substrates or interposers. Packaging substrates are used to mount semiconductor devices and / or interposers. Due to increasing data volume, circuit board yield may significantly decrease due to increased circuit board area or an increase in the number of stacked insulating layers. Therefore, to improve the yield of circuit boards with a large number of stacked layers, circuit boards can be divided into interposers and packaging substrates, thereby increasing circuit board yield. Additionally, as the density of semiconductor device terminals increases, it may be difficult to implement pads on the packaging substrate with regions corresponding to the semiconductor device terminals. Therefore, interposers can act as a buffer between the pad size of the packaging substrate and the fine pattern size of the semiconductor device terminals.

[0113] As described above, depending on the configuration of the insulating layer, the aforementioned packaging substrate and interposer can each be classified as a core substrate or a coreless substrate. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer in the stacked insulating layers that includes reinforcing members. The reinforcing members may refer to glass fiber. The core layer may be configured to be thicker than other insulating layers and may have functions such as preventing warping of the circuit board during the manufacturing process. However, the core layer may cause problems such as voltage drop and signal loss, or may make it difficult to achieve a reduced thickness. Therefore, depending on the application, a coreless substrate in which the insulating layer of the circuit board does not include a core layer may be used.

[0114] In this embodiment, the second core layer 111 of the circuit board 100 may include a cavity CV. That is, the circuit board 100 may include a second core layer 111, and the second core layer 111 includes a cavity CV. The cavity CV may pass through at least one of the upper stacked layer 112, the second core layer 111, and the lower stacked layer 113. In this embodiment, the cavity CV may be referred to differently as a "groove," "recess," "hole," "via," etc. Furthermore, in a plan view, the cavity CV may have various shapes, such as a circular shape or a quadrilateral shape. In addition, the inner wall of the cavity CV or the inner side of the second core layer 111 may have a structure in which the width or diameter increases from the center portion of the second core layer 111 toward the upper surface and from the center portion of the second core layer 111 toward the lower surface. Alternatively, the inner wall of the cavity CV or the inner side of the second core layer 111 may only have a structure in which the width or diameter increases from the center portion of the second core layer 111 toward the upper surface or from the center portion of the second core layer 111 toward the lower surface.

[0115] Furthermore, the cavity CV can have various shapes, depending on the shape of the device (e.g., a connecting member) installed therein. For example, the connecting member can typically have a quadrilateral shape in a plane perpendicular to the stacking direction. Correspondingly, the cavity CV can also have a quadrilateral shape in a plane perpendicular to the stacking direction. However, the cavity CV can have various shapes to facilitate the installation of the connecting member BR.

[0116] The circuit board 100 may include a connection member BR. Furthermore, the connection member BR may be located within a cavity CV. That is, the cavity CV allows for easy securing of mounting space for the connection member BR and the like within the upper stacked layer 112. Additionally, a lower electrode portion 123, having a smaller linewidth than the upper electrode portion 122 located outside the cavity CV, can be easily disposed on the cavity CV. Therefore, the circuit board according to the embodiment facilitates interconnection between semiconductor devices and provides an increased input / output (I / O) count.

[0117] According to an embodiment, the connecting member BR can be embedded in the cavity CV of the second core layer 111. That is, according to this embodiment, the circuit board 100 may include the second core layer 111 to prevent warping while reducing the thickness, and in this case, the connecting member BR can be embedded in the second core layer 111. Furthermore, as described above, since the connecting member BR is disposed in the second core layer 111, the reliability of the circuit board can be maintained even when the connecting member BR is installed therein, and various types of connecting members BR can be installed.

[0118] Additionally, the connecting member BR may be located in the second core layer 111 of the circuit board 100 and may overlap with the second core layer 111 in the horizontal direction (X-axis direction). For example, the connecting member BR may not be provided in the upper layer 112 or the lower layer 113 of the circuit board 100.

[0119] Furthermore, when at least a portion of the connecting member BR is embedded in the upper stack 112, the connecting member BR can be mounted within a limited height available in the upper stack 112. Additionally, as the length (thickness) of the connecting member BR increases in the stacking direction, cavities are formed in the upper stack 112, which includes multiple insulating layers, potentially causing problems such as delamination and cracking at the interfaces between the multiple insulating layers. Therefore, by mounting as much of the connecting member BR as possible in the second core layer 111, the connecting member BR can be easily mounted, regardless of its size. Furthermore, since it is not necessary to form through-holes through the interfaces between multiple insulating layers to mount the connecting member, the reliability of the circuit board can be improved.

[0120] Since the circuit board 100 according to this embodiment can be used as an intermediary layer and therefore may need to have a reduced thickness, the connecting member BR can be embedded in the second core layer 111.

[0121] Furthermore, the upper laminate 112 can be disposed on the second core layer 111, and a portion thereof can be disposed within the cavity CV of the second core layer 111. Therefore, a portion of the lower surface of the upper laminate 112 can contact a portion of the upper surface of the lower laminate 113, and these portions can be coplanar with each other. This configuration can be implemented within the cavity CV.

[0122] Further reference Figure 5 and Figure 6 In this embodiment, the thickness ta of the packaging substrate 200 may be different from the thickness tb of the circuit board 100. For example, the thickness ta of the packaging substrate 200 may be greater than the thickness tb of the circuit board 100.

[0123] Furthermore, the thickness t1 of the first core layer 211 of the packaging substrate 200 may be different from the thickness t2 of the second core layer 111 of the circuit board 100. For example, the thickness t1 of the first core layer 211 of the packaging substrate 200 may be greater than the thickness t2 of the second core layer 111 of the circuit board 100.

[0124] This configuration improves the overall mechanical strength and stability of the semiconductor package structure. Furthermore, semiconductor devices can be mounted on circuit boards, and electrical connection efficiency can be easily maintained. Additionally, heat dissipation is effectively achieved through the relatively thick packaging substrate within the semiconductor package, and structural support is also improved.

[0125] As described above, the cavity CV can pass through at least a portion of the circuit board 100. For example, the cavity CV can pass through the second core layer 111. Additionally, the connecting member BR can be located within the cavity CV.

[0126] As mentioned above, when cavities are designed to traverse multiple layers, the electrical connection paths within the multilayer structure can be shortened, and signal transmission speed can be increased. Specifically, by arranging connecting members within the cavities, the internal space utilization of the circuit board can be increased, and electrical connections between upper and lower layers can be effectively achieved through these connecting members. Therefore, circuit density can be increased, and design flexibility can be improved.

[0127] Furthermore, in some embodiments, the connecting member BR may overlap the second core layer 111 in the horizontal direction. According to various examples, at least a portion of the connecting member BR may be located above the upper surface of the second core layer 111, or at least a portion of the connecting member BR may be located below the lower surface of the second core layer 111.

[0128] Furthermore, the first core layer 211 may include a first through-hole 211h. The second core layer 111 may include a second through-hole 211h. Therefore, by forming through-holes in the first and second core layers, interlayer electrical connections (e.g., vias) can be achieved.

[0129] In this embodiment, the first through hole 211h and the second through hole 111h may have different shapes. The width Wa of the first through hole 211h may be the same on the upper surface, lower surface and central portion of the first core layer 211.

[0130] Conversely, the width Wb of the second via 111h can decrease toward the center of the second core layer 111 or the second via 111h.

[0131] With this configuration, the first core electrode portion in the first via 211h can have a constant impedance, thereby facilitating high-speed signal transmission. Additionally, the connection portions on both sides of the second via 111h can be widened, reducing reliability issues such as solder cracking and interface delamination. In other words, mechanical fixation and thermal / stress distribution can be improved.

[0132] Specifically, the first via electrode 221b can be located in the first via 211h. Additionally, the second via electrode 121b can be located in the second via 111h.

[0133] The first core via electrode 211b can be located on the inner surface of the first through hole 211h, and can not completely fill the interior of the first through hole 211h. That is, an empty space VC can be formed inside the first through hole 211h.

[0134] Furthermore, since the width Wa of the first via electrode 221b remains small, the stress relief effect can be improved. The second via electrode 121b can completely fill the second via 211h, thereby significantly improving the thermal and electrical properties.

[0135] Furthermore, the outer surface ES of the connecting member BR can face the first surface S1, which is the inner surface of the cavity CV formed in the second core layer 111. The central portion of the first surface S1 in the stacking direction or the vertical direction (Y-axis direction) can protrude toward the outer surface of the connecting member BR.

[0136] In other words, the gap between the first surface S1 and the connecting component BR can be minimized at the center of the cavity in the stacking direction (Y-axis direction). Additionally, the gap between the first surface S1 and the connecting component BR can increase from the center towards the upper or lower surface of the cavity CV.

[0137] For example, when the first surface S1 of the cavity CV and the outer surface ES of the connecting member BR are adjacent to or in contact with each other, the connecting member BR can be easily aligned within the cavity CV. Furthermore, the connecting member BR can be easily installed within the cavity CV.

[0138] Furthermore, due to the shape of the first surface of the cavity CV, stress caused by external forces or thermal expansion from mounting connection components BR, etc., may not be concentrated at a single point. Therefore, stress can be smoothly transmitted, effectively reducing the likelihood of cracking or delamination at specific locations. In other words, stress can be distributed and transmitted along the first surface of the cavity without concentrating in the central portion, thereby improving the durability of the circuit board and semiconductor package against thermal expansion or mechanical shock.

[0139] Furthermore, the thickness t2 of the second core layer 111 and the thickness t3 of the connecting member BR can be the same or different from each other. In this embodiment, the thickness t2 of the second core layer 111 can be greater than the thickness t3 of the connecting member BR.

[0140] Furthermore, the upper surface of the second core wiring portion 121a may be coplanar with the upper surface of the upper wiring BE disposed on the upper surface of the upper wiring BE. In this way, the thickness tc of the second core wiring portion 121a may be formed to correspond to the thickness td of the upper wiring BE disposed on the upper surface of the upper wiring BE.

[0141] This configuration simplifies the electrical connection between the top and second-core wiring sections and optimizes the signal transmission path, thereby reducing electrical losses. Furthermore, planarization processes such as chemical mechanical polishing (CMP) can be easily performed during manufacturing processes (e.g., when forming the top layer), improving production efficiency and helping to reduce the overall thickness of the circuit board. Additionally, height differences between wirings can be minimized to prevent signal delay or impedance mismatch and improve high-speed signal transmission performance.

[0142] Further reference Figure 7 The upper surface of the second core layer 111 may or may not be coplanar with the upper surface of the connecting member BR. For example, the upper surface of the second core layer 111 may have the same height as the lower surface of the second core layer 111 relative to the upper surface of the connecting member BR.

[0143] Furthermore, the upper surface of the second core layer 111 may be located below the upper surface of the connecting member BR. Alternatively, the upper surface of the second core layer 111 may be located above the upper surface of the connecting member BR.

[0144] Furthermore, the height from the upper surface of the second core layer 111 to the upper surface of the second core wiring portion 121a and the height from the upper surface of the second core layer 111 to the upper surface of the upper wiring BE can be different from or the same as each other. For example, according to the manufacturing method, the height from the upper surface of the second core layer 111 to the upper surface of the second core wiring portion 121a and the height from the upper surface of the second core layer 111 to the upper surface of the upper wiring BE can be adjusted to correspond to each other. The height from the upper surface of the second core layer 111 to the upper surface of the second core wiring portion 121a can be greater than the height from the upper surface of the second core layer 111 to the upper surface of the upper wiring BE.

[0145] In this way, the thickness and height of the upper wiring BE, etc., can be adjusted according to the thickness of the connecting member BR to correspond to the thickness and height of the second core wiring portion 121a. Therefore, it is easier to install the connecting member within the second core layer 111.

[0146] Further reference Figure 8 The bump portion BP may include a protrusion PP disposed on the upper surface of the protective layer SR and a via portion TP passing through the protective layer SR. In addition, the bump portion BP may also include a first layer L1 and a second layer L2.

[0147] The first layer L1 can be located below the second layer L2. Furthermore, at least a portion of the first layer L1 can protrude above the upper surface of the protective layer SR. Therefore, at least a portion of the first layer L1 can be horizontally separate from the protective layer SR.

[0148] Furthermore, the edge of the first layer L1 may include a downwardly formed groove. In this case, the second layer L2 may extend downward along the edge of the first layer L1. The second layer L2 may include a first region AR1 and a second region AR2. The first region AR1 may overlap with the protective layer SR in the horizontal direction. Additionally, the first region AR1 may be located below the upper surface of the first protective layer SR1.

[0149] Furthermore, the second region AR2 may not overlap with the first protective layer SR1 in the horizontal direction. The second region AR2 may be located above the upper surface of the first protective layer SR1.

[0150] The first region AR1 can be a recessed structure extending downward along the edge of the first layer L1. Additionally, the second region AR2 can extend upward, corresponding to a region extending horizontally toward the center or upper portion of the first layer L1. The second layer L2 can have a wider horizontal width than the first layer L1.

[0151] Furthermore, the first layer L1 may include a third region AR3 that overlaps with the first protective layer SR1 in the horizontal direction and a fourth region AR4 located above the upper surface of the first protective layer SR1. The fourth region AR4 may be surrounded by a second region AR2. Additionally, the first region AR1 may be located at the edge of the third region AR3.

[0152] Furthermore, the first layer L1 and the second layer L2 can be formed of different materials. For example, the first layer L1 may include copper (Cu), and the second layer L2 may include nickel (Ni).

[0153] Furthermore, the first layer L1 may be located within a through-hole of the first protective layer SR1. The inner wall of the through-hole in the first protective layer SR1 may contact the first layer L1 and the second layer L2. In this case, the contact thickness d4 of the first layer L1 contacting the inner wall of the through-hole may differ from the contact thickness d3 of the second layer L2 contacting the inner wall of the through-hole. For example, the contact thickness d4 of the first layer L1 contacting the inner wall of the through-hole may be less than the contact thickness d3 of the second layer L2 contacting the inner wall of the through-hole. The ratio of the contact thickness d4 of the first layer L1 contacting the inner wall of the through-hole to the contact thickness d3 of the second layer L2 contacting the inner wall of the through-hole may be in the range of 0.6:1 to 0.95:1. In this case, when the second layer L2 relative to the inner wall of the through-hole is outside the above-mentioned ratio range, the brittleness of nickel may lead to the risk of cracking or breakage at the connection between the bump portion and the bare die. Furthermore, since nickel has a lower thermal conductivity than copper, the bump portion may have a reduced ability to accommodate thermal deformation.

[0154] Furthermore, due to the aforementioned ratio, nickel, with its higher hardness and greater durability than copper, can provide the circuit board with increased resistance to mechanical stress or impact. Additionally, because nickel is more resistant to oxidation than copper, the bump portions adjacent to the exterior are suitable for long-term use. Therefore, reliability can be improved.

[0155] Figures 9 to 15 This is a view illustrating a method for manufacturing a circuit board and a package according to an embodiment of the present invention.

[0156] It should be noted here that one or more operations can be combined to simplify and / or clarify the operations used to provide or manufacture the circuit board. In some embodiments, the order of operations can be changed or modified. In some embodiments, one or more operations of the manufacturing method can be replaced by other operations without departing from the spirit of this disclosure. Depending on the different embodiments, the circuit board can be manufactured in different ways.

[0157] refer to Figure 9A second core layer 111 may be provided. As described above, the second core layer 111 may be an insulating layer with a predetermined thickness or greater. Furthermore, the second core layer 111 may comprise glass or glass fiber containing resin. However, the second core layer 111 may comprise different materials.

[0158] Reference Figure 10 Vias or through-holes 111h can be formed in the second core layer 111. Through-holes can be formed to pass through the upper and lower surfaces of the second core layer 111. Through-holes or through-holes can be formed by methods such as laser drilling.

[0159] refer to Figure 10 The second core electrode portion 121 can be formed in the second core layer 111. The electrode portion can be formed by a patterning process based on mask formation (such as exposure and curing), a stripping (removal) process, and / or a plating process.

[0160] For example, an electroplating process can be performed on the vias formed in the second core layer 111 to form through electrodes. Furthermore, core wiring portions can be formed on the upper and lower surfaces of the second core layer 111. The core wiring portions can have a pattern defined by a mask or the like. Moreover, the core wiring portions can be formed using additive manufacturing processes, subtractive manufacturing processes, modified semi-additive manufacturing processes (MSAP), and semi-additive manufacturing processes (SAP) used in printed circuit board manufacturing processes. This can also be applied to other wiring portions.

[0161] refer to Figure 11 The cavity CV can be formed in a region of the second core layer 111 by any of a variety of methods such as laser processing. The cavity CV can penetrate through the second core layer 111. The cavity CV can extend to a portion of the second core layer 111. That is, the cavity CV can be a hole or a groove.

[0162] Further reference Figure 12 The connecting member BR can be installed in the cavity CV of the second core layer 111. When the cavity CV, which serves as a through hole, is formed in the second core layer 111, the connecting member BR can be installed in the cavity CV using a stop portion (not shown).

[0163] Furthermore, the position of the connecting member BR can be easily adjusted using a stop (not shown), etc. For example, a mark (e.g., an alignment mark) for aligning the connecting member BR can be formed on the stop (not shown). With this configuration, the connecting member BR can be positioned at a more precise location within the cavity CV, depending on the design. For example, the position of the connecting member BR can be adjusted so that the center of the connecting member BR is located at the center of the cavity CV.

[0164] refer to Figure 13The upper lamination 112 can be formed on the second core layer 111 and in the cavity CV. In addition, the lower lamination 113 can be formed below the second core layer 111.

[0165] Furthermore, before forming the upper layer 112, a bottom filling process can be performed to fix the position of the connecting member BR in the cavity CV. For example, a filling member can be further applied to the cavity CV. Therefore, the filling member can improve the bonding strength between the second core layer 111 and the connecting member BR. Thus, the circuit board can be protected from impacts, drops, and vibrations. In addition, deformation caused by the difference in thermal expansion between the connecting member BR and another component (such as the second core layer 111) can be reduced. The filling member F1 may include epoxy resin, etc.

[0166] Furthermore, as described above, the upper lamination 112 can be applied to the cavity CV. Therefore, the upper lamination 112 can be disposed in the cavity CV, allowing the connecting member BR to be installed in the cavity CV.

[0167] refer to Figure 14 Vias or through-holes can be formed in the upper stacked layer 112 and / or the lower stacked layer 113. Vias can be formed by methods such as laser drilling, punching, etching (mechanical drilling, chemical etching or any other suitable mechanism).

[0168] Furthermore, the upper electrode portion 122 can be formed in the upper stacked layer 112. Furthermore, the lower electrode portion 123 can be formed in the lower stacked layer 113. The upper electrode portion 122 and the lower electrode portion 123 can be formed by patterning processes, stripping (removal) processes, and / or plating processes based on mask formation (such as exposure and curing).

[0169] Furthermore, the upper wiring portion of the upper electrode portion 122 can be formed on the upper surface of the upper stacked layer 112, and the lower wiring portion of the lower electrode portion 123 can be formed on the lower surface of the lower stacked layer 113. Each wiring portion can have a pattern formed using a mask or the like. Furthermore, the wiring portions can be formed using additive manufacturing processes, subtractive manufacturing processes, improved semi-additive manufacturing processes (MSAP), semi-additive manufacturing processes (SAP), etc., used in printed circuit board manufacturing processes.

[0170] Subsequently, a first protective layer SR1 can be formed on the upper laminate 112. Furthermore, a second protective layer SR2 can be formed below the lower laminate 113. Additionally, a via portion TP can be formed through the protective layer SR.

[0171] refer to Figure 15As described above, after the circuit board 100 is formed, semiconductor devices DI1 and DI2 can be mounted on it, and the packaging substrate 200 is disposed below it. For example, after semiconductor devices DI1 and DI2 are mounted on the circuit board 100, the circuit board 100 on which semiconductor devices DI1 and DI2 are mounted can be mounted on the packaging substrate 200.

[0172] Specifically, individual semiconductor devices (i.e., bare dies) can be cut from a wafer. In this case, lasers or cutting blades can be used to achieve the cutting.

[0173] Furthermore, the semiconductor devices can be mounted on the interposer layer. Semiconductor devices DI1 and DI2 can be precisely positioned on circuit board 100. Additionally, semiconductor devices DI1 and DI2 can be secured to circuit board 100 using various bonding components.

[0174] Furthermore, semiconductor devices DI1 and DI2, as well as circuit board 100 serving as an interposer, can be attached to package substrate 200. Subsequently, additional molding or other processes can be performed.

[0175] Furthermore, reflow and other processes can be performed on the circuit boards 100 and packaging substrate 200 of semiconductor devices DI1 and DI2. Additionally, electrical performance tests can be performed on the manufactured semiconductor packages. Furthermore, visual and mechanical inspections can be performed simultaneously.

[0176] Furthermore, when a circuit board having the above-described features of this invention is used in information technology (IT) equipment or home appliances (such as smartphones, server computers, or TVs), it can reliably perform functions such as signal transmission and / or power supply. For example, when a circuit board having the features of this invention is used as a semiconductor package, the circuit board can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and open circuit faults at the terminals supplying power to the semiconductor chip. In addition, when the circuit board is used for signal transmission, it can solve noise problems. Therefore, a circuit board having the above-described features of this invention can help maintain the stable operation of IT equipment or home appliances, and the entire product and circuit board using this invention can achieve functional integration or technical linkage.

[0177] When a circuit board with the features of the present invention described above is used in transportation equipment such as vehicles, the circuit board can resolve signal distortion in signals transmitted to the transportation equipment. Alternatively, the circuit board can further improve the reliability of the transportation equipment by safely protecting the semiconductor chips configured to control the transportation equipment from external influences and by addressing problems such as leakage current, electrical short circuits between terminals, and open circuit faults at the terminals supplying power to the semiconductor chips. Therefore, the transportation equipment and circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0178] When a circuit board with the features of the present invention described above is used in transportation equipment such as vehicles, the circuit board can resolve signal distortion in signals transmitted to the transportation equipment. Alternatively, the circuit board can further improve the reliability of the transportation equipment by safely protecting the semiconductor chips configured to control the transportation equipment from external influences and by addressing problems such as leakage current, electrical short circuits between terminals, and open circuit faults at the terminals supplying power to the semiconductor chips. Therefore, the transportation equipment and circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0179] Although embodiments have been described above, they are merely examples and are not intended to limit the invention. It will be apparent to those skilled in the art that various modifications and applications not described above can be made without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be implemented in a modified form. Furthermore, differences associated with such modifications and applications should be interpreted as including within the scope of the embodiments set forth in the appended claims.

Claims

1. A circuit board, comprising: A packaging substrate, the packaging substrate including a first core layer; A circuit board, the circuit board including a second core layer and disposed on the packaging substrate; and Semiconductor devices mounted on the circuit board, The thickness of the packaging substrate is greater than the thickness of the circuit board, and The thickness of the first core layer is greater than the thickness of the second core layer.

2. The circuit board according to claim 1, wherein the circuit board comprises: An upper lamination disposed on the second core layer; A lower lamination layer disposed below the second core layer; as well as Connecting members disposed in cavities within the circuit board.

3. The circuit board of claim 2, wherein the cavity passes through at least one of the upper laminate, the core layer, and the lower laminate.

4. The circuit board according to claim 2, wherein the connecting member overlaps with the second core layer in the horizontal direction.

5. The circuit board according to claim 2, wherein the first core layer includes a first through-hole, and The second core layer includes a second through-hole.

6. The circuit board of claim 5, wherein the width of the first through hole is the same at the upper surface, lower surface, and center portion of the first through hole, and The width of the second through hole decreases toward the center portion of the second through hole.

7. The circuit board of claim 2, wherein the outer surface of the connecting member faces the first surface of the cavity in the second core layer.

8. The circuit board of claim 7, wherein the central portion of the first surface protrudes toward the outer surface of the connecting member in the stacking direction.

9. The circuit board of claim 7, wherein the gap between the first surface and the connecting member is minimized at the central portion.

10. The circuit board of claim 2, wherein the packaging substrate includes a first core electrode portion, the first core electrode portion including a first core via electrode passing through the first core layer and a first core wiring portion disposed on the first core layer, and The circuit board includes a second core electrode portion, which includes a second core via electrode passing through the second core layer and a second core wiring portion disposed on the second core layer.

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