Read-write device of MIPI (Mobile Industry Processor Interface) display interface and image signal generator

Abstract

The utility model provides a read-write device of an MIPI display interface and an image signal generator. The device comprises an FPGA chip, a first switch and a second switch, the FPGA chip comprises a low-speed transmitter, a receiver, a high-speed transmitter and a controller; the output end of the low-speed transmitter is connected with the first end of the first switch; the output end of the high-speed transmitter is connected with the second end of the first switch; the first end and the third end of the second switch are connected; the second end of the second switch is connected with the input end of the receiver, and the third end of the second switch is used for being connected with an MIPI display interface of external MIPI equipment; the first output end and the second output end of the controller are respectively connected with the control ends of the first switch and the second switch; the first switch is used for controlling the first end and the third end to form a first sending channel or controlling the second end and the third end to form a second sending channel under the control of the controller, and the second switch is used for controlling the first end and the third end to form a third sending channel or controlling the second end and the third end to form a first reading channel under the control of the controller. And data backward reading is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of mobile industry processor interface (MIPI) equipment, and more specifically to a reading and writing device of a MIPI display interface and an image signal generator. Background Art

[0002] The Mobile Industry Processor Interface (MIPI) device has a corresponding data transmission device, which can communicate with the MIPI device so as to transmit target data to the MIPI device. In the related art, the data transmission device only has a transmission channel for writing target data to the MIPI device. However, in some application scenarios, it is necessary to read back data from the MIPI device. For example, the MIPI device can be a display screen with a MIPI display interface, and the image signal generator needs to read back information such as SN when or after the MIPI screen is clicked. The existing data transmission device cannot issue a display command set (Display Command Set, DCS) command that requires data to be returned to the MIPI device, nor does it support bus turn around (Bus Turn Around, BTA) of the data, so it cannot meet the readback requirements for some MIPI devices. Utility Model Content

[0003] The present utility model is proposed in view of the above problems. The utility model provides a reading and writing device of a MIPI display interface and an image signal generator.

[0004] According to one aspect of the utility model, a reading and writing device for a MIPI display interface is provided, comprising: a field programmable gate array chip, a first switch, and a second switch; the field programmable gate array chip comprises: a low-speed transmitter, a receiver, a high-speed transmitter and a controller; wherein the output end of the low-speed transmitter is connected to the first end of the first switch; the output end of the high-speed transmitter is connected to the second end of the first switch; the first end of the second switch is connected to the third end of the first switch; the second end of the second switch is connected to the input end of the receiver; the third end of the second switch is used to be connected to the MIPI display interface of an external MIPI device; the first output end and the second output end of the controller are respectively connected to the control ends of the first switch and the second switch; wherein the first switch is used to control its first end and its third end to form a first sending channel or control its second end and its third end to form a second sending channel under the control of the controller, and the second switch is used to control its first end and its third end to form a third sending channel or control its second end and its third end to form a first reading channel under the control of the controller.

[0005] Exemplarily, the low-speed transmitter has a sending buffer and a packet assembly component, the controller is connected to the packet assembly component, the packet assembly component is connected to the sending buffer component, the controller is used to control the packet assembly component to read the first target data in the sending buffer component and perform packet assembly, and send the packetized first target data to the external MIPI device through the first sending channel in the low-speed mode.

[0006] Exemplarily, the receiver has a receiving buffer and an unpacking component, the controller is connected to the unpacking component, the receiving buffer is connected to the unpacking component, and the controller is used to control the unpacking component to unpack the second target data read back from the external MIPI device through the first read channel by the low-speed module to obtain valid data, and cache the valid data in the receiving buffer.

[0007] Exemplarily, the field programmable gate array chip is a ZYNQ UltraScale+ series chip.

[0008] Exemplarily, the field programmable gate array chip includes a processing system part and a programmable logic part, and the processing system part and the programmable logic part are connected through a lightweight advanced extensible interface.

[0009] Exemplarily, the high-speed transmitter is used to transmit first target data to an external MIPI device through the second transmission channel in the high-speed mode, where the first target data includes image data and / or control data.

[0010] Exemplarily, the external MIPI device is a display screen having a MIPI display interface.

[0011] According to another aspect of the utility model, an image signal generator is provided, comprising the reading and writing device of the above-mentioned MIPI display interface.

[0012] Exemplarily, the image signal generator also includes an external controller, which is connected to the field programmable gate array chip using a network port, and the external controller is used to send a first sending instruction and first target data to the field programmable gate array chip, and / or, send a second read back instruction to the field programmable gate array chip; the field programmable gate array chip is specifically used to send the first target data to the external MIPI device through the second sending channel and the MIPI display interface based on the first sending instruction, and / or, read back the second target data from the MIPI display interface of the external MIPI device based on the second read back instruction.

[0013] Exemplarily, the external controller is a host computer.

[0014] According to the reading and writing device and image signal generator of the MIPI display interface of the embodiment of the utility model, the reading and writing device of the MIPI display interface includes a low-speed transmitter, a receiver, a high-speed transmitter, a first switch and a second switch. The first switch and the second switch can realize the switching of the connection channels between the low-speed transmitter, the receiver, and the high-speed transmitter and the external MIPI device, so that when data needs to be written to the external MIPI device, the target data can be transmitted to the external MIPI device through the low-speed transmitter or the high-speed transmitter, and when the data needs to be read back, the target data can be received from the external MIPI device through the receiver. This solution can realize two-way communication between the reading and writing device of the MIPI display interface and the external MIPI device, and can effectively solve the problem of reading back data from the external MIPI device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other purposes, features and advantages of the present invention will become more apparent by describing the embodiments of the present invention in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0016] Figure 1 A schematic block diagram showing a reading and writing device of a MIPI display interface and an external MIPI device according to an embodiment of the utility model; and

[0017] Figure 2 A schematic block diagram showing at least a partial structure of an image signal generator and a MIPI device according to an embodiment of the present utility model is shown. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the utility model more obvious, the exemplary embodiments according to the utility model will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments of the utility model, and it should be understood that the utility model is not limited to the exemplary embodiments described here. Based on the embodiments of the utility model described in the utility model, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the utility model.

[0019] The MIPI interface protocol can be widely used in various data transmission occasions. For ease of understanding, the following takes the display screen, which is the most typical application object of the MIPI interface protocol, as an example to explain the present invention in detail.

[0020] As a common display device, display screens have been widely used in various electronic devices. Different electronic devices use different types of display screens, such as color display screens and black and white display screens, as well as display screens of different sizes, such as 0.96-inch, 1.44-inch and 1.8-inch display screens. The display screen itself has a built-in processing chip, which is highly customized and only recognizes data in a specific format. Before transmitting data to the display screen, it is usually necessary to configure the registers on the display screen side, which can also be considered as establishing communication with the processing chip of the display screen. The configuration information may include, for example, the length of the data packet, the pixel format, etc. In this way, the display screen can parse the image data according to the configured format, so as to display the required image. For example, if the number of valid bytes in a row of images is configured to 2, when the display screen starts to receive image data, every 2 bytes of data are displayed as 1 row of images. In this way, for different types of display screens, each register of the display screen can be configured according to the configuration instructions in its data manual, so as to set the display screen to a state where it can be displayed. After that, as long as the data in a preset format is sent to the display screen, the display screen can display the image corresponding to the data. This process can be called a dot screen. The information of the configuration register can be sent by a host connected to the display screen, and the host can be implemented by one or more processor chips such as a single chip microcomputer, a microprocessor, a programmable logic controller (PLC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (ASIC), and peripheral circuits that work in conjunction with the processor chip. The above host can include the image signal generator and / or the external controller described herein.

[0021] For some display screens, after displaying a certain number of images, the chip built into the display screen will automatically transmit data back to the host. Some display screens perform bus turnaround (BTA) after receiving specific register configurations, that is, change the data transmission direction, and transmit data back to the host. These data include data about the display status of the display screen, such as whether the display screen has a black screen, a green screen, or a flowery screen. These situations may be caused by abnormal register data due to static electricity and other reasons. After receiving the returned data, the host verifies it to determine whether the display of the display screen is normal. If a display abnormality occurs, it can be restored by hardware reset and reconfiguring registers. For hosts that currently use the MIPI interface protocol, they usually do not have a readback function, so it may not be possible to detect display abnormalities in a timely manner, reducing the reliability of the display.

[0022] For other displays, the host needs to read the display's product serial number (SN) to obtain the display's related information to adjust the host's configuration in conjunction with the display. For a host that does not have a readback function, the above function is obviously not possible.

[0023] In order to at least partially solve the above problems, an embodiment of the utility model provides a read-write device for a MIPI display interface. The read-write device for the MIPI display interface can communicate with an external MIPI device to read and write data to the external MIPI device. The external MIPI device can be any device that can communicate with the read-write device for the MIPI display interface based on the MIPI protocol. Exemplarily, the external MIPI device can be a display screen having a MIPI display interface, and the read-write device for the MIPI display interface can be connected to the display screen through the MIPI display interface to send data including image data, readback instructions, etc., and / or read the readback data of the display screen.

[0024] Figure 1 A schematic block diagram of a MIPI display interface reading and writing device and an external MIPI device according to an embodiment of the present invention is shown. Figure 1 As shown, the reading and writing device of the MIPI display interface includes a field programmable gate array (FPGA) chip 110, a first switch 120 and a second switch 130. It should be noted that Figure 1 The structure of the reading and writing device of the MIPI display interface shown is only an example and not a limitation of the present invention. For example, Figure 1 The FPGA chip 110 shown in FIG. 1 includes a processing system (PS) and a programmable logic (PL). However, the FPGA chip 110 of this architecture is replaceable. Figure 1 The FPGA chip 110 shown is replaced with any existing or future FPGA chip that is different from the PS-PL architecture. Figure 1 The two output terminals shown, namely the first output terminal Ctrl1 and the second output terminal Ctrl2 of the controller described below, can be optionally arranged on the PS side.

[0025] The field programmable gate array chip 110 includes: a low-speed transmitter 112, a receiver 114, a high-speed transmitter 116 and a controller (not shown). The field programmable gate array chip (FPGA) 110 is a semi-custom circuit in a dedicated integrated circuit. It is a programmable logic array. The user can change the connection relationship of its internal circuits through programming, so as to build a circuit module with desired functions inside it. Exemplarily, the field programmable gate array chip 110 can adopt the ZYNQ UltraScale+ series chip. This series of chips is more suitable for processing image signals and is relatively simple to develop.

[0026] The above-mentioned low-speed transmitter 112, receiver 114, high-speed transmitter 116 and controller can all be constructed in the field programmable gate array chip 110 by programming. These are the knowledge known to those skilled in the art and will not be repeated here. The low-speed transmitter 112 is used to send data at a lower rate, such as sending a BTA command to a display screen. The receiver is used to receive data read back from the display screen at a lower rate, and the high-speed transmitter 116 is used to send data at a higher rate, such as video data. The image data described in this article includes video data.

[0027] The first switch 120 includes a first terminal P1, a second terminal P2, and a third terminal P3. Figure 1 As shown, the output end of the low-speed transmitter 112 is connected to the first end P1 of the first switch 120, and the output end of the high-speed transmitter 116 is connected to the second end P2 of the first switch 120. The first switch 120 is at least a switch with 2 inputs and 1 output, and can select to transmit the data of the first end to the third end, or transmit the data of the second end to the third end according to the control signal. The transmission rate of the first switch 120 can at least meet the transmission rate of the high-speed transmitter 116. Exemplarily, the first switch 120 may include a data selector.

[0028] The second switch 130 also includes a first terminal P1, a second terminal P2, and a third terminal P3. The second switch 130 can transmit data from the first terminal P1 to the third terminal P3, or transmit a signal from the third terminal P3 to the second terminal P2, according to a control signal. The first terminal P1 of the second switch 130 is connected to the third terminal P3 of the first switch 120, the second terminal P2 of the second switch 130 is connected to the input terminal of the receiver 114, and the third terminal P3 of the second switch 130 is used to connect to the MIPI display interface of the external MIPI device 200. When the field programmable gate array chip 110 sends high-speed data, such as Figure 1As shown, the data of the high-speed transmitter 116 can reach the third end P3 of the first switch 120 via the second end P2 of the first switch 120, and then reach the third end P3 of the second switch 130 through the first end P1 of the second switch 130, and then reach the MIPI display interface of the external MIPI device 200. When the field programmable gate array chip 110 sends low-speed data, such as Figure 1 As shown, the data of the low-speed transmitter 112 can reach the third end P3 of the first switch 120 via the first end P1 of the first switch 120, and then reach the third end P3 of the second switch 130 through the first end P1 of the second switch 130, and then reach the MIPI display interface of the external MIPI device 200. When the field programmable gate array chip 110 receives low-speed data, as shown in FIG. Figure 1 As shown, the data read back from the MIPI display interface can reach the second end P2 of the second switch 130 via the third end P3 of the second switch 130, and then reach the receiver 114 of the field programmable gate array chip 110. The transmission rate of the second switch 130 can at least meet the transmission rate of the high-speed transmitter 116.

[0029] The first output terminal Ctrl1 and the second output terminal Ctrl2 of the controller are respectively connected to the control terminals of the first switch 120 and the second switch 130. The first switch 120 is used to control its first terminal P1 and its third terminal P3 to form a first transmission channel under the control of the controller, or to control its second terminal P2 and its third terminal P3 to form a second transmission channel. The second switch 130 is used to control its first terminal P1 and its third terminal P3 to form a third transmission channel or to control its second terminal P2 and its third terminal P3 to form a first reading channel under the control of the controller.

[0030] Exemplarily, the MIPI display interface ( Figure 1 The first switch 120 and the second switch 130 are not shown in the figure. The first switch 120 and the second switch 130 may include a clock line MCLK, an IIC line and four pairs of differential lines, wherein the four pairs of differential lines can be used as data transmission channels and connected to the third end P3 of the second switch 130. Therefore, the first switch 120 and the second switch 130 are not only capable of switching one line, but can form multiple sets of parallel channels between the first end P1, the second end P2 and the third end P3. Exemplarily, the first switch 120 and the second switch 130 may include a plurality of sub-switches, each differential line may be connected to a sub-switch, and each sub-switch may only control the connection of one differential line. In short, the second switch 130 can synchronously connect the four pairs of differential lines connected to the first end P1, eight lines to the third end P3 of the second switch 130, thereby forming a third transmission channel between the first end P1 and the third end P3; or synchronously connect the eight lines connected to the second end P2 to the third end P3 of the second switch 130, thereby forming a first read channel between the second end P2 and its third end P3.

[0031] For example, the channel formed by the first switch 120 and the second switch 130 may be bidirectional, and when a first read channel is formed between the second end P2 of the second switch 130 and the third end P3 thereof, the signal is allowed to be transmitted from the third end P3 to the second end P2, and is also allowed to be transmitted in the reverse direction from the second end P2 to the third end P3. In this way, the first switch 120 and the second switch 130 may use the same chip, that is, there is no substantial difference between the sending channel and the reading channel, and only the transmission direction of the signal when reading and writing is artificially specified.

[0032] According to the reading and writing device and image signal generator of the MIPI display interface of the embodiment of the utility model, the reading and writing device of the MIPI display interface includes a low-speed transmitter, a receiver, a high-speed transmitter, a first switch and a second switch. The first switch and the second switch can realize the switching of the connection channels between the low-speed transmitter, the receiver, and the high-speed transmitter and the external MIPI device, so that when data needs to be written to the external MIPI device, the target data can be transmitted to the external MIPI device through the low-speed transmitter or the high-speed transmitter, and when the data needs to be read back, the target data can be received from the external MIPI device through the receiver. This solution can realize two-way communication between the reading and writing device of the MIPI display interface and the external MIPI device, and can effectively solve the problem of reading back data from the external MIPI device.

[0033] Exemplarily, the low-speed transmitter has a sending buffer and a packet assembly component, the controller is connected to the packet assembly component, the packet assembly component is connected to the sending buffer component, the controller is used to control the packet assembly component to read the first target data in the sending buffer component and perform packet assembly, and send the packetized first target data to the external MIPI device through the first sending channel in the low-speed mode.

[0034] like Figure 1As shown, the low-speed transmitter 112 has a transmission buffer 1122 and a package assembly 1124. Exemplarily, the transmission buffer 1122 may include a first-in first-out (FIFO) module. Since the speeds of various parts inside the chip are different, when the first target data is transmitted to the low-speed transmitter, its transmission rate is much higher than the transmission rate of the low-speed transmitter. Therefore, the first target data can be cached through the FIFO, and then packaged into a preset data packet format in the package assembly 1124, such as adding a data packet header and a packet tail. Exemplarily but not restrictively, the data packet can be a short packet of four bytes, the first byte is the type read, the middle 2 bytes are the address, and the last byte is the check. After performing the above steps, the data packet can be sent to the external MIPI device 200 through the first transmission channel, the third transmission channel and the MIPI display interface. The first transmission channel and the third transmission channel can work in low-speed mode and can transmit low-speed data. Setting the transmission buffer 1122 and the package assembly 1124 can enable different areas inside the chip to have different data transmission rates to avoid data loss and errors.

[0035] Exemplarily, the receiver has a receiving buffer and an unpacking component, the controller is connected to the unpacking component, the receiving buffer is connected to the unpacking component, and the controller is used to control the unpacking component to unpack the second target data read back from the external MIPI device through the first read channel with a low-speed module to obtain valid data, and cache the valid data in the receiving buffer.

[0036] like Figure 1 As shown, the receiver 114 may have a receiving buffer 1142 and an unpacking component 1144. Similar to the low-speed transmitter, the receiver can read the low-speed second target data from the external MIPI device 200 through the MIPI display interface and the first read channel. After unpacking the second target data, it is stored in the FIFO of the receiving buffer 1142 at a low speed for buffering. After the buffering is completed, other modules of the chip can read the buffered information at a high speed. This can also avoid data loss or errors.

[0037] Exemplarily, the high-speed transmitter is used to transmit first target data to an external MIPI device through a second transmission channel in high-speed mode, and the first target data includes image data and / or control data. As described above, taking the MIPI display screen as an example, control data is first sent to it to establish a communication connection. Image data can then be sent to it, and the MIPI display screen can display the image. Since the above data is high-speed data, it is consistent with the data transmission rate of the field programmable gate array chip 110, so there is no need to use a cache element, and the data can be transmitted directly to the MIPI display screen. Of course, optionally, a package element can be set to package the data as needed. Figure 1As shown, the high-speed transmitter 116 may have a high-speed transmitter controller 1162 and a packetizer 1164. The high-speed transmitter controller 1162 is used to send the first target data to the packetizer 1164 for packetization. The packetizer 1164 may transmit the packetized first target data to the external MIPI device 200 through the second transmission channel and the third transmission channel.

[0038] By setting the second transmission channel, the MIPI interface can send high-speed data as well as send and receive low-speed data, and the types of compatible external MIPI devices are more abundant.

[0039] Exemplarily, the field programmable gate array chip includes a processing system part and a programmable logic part, and the processing system part and the programmable logic part are connected through a lightweight advanced extensible interface.

[0040] like Figure 1 As shown, the field programmable gate array chip 110 may include a processing system part (PS) and a programmable logic part (PL). Exemplarily, the processing system part may be implemented using an ARM series core. The processing system part may provide advanced processing capabilities and a standard software management interface, making it easier for users to implement and debug complex software functions. The programmable logic part may provide customized hardware acceleration capabilities, which may more conveniently achieve efficient system optimization and function enhancement. Between the two, a lightweight bus interface such as AXI4-Lite may be used for connection, thereby simplifying the design and reducing the occupancy of on-chip resources.

[0041] According to another aspect of the present application, an image signal generator is provided. The image signal generator includes the read / write device of the MIPI display interface. Exemplarily, the image signal generator can read information in, for example, a memory card or a storage chip, and convert it into image data, and transmit the image data to a MIPI device through the read / write device of the MIPI display interface, so that the image is displayed through the MIPI device.

[0042] The image signal generator includes the read / write device of the above-mentioned MIPI display interface, so that the image signal generator can realize two-way communication with the external MIPI device through the read / write device of the MIPI display interface, thereby enabling the image signal generator to realize the function of reading back data from the external MIPI device.

[0043] Exemplarily, the image signal generator further includes an external controller, and the external controller is connected to the field programmable gate array chip via a network port, which may be an Ethernet interface, which has good compatibility and can transmit large amounts of data at high speed. Figure 2 FIG. 1 is a schematic block diagram showing at least a partial structure of an image signal generator according to an embodiment of the present invention and a MIPI device. Figure 2 As shown, the image signal generator may include the above-mentioned MIPI display interface reading and writing device 100. In addition, the image signal generator may also include an external controller 300. The external controller 300 may be used to send a first sending instruction and first target data to the field programmable gate array chip 110. The field programmable gate array chip 110 may be specifically used to send the first target data to the external MIPI device 200 through the second sending channel and the MIPI display interface based on the first sending instruction.

[0044] Optionally, the external controller 300 can be implemented by any suitable processing unit with data processing capability and / or instruction execution capability, and the processing unit may include but is not limited to one or more of a microprocessor, a digital signal processor (DSP), a programmable logic array (PLA), a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), etc. Optionally, the external controller 300 can also be implemented by hardware devices such as a personal computer, a server, and an intelligent terminal. Exemplarily, the external controller 300 may include, for example, a computer host, a programmable logic controller (PLC), a touch screen, etc. Exemplarily, the external controller may include a host computer, and a software program for controlling the image signal generator may be run on the host computer. The host computer may include an input and output device, and the user may interact with the host computer through the input and output device. For example, the user may input a read-write control instruction to the host computer for controlling the image signal generator to read and write the external MIPI device 200. The host computer may send a first sending instruction and first target data to the field programmable gate array chip 110 based on the read / write control instruction input by the user, and / or send a second read-back instruction to the field programmable gate array chip 110 .

[0045] The first sending instruction sent by the external controller 300 can control the field programmable gate array chip 110 to switch to the sending mode, and complete the functions of selecting the first switch 120 and the second switch 130. The first target data may include image data. After receiving the first target data, the field programmable gate array 110 can process it, or directly send it to the external MIPI device through the second sending channel, the third sending channel and the MIPI display interface, so as to complete the function of displaying an image on the MIPI display screen, for example.

[0046] Exemplarily, the external controller 300 may also send a second read-back instruction to the field programmable gate array chip 110. The field programmable gate array chip 110 may also be used to read back the second target data from the MIPI display interface of the external MIPI device 200 based on the second read-back instruction. Exemplarily, after receiving the second read-back instruction, the field programmable gate array chip 110 may send the first target data after packetization to the external MIPI device 200 through the first transmission channel and the third transmission channel, as well as the MIPI display interface. The first target data may also include a BTA command. After receiving the BTA command, the external MIPI device 200 performs bus steering. At this time, the field programmable gate array chip 110 has switched the second switch 130 to connect the first read channel. At this time, the field programmable gate array chip 110 can read the second target data of the external MIPI device 200. The second target data may include the register value of the external MIPI device, such as an SN code, etc.

[0047] Exemplarily, the external controller 300 and the image signal generator can be used for the production and detection of MIPI display screens, for example, by outputting image data, lighting up the MIPI display screen, and detecting its display condition through machine vision. The register value of the MIPI display screen can then be read back, and the detection result can be matched with the register value one by one, thereby achieving full traceability of the MIPI display screen.

[0048] A person skilled in the art may understand the specific implementation scheme of the above-mentioned image signal generator by reading the above description of the reading and writing device of the MIPI display interface, and will not be described in detail here for the sake of brevity.

[0049] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present invention thereto. A person of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as required by the appended claims.

[0050] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0051] It should be noted that the above embodiments illustrate the utility model rather than limit the utility model, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the existence of elements or steps not listed in the claims. The word "one" or "an" before an element does not exclude the existence of multiple such elements. The utility model can be implemented by means of hardware including several different elements and by means of appropriately programmed computers. In a unit claim that lists several devices, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

[0052] The above is only a specific implementation or description of the specific implementation of the utility model, and the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. The protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. A reading and writing device for a MIPI display interface, characterized in that: include: A field programmable gate array chip, a first switch, and a second switch; The field programmable gate array chip includes: a low-speed transmitter, a receiver, a high-speed transmitter and a controller; wherein, The output end of the low-speed transmitter is connected to the first end of the first switch; The output end of the high-speed transmitter is connected to the second end of the first switch; The first end of the second switch is connected to the third end of the first switch; The second end of the second switch is connected to the input end of the receiver; The third end of the second switch is used to connect to the MIPI display interface of the external MIPI device; The first output terminal and the second output terminal of the controller are connected to the control terminals of the first switch and the second switch respectively; Among them, the first switch is used to control its first end and its third end to form a first sending channel or control its second end and its third end to form a second sending channel under the control of the controller, and the second switch is used to control its first end and its third end to form a third sending channel or control its second end and its third end to form a first reading channel under the control of the controller.

2. The MIPI display interface reading and writing device according to claim 1, characterized in that: The low-speed transmitter has a sending buffer and a packaging component, the controller is connected to the packaging component, and the packaging component is connected to the sending buffer. The controller is used to control the packaging component to read the first target data in the sending buffer and perform packaging, and send the packaged first target data to the external MIPI device through the first sending channel in low-speed mode.

3. The MIPI display interface reading and writing device according to claim 1, characterized in that: The receiver has a receiving buffer and an unpacking component, the controller is connected to the unpacking component, the receiving buffer is connected to the unpacking component, and the controller is used to control the unpacking component to unpack the second target data read back from the external MIPI device through the first read channel by a low-speed module to obtain valid data, and cache the valid data in the receiving buffer.

4. The MIPI display interface reading and writing device according to any one of claims 1 to 3, characterized in that: The field programmable gate array chip is a ZYNQ UltraScale+ series chip.

5. The reading and writing device of the MIPI display interface as claimed in claim 4, characterized in that: The field programmable gate array chip includes a processing system part and a programmable logic part, and the processing system part and the programmable logic part are connected through a lightweight advanced extensible interface.

6. The MIPI display interface reading and writing device according to any one of claims 1 to 3, characterized in that: The high-speed transmitter is used to transmit first target data to the external MIPI device through the second transmission channel in high-speed mode, where the first target data includes image data and / or control data.

7. The MIPI display interface reading and writing device according to any one of claims 1 to 3, characterized in that: The external MIPI device is a display screen having a MIPI display interface.

8. An image signal generator, characterized in that: A reading and writing device comprising a MIPI display interface as claimed in any one of claims 1 to 7.

9. The image signal generator according to claim 8, characterized in that: The image signal generator further includes an external controller, and the external controller is connected to the field programmable gate array chip via a network port. The external controller is used to send a first sending instruction and first target data to the field programmable gate array chip, and / or send a second read-back instruction to the field programmable gate array chip; The field programmable gate array chip is specifically used to send the first target data to the external MIPI device through the second sending channel and the MIPI display interface based on the first sending instruction, and / or to read back the second target data from the MIPI display interface of the external MIPI device based on the second read back instruction.

10. The image signal generator according to claim 9, characterized in that: The external controller is a host computer.

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