PCB structure for optimizing fan-out signal quality of DDR5 particles
By adding GND return holes and optimizing signal via spacing in the DDR5 particle fan-out trace segment L3, the problem of insufficient signal quality in the DDR5 topological link is solved, and higher signal quality and lower cost are achieved.
Patent Information
- Application Number
- CN202420359956.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-26
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-02-26
AI Technical Summary
Inadequate signal quality in the DDR5 topological link leads to possible errors or losses during signal transmission, and it is difficult for the prior art to optimize signal quality without increasing device and design or processing costs.
In the DDR5 particle fan-out trace segment L3, an optimized PCB structure is adopted to reduce crosstalk between signals and by increasing the center spacing of signal vias and at least one GND return hole is present within the center spacing of 0.8 mm for each signal via. Return path.
Significantly optimized DDR5 signal quality, reduce crosstalk between signals, is suitable for higher-speed DDR5 operation without the need to increase other devices or design and processing costs.
Smart Images
Figure CN222147880U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuit boards, and specifically to a PCB structure for optimizing the quality of DDR5 particle fan-out signals. Background Art
[0002] Printed Circuit Board (PCB), also known as printed circuit board, is an important component of the physical support and signal transmission of electronic products. The traces in the PCB board serve to connect the pins of different chips.
[0003] Among the widely used DDR (Double Data Rate) particles, the latest generation of DDR5 particles has a maximum operating speed of more than 6400Mbps from mainstream particle manufacturers. Compared with the previous generation DDR4 with a maximum speed of 3200Mbps, the transmission rate of DDR5 has more than doubled. The advantage of DDR5 is that reading, writing, and copying are higher than DDR4, and this advantage increases with the increase of memory frequency. The improvement in timing has some impact, but it is not as obvious as frequency. The bandwidth of DDR5 has doubled, which can meet more IO-intensive computing needs. At present, it has a relatively large advantage in deep learning and scientific computing. The capacity of DDR5 chips in the future will be larger, which can meet the requirements for large capacity.
[0004] Currently, if Figure 1 As shown, the commonly used DDR5 topology link is generally divided into the trunk routing segment M, the breakout routing segments L0, L1, L2 and the particle fan-out routing segment L3. The impedance of the trunk routing segment M is 40 ohms, and the impedance of the breakout routing segments L0, L1, L2 and the particle fan-out routing segment L3 are all controlled at 40+ / -5 ohms. In DDR5, the power supply voltage is 1.1V. In the above DDR5 topology link, due to different controller drives, design and processing factors, sometimes the signal quality margin of the topology is insufficient, resulting in errors or loss of signals during transmission. Therefore, how to optimize the signal quality of the DDR5 topology link without increasing other devices, design or processing costs has become an urgent problem to be solved in the industry. Utility Model Content
[0005] In order to overcome the problem of insufficient signal quality margin in the DDR5 topology link in the prior art, the utility model provides a PCB structure for optimizing the fan-out signal quality of DDR5 particles.
[0006] The technical solution of the utility model is as follows:
[0007] A PCB structure for optimizing the quality of a DDR5 particle fan-out signal, applied to a particle fan-out routing segment L3 of a DDR5 topology link, includes:
[0008] PCB board;
[0009] A signal routing line is arranged on the PCB board, including a plurality of first signal routing lines and a plurality of second signal routing lines, wherein the second signal routing lines are GND signal routing lines;
[0010] Signal vias are arranged on the PCB board, including a plurality of first signal vias and a plurality of second signal vias, wherein the second signal vias are GND return holes, the first signal traces are electrically connected to the first signal vias, and the GND signal traces are electrically connected to the GND return holes;
[0011] The center distance between two adjacent first signal vias is greater than 0.8 mm, and there is at least one GND return hole within the 0.8 mm center distance of each of the first signal vias.
[0012] As an embodiment of the present invention, the center distance between two adjacent first signal vias is 1.13 mm.
[0013] As an embodiment of the present utility model, the first signal routing includes an address / data signal routing, a DQS and clock signal routing, and a VDD power signal routing, the first signal via includes an address / data signal via, a DQS and clock signal via, and a VDD power signal via, the address / data signal routing is electrically connected to the address / data signal via, the DQS and clock signal routing is electrically connected to the DQS and clock signal via, and the VDD power signal routing is electrically connected to the VDD power signal via.
[0014] As an embodiment of the present utility model, the GND return hole includes a first GND return hole and a second GND return hole, and the first GND return hole is electrically connected to the GND signal wiring.
[0015] As an embodiment of the present invention, the diameters of all the signal vias are 8-16 mils.
[0016] As an embodiment of the present invention, the diameters of all the signal vias are 6-16 mils.
[0017] As an embodiment of the present invention, the diameters of all the signal vias are 8-14 mil.
[0018] As an embodiment of the present invention, the diameters of all the signal vias are 9-16 mils.
[0019] As an embodiment of the present invention, the diameters of all the signal vias are 9-18 mils.
[0020] As an embodiment of the present invention, the diameters of all the signal vias are 7-14 mils.
[0021] Compared with the prior art, the beneficial effects of the utility model are:
[0022] The utility model provides a PCB structure for optimizing the fan-out signal quality of DDR5 particles. By optimizing the staggered punching method, the center spacing between the first signal vias is increased, and more GND return holes are added. It is ensured that there is at least one GND return hole within the 0.8mm center spacing of each first signal via, so as to achieve the effect of reducing crosstalk between signals and reducing their return paths. When DDR5 runs at a higher rate, the fan-out signal quality can be significantly optimized without adding other devices and design or processing costs. The advantage is very obvious and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 A schematic diagram of a commonly used DDR5 topology link;
[0025] Figure 2 A schematic diagram of a traditional PCB structure of a particle fan-out routing segment L3 in a commonly used DDR5 topology link;
[0026] Figure 3 This is a structural schematic diagram of a PCB structure for optimizing the fan-out signal quality of DDR5 particles in one embodiment of the utility model;
[0027] Figure 4 A comparison chart of signal quality between a DDR5 topology link using the PCB structure of the utility model and a fan-out using a traditional PCB structure;
[0028] Figure 5 This is an eye diagram of a traditional PCB structure of a particle fan-out trace segment L3 in a commonly used DDR5 topology link at a 6400Mbps operating rate;
[0029] Figure 6An eye diagram of a PCB structure for optimizing the quality of DDR5 particle fan-out signals at a running rate of 6400Mbps in one embodiment of the utility model;
[0030] Figure 7 This is a schematic diagram of the structure of a 106pin-16-bit particle in an embodiment of the utility model;
[0031] Figure 8 This is a PIN definition diagram of a 106pin-16-bit particle in an embodiment of the present invention.
[0032] In the figure,
[0033] 1. PCB board; 2. Address / data signal routing; 3. DQS and clock signal routing; 4. VDD power signal routing; 5. GND signal routing; 6. Address / data signal vias; 7. DQS and clock signal vias; 8. VDD power signal vias; 9. GND return hole; 901. First GND return hole; 902. Second GND return hole. DETAILED DESCRIPTION
[0034] In order to make the technical problems, technical solutions and beneficial effects to be solved by the utility model more clearly understood, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, it is stated that the embodiments described below are only used to explain the utility model and are not used to limit the utility model.
[0035] It should be noted that the terms "set", "connect", "fix" and the like should be understood in a broad sense, for example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected, or indirectly connected through an intermediate medium, or they can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. The indication of orientation or position relationship is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the application product is usually placed when in use, or the orientation or position relationship commonly understood by those skilled in the art, or the orientation or position relationship in which the application product is usually placed when in use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for the purpose of convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0036] Figure 2 A traditional PCB structure of a particle fan-out routing segment L3 of a commonly used DDR5 topology link is shown. The PCB structure includes a PCB board 1 and signal routing and signal vias arranged on the PCB board 1, the signal routing includes an address / data signal routing 2, a DQS and clock signal routing 3, a VDD power signal routing 4 and a GND signal routing 5, the signal vias include an address / data signal via 6, a DQS and clock signal via 7, a VDD power signal via 8 and a GND return hole 9, the address / data signal routing 2 is electrically connected to the address / data signal via 6, the DQS and clock signal routing 3 is electrically connected to the DQS and clock signal via 7, the VDD power signal routing 4 is electrically connected to the VDD power signal via 8, and the GND signal routing 5 is electrically connected to the GND return hole 9. In the above-mentioned PCB structure, various signal routings choose to fan out nearby, resulting in a center spacing of 0.8mm between adjacent signal vias, and only some signal routings can be guaranteed to have nearby GND return holes 9. The center spacing between most signal routings and adjacent GND return holes 9 is much larger than 0.8mm, which has a certain impact on the return and crosstalk of DDR5 signals, resulting in the problem of insufficient signal quality margin in the DDR5 topology link.
[0037] To this end, an embodiment of the utility model provides a PCB structure for optimizing the quality of DDR5 particle fan-out signals, which is applied to the particle fan-out routing segment L3 of the DDR5 topology link. Figure 3 The PCB structure includes a PCB board 1, signal traces and signal vias, and the signal traces and signal vias are arranged on the PCB board 1. The signal traces include a plurality of first signal traces and a plurality of second signal traces, the first signal traces include an address / data signal trace 2, a DQS and clock signal trace 3 and a VDD power signal trace 4, and the second signal trace is a GND signal trace 5. The signal vias include a plurality of first signal vias and a plurality of second signal vias, the first signal vias include an address / data signal via 6, a DQS and clock signal via 7 and a VDD power signal via 8, the address / data signal trace 2 is electrically connected to the address / data signal via 6, the DQS and clock signal trace 3 is electrically connected to the DQS and clock signal via 7, and the VDD power signal trace 4 is electrically connected to the VDD power signal via 8. The second signal via is a GND return hole 9, and the GND signal trace 5 is electrically connected to the GND return hole 9. The center distance between two adjacent first signal vias is greater than 0.8 mm, and there is at least one GND return hole 9 within the 0.8 mm center distance of each first signal via.
[0038] See also Figures 4 to 6After a large number of simulation and test experiments, the utility model increases the center distance between the first signal vias in the particle fan-out routing segment L3 and adds more GND return holes 9 to ensure that there is at least one GND return hole 9 within the 0.8mm center distance of each first signal via, which will significantly optimize the signal quality of the DDR5 topology link fanout fanout.
[0039] Compared with the traditional PCB structure, the utility model only optimizes the staggered punching method, increases the center spacing between the first signal vias, and adds more GND return holes 9, ensuring that there is at least one GND return hole 9 within the 0.8mm center spacing of each first signal via, so as to achieve the effect of reducing the crosstalk between signals and reducing their return paths. The fan-out signal quality can be significantly optimized when running at a higher rate in DDR5, without adding other devices and design or processing costs. The advantages are very obvious and have broad application prospects.
[0040] In PCB design, you only need to follow Figure 3 The interconnect routing design adjusts the routing line width of the particle fan-out routing segment L3 through impedance calculation according to different stacking layers, and controls the impedance of this segment to 40 ohms, which is universal.
[0041] In one embodiment, the center spacing between two adjacent first signal vias is 1.13mm. Compared with the traditional 0.8mm center spacing, the utility model can reduce the coupling between signals by increasing the center spacing between two adjacent first signal vias to 1.13mm, thereby reducing the possibility of crosstalk and achieving the effect of improving signal quality. At the same time, this spacing also takes into account the limitations of the processing technology and the return path of the signal. In the actual processing process, the position and size of the vias need to take into account factors such as drilling accuracy and hole wall roughness. Too large a spacing may increase the difficulty and cost of processing, while too small a spacing may not meet the requirements of signal transmission. A spacing of 1.13mm is a relatively easy to implement and effective option in terms of technology.
[0042] In one embodiment, the GND return hole 9 includes a first GND return hole 901 and a second GND return hole 902. The first GND return hole 901 is electrically connected to the GND signal routing line 5, and the second GND return hole 902 is not electrically connected to the GND signal routing line 5, and is only arranged near the first signal via to reduce the return path of the first signal routing line.
[0043] In one embodiment, the diameter of all signal vias is 8-16 mil. An appropriate via diameter can help improve signal transmission efficiency. A diameter that is too small may cause signal attenuation or blocking, while a diameter that is too large may increase unnecessary capacitance and inductance, affecting signal quality. Therefore, selecting an appropriate diameter within this range can ensure that the signal is effectively transmitted from one layer to another. At the same time, the selection of diameters within this range also takes into account processing and manufacturing costs. A via diameter that is too small may increase processing difficulty and cost, while a diameter that is too large may reduce the overall performance of the PCB. Selecting a diameter within this range can ensure performance while also taking into account manufacturing costs and processing efficiency. It should be understood that those skilled in the art can set it arbitrarily within this area according to actual conditions. For example, the diameters of all signal vias can be set to 8 mil, 10 mil, 12 mil, 14 mil or 16 mil, etc., and the utility model does not limit this.
[0044] In other embodiments, the diameter of all signal vias is 6-16 mil.
[0045] In other embodiments, the diameter of all signal vias is 8-14 mil.
[0046] In other embodiments, the diameter of all signal vias is 9-16 mil.
[0047] In other embodiments, the diameter of all signal vias is 9-18 mil.
[0048] In other embodiments, the diameter of all signal vias is 7-14 mil.
[0049] In one embodiment, the DDR5 particle adopts a 106pin-16-bit particle. The specific structure and PIN definition of the 106pin-16-bit particle are as follows: Figure 7 , Figure 8 Of course, in other embodiments, DDR5 particles may also use other types of PCB boards, and the present invention does not limit this.
[0050] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.
[0051] The above is an exemplary description of the utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the utility model patent is not limited to the above-mentioned method. As long as various improvements are made by adopting the method concept and technical solution of the utility model patent, or the concept and technical solution of the utility model patent are directly applied to other occasions without improvement, they are all within the protection scope of the utility model.
Claims
1. A PCB structure for optimizing the quality of DDR5 particle fan-out signals, applied to the particle fan-out routing segment L3 of a DDR5 topology link, characterized in that: include: PCB board; A signal routing line is arranged on the PCB board, including a plurality of first signal routing lines and a plurality of second signal routing lines, wherein the second signal routing lines are GND signal routing lines; Signal vias are arranged on the PCB board, including a plurality of first signal vias and a plurality of second signal vias, wherein the second signal vias are GND return holes, the first signal traces are electrically connected to the first signal vias, and the GND signal traces are electrically connected to the GND return holes; The center distance between two adjacent first signal vias is greater than 0.8 mm, and there is at least one GND return hole within the 0.8 mm center distance of each of the first signal vias.
2. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The center distance between two adjacent first signal vias is 1.13 mm.
3. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The first signal routing includes an address / data signal routing, a DQS and clock signal routing, and a VDD power signal routing; the first signal via includes an address / data signal via, a DQS and clock signal via, and a VDD power signal via; the address / data signal routing is electrically connected to the address / data signal via, the DQS and clock signal routing is electrically connected to the DQS and clock signal via, and the VDD power signal routing is electrically connected to the VDD power signal via.
4. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The GND return hole includes a first GND return hole and a second GND return hole, and the first GND return hole is electrically connected to the GND signal wiring.
5. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The diameter of all the signal vias is 8-16 mil.
6. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The diameter of all the signal vias is 6-16 mil.
7. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The diameter of all the signal vias is 8-14 mil.
8. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The diameter of all the signal vias is 9-16 mil.
9. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The diameter of all the signal vias is 9-18 mil.
10. The PCB structure for optimizing the fan-out signal quality of DDR5 particles according to claim 1, characterized in that: The diameter of all the signal vias is 7-14 mil.