PCB structure for optimizing fan-out signal quality of DDR5 golden finger
By adding backflow vias and adjusting the serial resistor placement position in the PCB structure of the DDR5 RDIMM topology link, the problem of insufficient signal quality of the DDR5 RDIMM topology link is solved, and the signal quality of the DDR5 RDIMM fan-out is optimized. It is suitable for the problem of insufficient signal quality of DDR5 RDIMM fan-out, and improves the signal quality of DDR5 RDIMM fan-out.
Patent Information
- Application Number
- CN202420349295.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-26
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-02-26
AI Technical Summary
Inadequate signal quality in the DDR5 RDIMM topology link leads to possible errors or losses during signal transmission, and it is difficult for the prior art to optimize signal quality without increasing device and design or processing costs.
Design a PCB structure that optimizes the signal quality of DDR5 gold finger fanout, by adding more reflux through holes in the trace segment L0/L1, and ensuring that at least one GND exists within the center spacing of 0.65-1mm of each signal via hole. Reflow hole, adjust the serial resistor placement position to reduce crosstalk and return path between signals.
Signal quality of the DDR5 RDIMM fan-out is significantly optimized, reducing crosstalk and return paths between signals, improving signal quality at high rates, and no additional devices and design or processing costs are required.
Smart Images
Figure CN222147892U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuit boards, and in particular to a PCB structure for optimizing the quality of DDR5 gold finger fan-out signals. Background Art
[0002] Printed Circuit Board (PCB), also known as printed circuit board, is an important component of the physical support and signal transmission of electronic products. The traces in the PCB board serve to connect the pins of different chips.
[0003] In today's computer world, memory is a vital component that has a direct impact on the performance of the system. With the continuous advancement of technology, DDR5 memory has begun to emerge. Compared with DDR4 memory, DDR5 memory has higher bandwidth, higher frequency, lower energy consumption, and larger capacity, which is very beneficial for applications that need to process large amounts of data.
[0004] At present, the data signal on DDR5 RDIMM has simple and commonly used topology links, such as Figure 1 As shown. Figure 1 In the topology link, the impedance of the routing segments L0, L1, L2, and L3 are all controlled at 40 ohms. In DDR5, the power supply voltage is 1.1V. In the above topology link, due to different controller drives, and RDIMMs all use multi-RANK applications, coupled with factors such as design and processing, sometimes the signal quality margin of the topology link is insufficient, resulting in errors or loss of signals during transmission. Therefore, how to optimize the signal quality of the topology link without increasing other devices, design or processing costs has become an urgent problem to be solved in the industry. Utility Model Content
[0005] In order to overcome the problem of insufficient signal quality margin in the DDR5 RDIMM topology link in the prior art, the utility model provides a PCB structure for optimizing the quality of DDR5 gold finger fan-out signals.
[0006] The technical solution of the utility model is as follows:
[0007] A PCB structure for optimizing the quality of a DDR5 gold finger fan-out signal, applied to a routing segment L0 / L1 of a DDR5 RDIMM topology link, comprising:
[0008] A PCB board, comprising a top layer, a bottom layer, and an inner layer located between the top layer and the bottom layer;
[0009] A gold finger assembly is arranged at the end of the PCB board and located at the top layer and / or the bottom layer, and includes a plurality of ground gold fingers and a plurality of signal gold fingers that are isolated from each other;
[0010] Routings, arranged on the PCB board, including a plurality of ground routings electrically connected to the corresponding grounding gold fingers and a plurality of signal routings electrically connected to the corresponding signal gold fingers;
[0011] Vias are arranged on the PCB board, including a plurality of first return ground vias electrically connected to the corresponding ground gold fingers, a plurality of second return ground vias and a plurality of signal vias electrically connected to the corresponding signal gold fingers;
[0012] There is at least one second return ground via within a 0.65-1 mm center distance of each of the signal vias.
[0013] As an embodiment of the present invention, the first return ground via is arranged adjacent to the grounding gold finger.
[0014] As an embodiment of the present utility model, a plurality of the first return ground vias form two rows of first return ground vias, the two rows of the first return ground vias are arranged between a plurality of the signal vias and a plurality of the grounding gold fingers, and a row of the first return ground vias close to a plurality of the grounding gold fingers is electrically connected to the corresponding grounding gold fingers.
[0015] As an embodiment of the present utility model, the signal gold finger includes an address / data signal gold finger and a DQS signal gold finger, the signal routing includes an address / data signal routing and a DQS signal routing, the signal via includes an address / data signal via and a DQS signal via, the two ends of the address / data signal routing are respectively electrically connected to the corresponding address / data signal gold finger and the address / data signal via, and the two ends of the DQS signal routing are respectively electrically connected to the corresponding DQS signal gold finger and the DQS signal via.
[0016] As an embodiment of the present utility model, a first resistor is connected in series on the address / data signal routing line, and the first resistor is placed horizontally. A second resistor is connected in series on the DQS signal routing line, and the second resistor is placed vertically.
[0017] As an embodiment of the present invention, the diameters of all the first return ground vias, the second return ground vias and the signal vias are 8-16 mils.
[0018] As an embodiment of the present invention, the diameters of all the first return ground vias, the second return ground vias and the signal vias are 8-14 mils.
[0019] As an embodiment of the present invention, the diameters of all the first return ground vias, the second return ground vias and the signal vias are 6-16 mils.
[0020] As an embodiment of the present invention, the diameters of all the first return ground vias, the second return ground vias and the signal vias are 6-14 mils.
[0021] As an embodiment of the present utility model, the PCB board is a 288pin-DDR5 RDIMM PCB board.
[0022] Compared with the prior art, the beneficial effects of the utility model are:
[0023] The utility model provides a PCB structure for optimizing the quality of DDR5 gold finger fan-out signals. By adjusting the placement of the string resistor and optimizing the punching method, more return ground vias are added to ensure that at least one GND return hole exists within the 0.65-1mm center spacing of each signal via, so as to achieve the effect of reducing the crosstalk between signals and reducing the return path thereof. The fan-out signal quality can be significantly optimized when DDR5 runs at a higher rate, without adding other devices and design or processing costs, and the advantages are very obvious, with broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 A schematic diagram of a commonly used DDR5 RDIMM topology link;
[0026] Figure 2 A partial front view of a conventional PCB structure of the routing segments L0 / L1 in a commonly used DDR5 RDIMM topology link;
[0027] Figure 3 A partial schematic diagram of the back side of a traditional PCB structure of the routing segment L0 / L1 in a commonly used DDR5 RDIMM topology link;
[0028] Figure 4 It is a partial front schematic diagram of a PCB structure for optimizing the quality of DDR5 gold finger fan-out signals in one embodiment of the utility model;
[0029] Figure 5It is a partial schematic diagram of the back side of a PCB structure for optimizing the quality of DDR5 gold finger fan-out signals in one embodiment of the utility model;
[0030] Figure 6 A signal quality comparison diagram of a DDR5 RDIMM topology link using the PCB structure of the utility model and a fan-out using a traditional PCB structure;
[0031] Figure 7 This is an eye diagram of a traditional PCB structure of the Breakout trace segment L3 in a commonly used DDR5 RDIMM topology link at a 6400Mbps operating rate;
[0032] Figure 8 An eye diagram of a PCB structure for optimizing the quality of DDR5 particle fan-out signals at a running rate of 6400Mbps in one embodiment of the utility model;
[0033] Fig. 9 This is a front schematic diagram of a 288pin-DDR5 RDIMM PCB board in an embodiment of the utility model;
[0034] Fig.10 This is a schematic diagram of the back side of a 288pin-DDR5 RDIMM PCB board in one embodiment of the utility model;
[0035] Fig.11 It is a cross-sectional view of a 288pin-DDR5 RDIMM PCB board in one embodiment of the utility model;
[0036] Fig.12 This is a PIN definition diagram of a 288-pin-DDR5 RDIMM PCB board in one embodiment of the utility model.
[0037] In the figure,
[0038] 1. PCB board; 101. Top layer; 102. Bottom layer; 2. Ground gold finger; 3. Address / data signal gold finger; 4. DQS signal gold finger; 5. Ground trace; 6. Address / data signal trace; 7. DQS signal trace; 8. First return ground via; 9. Address / data signal via; 10. DQS signal via; 11. Second return ground via; 12. First resistor; 13. Second resistor. DETAILED DESCRIPTION
[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by the utility model more clearly understood, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, it is stated that the embodiments described below are only used to explain the utility model and are not used to limit the utility model.
[0040] It should be noted that the terms "set", "connect", "fix" and the like should be understood in a broad sense, for example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected, or indirectly connected through an intermediate medium, or they can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. The indication of orientation or position relationship is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the application product is usually placed when in use, or the orientation or position relationship commonly understood by those skilled in the art, or the orientation or position relationship in which the application product is usually placed when in use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for the purpose of convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0041] Figure 2 , Figure 3A conventional PCB structure of a routing segment L0 / L1 in a commonly used DDR5 RDIMM topology link is shown. The PCB structure includes a PCB board 1, a gold finger assembly, routing and vias. The PCB board 1 includes a top layer 101, a bottom layer 102 and an inner layer between the top layer 101 and the bottom layer 102. The gold finger assembly is arranged at the end of the PCB board 1 and is located at the top layer 101 and the bottom layer 102, and includes a plurality of grounding gold fingers 2, a plurality of address / data signal gold fingers 3 and a plurality of DQS signal gold fingers 4 that are isolated from each other. The routing is arranged on the PCB board 1, and includes a plurality of ground routing lines 5 electrically connected to the corresponding grounding gold fingers 2, a plurality of address / data signal routing lines 6 electrically connected to the corresponding address / data signal gold fingers 3 and a plurality of DQS signal routing lines 7 electrically connected to the corresponding DQS signal gold fingers 4. The vias are arranged on the PCB board 1, and include a plurality of first return ground vias 8 electrically connected to the corresponding ground gold fingers 2, a plurality of address / data signal vias 9 electrically connected to the corresponding address / data signal gold fingers 3, a plurality of DQS signal vias 10 electrically connected to the corresponding DQS signal gold fingers 4, and a plurality of second return ground vias 11 arranged adjacent to the DQS signal vias 10. In addition, a first resistor 12 is connected in series to the address / data signal wiring 6, a second resistor 13 is connected in series to the DQS signal wiring 7, and the first resistor 12 and the second resistor 13 are both arranged vertically.
[0042] In the above-mentioned PCB structure, only the DQS signal routing 7 has a nearby return ground via, while the address / data signal routing 6 is far away from the adjacent return ground via, and the first resistor 12 and the second resistor 13 are both placed vertically, resulting in a small center distance between adjacent signal vias, which has a certain impact on the return and crosstalk of the DDR5 data / address signal, resulting in the problem of insufficient signal quality margin in the DDR5 RDIMM topology link.
[0043] To this end, this embodiment provides a PCB structure for optimizing the quality of DDR5 gold finger fan-out signals, which is applied to the routing segment L0 / L1 of the DDR5 RDIMM topology link. Figures 4 to 5, the PCB structure includes a PCB board 1, a gold finger assembly, a trace and a via. The PCB board 1 includes a top layer 101, a bottom layer 102 and an inner layer between the top layer 101 and the bottom layer 102. The gold finger assembly is arranged at the end of the PCB board 1 and is located at the top layer 101 and the bottom layer 102, and includes a plurality of ground gold fingers 2 and a plurality of signal gold fingers isolated from each other. Of course, in other embodiments, the gold finger assembly can also be arranged only on the top layer 101 or the bottom layer 102 of the PCB board 1, and the utility model does not limit this. The trace is arranged on the PCB board 1, and includes a plurality of ground traces 5 electrically connected to the corresponding ground gold fingers 2 and a plurality of signal traces electrically connected to the corresponding signal gold fingers. The via is arranged on the PCB board 1, and includes a plurality of first return ground vias 8 electrically connected to the corresponding ground gold fingers 2, a plurality of second return ground vias 11 and a plurality of signal vias electrically connected to the corresponding signal gold fingers. In this embodiment, the signal gold finger includes an address / data signal gold finger 3 and a DQS signal gold finger 4, the signal routing includes an address / data signal routing 6 and a DQS signal routing 7, the signal via includes an address / data signal via 9 and a DQS signal via 10, the two ends of the address / data signal routing 6 are respectively electrically connected to the corresponding address / data signal gold finger 3 and the address / data signal via 9, and the two ends of the DQS signal routing 7 are respectively electrically connected to the corresponding DQS signal gold finger 4 and the DQS signal via 10. Among them, there is at least one second return ground via 11 within the 0.65-1mm center spacing of each signal via, and the center spacing can be adjusted autonomously between 0.65-1mm according to the actual product layout.
[0044] See also Figures 6 to 8 After a large number of simulation and test experiments, the utility model adds more return ground vias in the routing segment L0 / L1 to ensure that there is at least one return ground via within the 0.65-1mm center spacing of each signal via. After this optimization, the signal quality of the DDR5 RDIMM topology link fanout fanout is significantly optimized.
[0045] Compared with the traditional PCB structure, the utility model optimizes the punching method, adds more return ground vias, and ensures that there is at least one GND return hole within the 0.65-1mm center spacing of each signal via, so as to achieve the effect of reducing crosstalk between signals and reducing their return paths; running at a higher rate of DDR5 can significantly optimize the fan-out signal quality without adding other devices and design or processing costs. The advantage is very obvious and has broad application prospects.
[0046] In PCB design, you only need to follow Figure 4 , Figure 5The interconnection routing design adjusts the routing line width of the routing segment L0 / L1 through impedance calculation according to different stacking layers, and controls the impedance of this routing segment to 40 ohms, which is universal.
[0047] In one embodiment, the first return ground via 8 is disposed adjacent to the grounding golden finger 2 , which can effectively improve and reduce the return path and crosstalk between the DIMM signal and the main control board signal.
[0048] In one embodiment, a plurality of first return ground vias 8 form two rows of first return ground vias 8, the two rows of first return ground vias 8 are arranged between a plurality of signal vias and a plurality of grounding gold fingers 2, and a row of first return ground vias 8 close to a plurality of grounding gold fingers 2 is electrically connected to the corresponding grounding gold fingers 2. The above arrangement can effectively improve and reduce the return path and crosstalk of the connection between the DIMM signal and the main control board signal.
[0049] In one embodiment, a first resistor 12 is connected in series to the address / data signal line 6, and the first resistor 12 is placed horizontally. A second resistor 13 is connected in series to the DQS signal line 7, and the second resistor 13 is placed vertically. By adjusting the placement of the series resistor, that is, placing the first resistor 12 horizontally, the spacing between adjacent address / data signal vias 9 can be increased to reduce the crosstalk between the signals. After this optimization, the signal quality of the fanout fanout of the DDR5 RDIMM topology link will be further optimized.
[0050] In one embodiment, the diameters of all first return ground vias 8, second return ground vias 11 and signal vias are 8-16 mil. Appropriate via diameters can help improve signal transmission efficiency. Too small a diameter may cause signal attenuation or blocking, while too large a diameter may increase unnecessary capacitance and inductance, affecting signal quality. Therefore, selecting an appropriate diameter within this range can ensure that the signal is effectively transmitted from one layer to another. At the same time, the selection of diameters within this range also takes into account processing and manufacturing costs. Too small a via diameter may increase processing difficulty and cost, while too large a diameter may reduce the overall performance of the PCB. Selecting a diameter within this range can ensure performance while also taking into account manufacturing costs and processing efficiency. It should be understood that those skilled in the art can set it arbitrarily within this area according to actual conditions. For example, the diameters of all first return ground vias 8, second return ground vias 11 and signal vias are all set to 8 mil, 10 mil, 12 mil, 14 mil or 16 mil, and the utility model does not limit this.
[0051] In one embodiment, the diameters of all first return ground vias, second return ground vias, and signal vias are 8-14 mils.
[0052] In one embodiment, the diameters of all the first return ground vias, the second return ground vias, and the signal vias are 6-16 mils.
[0053] In one embodiment, the diameters of all first return ground vias, second return ground vias, and signal vias are 6-14 mils.
[0054] In one embodiment, the PCB board 1 is a 288-pin-DDR5 RDIMM PCB board. The specific structure and PIN definition of the 288-pin-DDR5 RDIMM PCB board are as follows: Figure 9-12 Of course, in other embodiments, the PCB board 1 may also be other types of PCB boards, and the present invention does not limit this.
[0055] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.
[0056] The above is an exemplary description of the utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the utility model patent is not limited to the above-mentioned method. As long as various improvements are made by adopting the method concept and technical solution of the utility model patent, or the concept and technical solution of the utility model patent are directly applied to other occasions without improvement, they are all within the protection scope of the utility model.
Claims
1. A PCB structure for optimizing the quality of DDR5 gold finger fan-out signals, applied to the routing segment L0 / L1 of a DDR5 RDIMM topology link, characterized in that: include: A PCB board, comprising a top layer, a bottom layer, and an inner layer located between the top layer and the bottom layer; A gold finger assembly is arranged at the end of the PCB board and located at the top layer and / or the bottom layer, and includes a plurality of ground gold fingers and a plurality of signal gold fingers that are isolated from each other; Routings, arranged on the PCB board, including a plurality of ground routings electrically connected to the corresponding grounding gold fingers and a plurality of signal routings electrically connected to the corresponding signal gold fingers; Vias are arranged on the PCB board, including a plurality of first return ground vias electrically connected to the corresponding ground gold fingers, a plurality of second return ground vias and a plurality of signal vias electrically connected to the corresponding signal gold fingers; There is at least one second return ground via within a 0.65-1 mm center distance of each of the signal vias.
2. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The first return ground via is arranged adjacent to the grounding gold finger.
3. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The first return ground vias form two rows of first return ground vias, the two rows of first return ground vias are arranged between the signal vias and the grounding gold fingers, and a row of the first return ground vias close to the grounding gold fingers is electrically connected to the corresponding grounding gold fingers.
4. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The signal gold fingers include address / data signal gold fingers and DQS signal gold fingers, the signal routing includes address / data signal routing and DQS signal routing, the signal vias include address / data signal vias and DQS signal vias, the two ends of the address / data signal routing are electrically connected to the corresponding address / data signal gold fingers and the address / data signal vias, and the two ends of the DQS signal routing are electrically connected to the corresponding DQS signal gold fingers and the DQS signal vias.
5. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 4, characterized in that: A first resistor is connected in series on the address / data signal routing line, and the first resistor is placed horizontally. A second resistor is connected in series on the DQS signal routing line, and the second resistor is placed vertically.
6. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The diameters of all the first return ground vias, the second return ground vias and the signal vias are 8-16 mils.
7. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The diameters of all the first return ground vias, the second return ground vias and the signal vias are 8-14 mils.
8. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The diameters of all the first return ground vias, the second return ground vias and the signal vias are 6-16 mils.
9. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The diameters of all the first return ground vias, the second return ground vias and the signal vias are 6-14 mils.
10. The PCB structure for optimizing the quality of DDR5 gold finger fan-out signals according to claim 1, characterized in that: The PCB board is a 288pin-DDR5 RDIMM PCB board.