Power semiconductor device

Abstract

The utility model relates to a power semiconductor device. Comprising a substrate of a first conductive type, a first well region of the first conductive type implanted on the back surface of the substrate, and a second well region of a second conductive type implanted on the front surface of the substrate. The second well region is located on the front face of the substrate and provided with a first doped region and a second doped region of a second conduction type, and a buried region of the first conduction type extends from the first doped region to the interior of the substrate on the lower side of the second well region. The first well region is provided with a third doped region of the first conductivity type and a fourth doped region of the second conductivity type, and a drift region of the second conductivity type extending from the fourth doped region to the substrate contacting the upper side of the first well region. The buried region and the third doped region are partially overlapped, and under the condition that a node between the first doped region and the buried region is reversely broken down, a vertical current path between the buried region and the third doped region triggers the bipolar transistor between the second doped region and the substrate and the bipolar transistor between the second doped region and the drift region to be conducted.

Description

Technical Field

[0001] The utility model mainly relates to the technical field of semiconductor devices, and more specifically, to a solution for ensuring the safety of a memory interface and a power semiconductor device. Background Art

[0002] In electronic products, interface technology is usually used in microprocessor structure, instruction system, memory interface, interrupt technology, input / output interface, programmable interface chip, human-computer interaction and bus technology. Among the different application directions of hardware interface technology, memory interface is a typical application that requires a large data carrying capacity. As the memory interface faces high bandwidth and high transmission rate, complex communication protocols are integrated with hardware interfaces. The most obvious feature is that the number of interfaces is increasing dramatically, the layout density of interfaces is increasing, and interfaces are more susceptible to interference from the surrounding environment.

[0003] One of the concerns about the memory interface is that with the high input and output of data, the hardware interface runs under the current mainstream low power supply voltage. The voltage coupled from the interface part and the voltage from unintentional contact or touch will interfere with the normal input and output of data at the hardware interface, and even damage the interface in serious cases. In situations such as NVME, PCIE, etc. that use a large number of data lines, clock lines, address lines and other types of buses, a slight external unexpected voltage at the interface can easily cause input and output information errors or even burn the memory interface. This is one of the serious problems that need to be solved urgently. Utility Model Content

[0004] The present application relates to a power semiconductor device, characterized in that it comprises:

[0005] A substrate of a first conductivity type, a first well region of the first conductivity type implanted on the back side of the substrate, and a second well region of the second conductivity type implanted on the front side of the substrate;

[0006] First and second doped regions of the second conductivity type located on the front side of the substrate in the second well region, and a buried region of the first conductivity type extending from the first doped region to the inside of the substrate at the lower side of the second well region;

[0007] A third doping region of the first conductivity type and a fourth doping region of the second conductivity type located on the back side of the substrate in the first well region, and a drift region of the second conductivity type extending from the fourth doping region to contact the substrate on the upper side of the first well region;

[0008] The buried region and the third doped region at least partially overlap in a direction perpendicular to the substrate, and under the condition that the node between the first doped region and the buried region is reversely broken down, a bipolar transistor between the second doped region, the substrate, and the drift region is triggered to turn on by the vertical current path between the buried region and the third doped region.

[0009] The power semiconductor device described above, wherein: a top metal layer insulated from the substrate by a top dielectric layer is provided on the front side of the substrate, and the top metal layer simultaneously contacts the first doped region and the second doped region through a through hole penetrating the top dielectric layer;

[0010] A bottom metal layer insulated from the substrate by a bottom dielectric layer is disposed on the back side of the substrate. The bottom metal layer contacts the third and fourth doped regions simultaneously through a through hole penetrating the bottom dielectric layer.

[0011] The above-mentioned power semiconductor device, wherein: the interface (I / O) of the memory for transmitting data is connected to the top metal layer, and the bottom metal layer is connected to a reference potential (such as a reference ground GND); if the actual voltage loaded on the interface exceeds a preset threshold, a current discharge path is generated between the actual voltage and the reference potential through the bipolar transistor that is triggered to turn on.

[0012] The above-mentioned power semiconductor device, wherein further comprises:

[0013] A floating island region of the first conductivity type located on the front side of the substrate in the second well region, and in a direction perpendicular to the substrate, the floating island region is offset from the third and fourth doped regions and the drift region without overlapping;

[0014] When the bipolar transistor between the second doped region, the substrate and the drift region is triggered to turn on, the current under the on condition triggers another bipolar transistor between the floating island region, the second well region and the substrate to be further turned on.

[0015] The above-mentioned power semiconductor device, wherein, further comprises:

[0016] A floating island region of the first conductivity type located on the front side of the substrate in the second well region, and a body region of the second conductivity type adjacent to the floating island region;

[0017] A heavily doped region adjacent to the buried region and the first doped region and having a doping concentration exceeding that of the first doped region;

[0018] A trench extending from the heavily doped region to the body region is opened in the second well region on the front side of the substrate, an isolation layer such as an oxide layer is formed on the inner wall of the trench, and the interior of the trench is filled with a conductive material that couples the heavily doped region to the body region, and the heavily doped region and the conductive material are both covered by an insulating layer.

[0019] The above-mentioned power semiconductor device, wherein: in the direction perpendicular to the substrate, the floating island region is offset from the third doping region, the fourth doping region and the drift region without overlapping, and the body region is offset from the third doping region, the fourth doping region and the drift region without overlapping.

[0020] The above-mentioned power semiconductor device, wherein: when the node between the first doped region and the buried region reaches the condition of reverse breakdown but fails to break down, the control diode between the floating island region and the body region guides the node between the heavily doped region and the buried region to break through, thereby triggering a bipolar transistor between the second doped region, the substrate, and the drift region to turn on (for example, the first bipolar transistor).

[0021] The power semiconductor device described above, wherein: a top metal layer insulated from the substrate by a top dielectric layer is provided on the front side of the substrate, and the top metal layer simultaneously contacts the first doped region, the second doped region and the floating island region through a through hole penetrating the top dielectric layer;

[0022] A bottom metal layer insulated from the substrate by a bottom dielectric layer is disposed on the back side of the substrate. The bottom metal layer contacts the third doping region and the fourth doping region simultaneously through a through hole penetrating the bottom dielectric layer.

[0023] The above-mentioned power semiconductor device, wherein: when a bipolar transistor between the second doped region, the substrate, and the drift region is triggered to turn on, the current under its on condition triggers another bipolar transistor (for example, the second bipolar transistor) between the floating island region, the second well region, and the substrate to be further turned on.

[0024] In the above power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0025] The present application also relates to a method for ensuring the security of a memory interface, characterized in that a power semiconductor device is used to protect the security of a memory interface (I / O) during data communication:

[0026] The power semiconductor device comprises:

[0027] A substrate of a first conductivity type, a first well region of the first conductivity type implanted on the back side of the substrate, and a second well region of the second conductivity type implanted on the front side of the substrate;

[0028] First and second doped regions of the second conductivity type located on the front side of the substrate in the second well region, and a buried region of the first conductivity type extending from the first doped region to the inside of the substrate at the lower side of the second well region;

[0029] A third doping region of the first conductivity type and a fourth doping region of the second conductivity type located on the back side of the substrate in the first well region, and a drift region of the second conductivity type extending from the fourth doping region to contact the substrate on the upper side of the first well region;

[0030] The buried region and the third doped region at least partially overlap in a direction perpendicular to the substrate, and under the condition that a node between the first doped region and the buried region is reversely broken down, a bipolar transistor between the second doped region, the substrate and the drift region is triggered to turn on by a vertical current path between the buried region and the third doped region;

[0031] The method includes: coupling the interface to the first and second doping regions simultaneously, coupling the third and fourth doping regions to a reference potential (such as a reference ground potential GND) simultaneously, and if the actual voltage loaded on the interface exceeds a preset threshold, a current discharge path is generated between the actual voltage and the reference potential through a bipolar transistor that is triggered to turn on.

[0032] The above method, wherein: a top metal layer insulated from the substrate by a top dielectric layer is provided on the front side of the substrate, and the top metal layer contacts the first doped region and the second doped region simultaneously through a through hole penetrating the top dielectric layer;

[0033] A bottom metal layer insulated from the substrate by a bottom dielectric layer is disposed on the back side of the substrate. The bottom metal layer contacts the third doping region and the fourth doping region simultaneously through a through hole penetrating the bottom dielectric layer.

[0034] The above method, wherein: an interface (I / O) for transmitting data of a memory such as an SSD is connected to the top metal layer, and the bottom metal layer is connected to the reference potential. For example: if the actual voltage loaded on the interface exceeds a preset threshold, a current discharge path is generated between the actual voltage and the reference potential through a bipolar transistor that is triggered to turn on.

[0035] The above method further comprises:

[0036] A floating island region of the first conductivity type located on the front side of the substrate in the second well region, and in a direction perpendicular to the substrate, the floating island region is offset from the third and fourth doped regions and the drift region without overlapping;

[0037] When the bipolar transistor between the second doped region, the substrate and the drift region is triggered to turn on, the current under the on condition triggers another bipolar transistor between the floating island region, the second well region and the substrate to be further turned on.

[0038] The above method further comprises:

[0039] A floating island region of the first conductivity type located on the front side of the substrate in the second well region, and a body region of the second conductivity type adjacent to the floating island region;

[0040] A heavily doped region adjacent to the first doped region and the buried region and having a doping concentration exceeding that of the first doped region;

[0041] In the second well region, a trench extending from the heavily doped region to the body region is opened on the front side of the substrate, an oxide layer is formed on the inner wall of the trench, and the interior of the trench is filled with a conductive material that couples the heavily doped region to the body region, and the heavily doped region and the conductive material are both covered by an insulating layer.

[0042] The above method, wherein: in a direction perpendicular to the substrate, the floating island region is offset from the third doping region, the fourth doping region and the drift region without overlapping, and the body region is offset from the third and fourth doping regions and the drift region without overlapping.

[0043] The above method, wherein: when the node between the first doped region and the buried region reaches the condition of reverse breakdown but fails to break down, the control diode between the floating island region and the body region guides the node between the heavily doped region and the buried region to break through, thereby triggering a bipolar transistor between the second doped region, the substrate, and the drift region to turn on.

[0044] The above method, wherein: a top metal layer insulated from the substrate by a top dielectric layer is provided on the front side of the substrate, and the top metal layer simultaneously contacts the first doped region, the second doped region, and the floating island region through a through hole penetrating the top dielectric layer; a bottom metal layer insulated from the substrate by a bottom dielectric layer is provided on the back side of the substrate, and the bottom metal layer simultaneously contacts the third doped region and the fourth doped region through a through hole penetrating the bottom dielectric layer.

[0045] In the above method, when a bipolar transistor between the second doped region, the substrate and the drift region is triggered to turn on, the current under its on condition triggers another bipolar transistor between the floating island region, the second well region and the substrate to be further turned on.

[0046] In the above method, the first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type.

[0047] The present application also relates to a power semiconductor device, characterized in that it comprises:

[0048] A P conductive type substrate, a P conductive type first well region implanted on the back side of the substrate, and an N conductive type second well region implanted on the front side of the substrate;

[0049] First and second N conductive type doped regions located on the front side of the substrate in the second well region, and a P conductive type buried region extending from the first doped region to the inside of the substrate at the lower side of the second well region;

[0050] A third doping region of P conductivity type and a fourth doping region of N conductivity type located on the back side of the substrate in the first well region, and an N conductivity type drift region extending from the fourth doping region to contact the substrate on the upper side of the first well region;

[0051] The buried region and the third doped region at least partially overlap in a direction perpendicular to the substrate, and under the condition that the node between the first doped region and the buried region is reversely broken down, a bipolar transistor between the second doped region, the substrate, and the drift region is triggered to turn on by the vertical current path between the buried region and the third doped region.

[0052] One of the advantages of this application is that for memories with high data input and output, even if there is a high probability of interference voltage coupled or accidentally contacted or touched on the hardware interface, since the semiconductor power device can generate a discharge path by triggering the bipolar transistor to turn on when facing such interference voltage, the disturbance of the interference voltage on the hardware interface will be eliminated in a short time. For example, it can be smoothed within the symbol period of a very small amount of data communication. Under external unexpected interference voltage, it can also ensure that the I / O information is less wrong and prevent the memory interface from being damaged.

[0053] The second advantage of the present application is that the vertical current path provided inside the semiconductor power device for triggering the discharge event can ensure the fastest response speed of the release of the external interference voltage applied to the storage interface. Moreover, the layout structure of the vertical current path for triggering the discharge event avoids the negative impact of various parasitic devices inside the semiconductor power device on the vertical current path related to current bifurcation and current start-up hysteresis to the greatest extent, so the release of the external interference voltage at the interface almost reaches a transient response, and the loss rate of the code element at the interface caused by the interference is extremely low.

[0054] The third advantage of the present application is that a reverse breakdown sub-node path of a heavily doped region controlled by the invention is combined with a bipolar transistor. If the reverse breakdown sub-node of the heavily doped region reaches the reverse breakdown condition, it is equivalent to using the sub-node to activate the combined bipolar transistor in advance, thereby promoting the occurrence of positive feedback of the bipolar transistor. The entire semiconductor power device can still respond quickly and be sensitive to interference voltage when the main node does not reversely break down or breaks down with hysteresis. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0056] Figure 1 It shows implanting a first well region at the back side of the substrate and implanting a second well region at the front side of the substrate.

[0057] Figure 2 In addition to the voltage that represents the data level, there is also an interference voltage at the memory interface.

[0058] Figure 3 It is an alternative paradigm for integrating power semiconductor devices and memory into the same die.

[0059] Figure 4 A set of bipolar transistors is used to provide a discharge path for the interference voltage at the interface.

[0060] Figure 5 The secondary node is triggered when the main node does not have reverse breakdown or delayed breakdown.

[0061] Figure 6 It is a three-dimensional representation of a power semiconductor device with integrated main and secondary nodes. DETAILED DESCRIPTION

[0062] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0063] See also Figure 1Compared with other electronic devices, a feature of memory is that the amount of data in and out is extremely large, so the hardware interface (I / O) of the memory itself usually needs to bear high-frequency voltage shocks. Usually, the applied voltage of the memory interface fluctuates only within the range of high and low levels that can be tolerated, and the memory interface will not be damaged in general. For example, the high level is a high potential that represents a data code element, and the low level is another low potential that represents the opposite code element of the data. However, there are various unexpected situations in the applied voltage of the memory interface: the adjacent wires of the direct-connected wires directly connected to the memory interface will couple the interference voltage to the memory interface, the creepage voltage of other electronic components around the memory will accidentally creep to some interfaces of the memory, the interference signal in the working environment of the memory is applied to the port, such as arc signals, and the interference source caused by accidentally contacting or touching the memory interface. Outside the voltage range that the interface can tolerate, the interference voltage coupled or the interference voltage accidentally contacted or touched will destroy the data and damage the interface in most cases.

[0064] See also Figure 1 Taking NOR Flash as an example, its I / O ports mainly include bus ports such as address, instruction and data, enable port and latch port, status (ready / busy) port, etc. NAND Flash also has its own ports compared to the NOR Flash mentioned above. For example, SPI NAND mainly has chip select signal port, master output slave input port, master input slave output port, and clock port. It can be seen that the number of ports, port usage and definition of different types of memory are different. The interference voltage generated by coupling or the interference voltage generated by unintentional contact or touch will be applied to any type of port of the flash memory.

[0065] See also Figure 1 , storage devices other than SSD such as SRAM and DRAM. Taking synchronous dynamic random access memory as an example, system clock port, clock enable port, chip select port, column strobe port, row strobe port or data mask port, write enable port, address bus port, data bus port, bank address port, etc. Memory has much more ports than flash memory. This is because the communication protocol is more complex and requires more ports. More ports but using a smaller area of ​​space is the mainstream trend of current memory. It is easy to understand that more ports squeezed into a smaller area will increase the density of ports, so the creepage and external signal interference at the port and the interference source coupled to the port will tend to be serious. The ports of communication protocols such as NVME and PCIE are more complex, so when using a large number of data lines and address lines and other buses, avoiding the I / O input and output information errors caused by the external unexpected voltage applied to the I / O interface, or even damaging the I / O interface, is one of the problems that need to be solved.

[0066] See also Figure 1 In an optional embodiment, the preparation of the power semiconductor device is based on a wafer process, for example, the power semiconductor device is prepared on a substrate P-SUB including a first conductivity type. The first conductivity type is assumed to be a P-type semiconductor or a P conductivity type, the first and second conductivity types are relative or opposite, and the second conductivity type is assumed to be an N-type semiconductor or an N conductivity type. The first and second conductivity types can also be swapped with each other, the first conductivity type is assumed to be an N-type semiconductor or an N conductivity type, the first and second conductivity types are relative or opposite, and the second conductivity type is assumed to be a P-type semiconductor or a P conductivity type. The aforementioned relationship between the first and second conductivity types applies to the context of the present application.

[0067] See also Figure 1 In an optional embodiment, a first well region of the first conductivity type is implanted on the back side of the substrate P-SUB and the first well region can be represented by P-WELL, and the implanted dopant can be based on a P-type semiconductor material. The back side implantation can adopt a conventional ion implantation process, and it can be seen that the present application can be implemented based on the current semiconductor process.

[0068] See also Figure 1 In an optional embodiment, a second well region of a second conductivity type is implanted on the front side of the substrate P-SUB and the second well region can be represented by N-WELL, and the implanted dopant can be based on an N-type semiconductor material. The front side implantation can adopt a conventional ion implantation process, and it can be seen that the present application can be implemented based on the current semiconductor process.

[0069] See also Figure 1 In an optional embodiment, due to the first well region of the first conductivity type implanted on the back side of the substrate P-SUB and the second well region of the second conductivity type implanted on the front side of the substrate P-SUB, the remaining portion of the substrate P-SUB is between the first well region P-WELL and the second well region N-WELL, similar to a sandwich structure.

[0070] See also Figure 1 In an optional embodiment, the power semiconductor device includes a first doping region 10 and a second doping region 12 of the second conductivity type located on the front side of the substrate P-SUB in the second well region N-WELL, and the dopants of the first doping region 10 and the second doping region 12 are, for example, both dopants of the second conductivity type, such as N-doping type. It can be considered that the first doping region 10 and the second doping region 12 are formed in a local area of ​​the second well region located on the front side of the substrate P-SUB.

[0071] See also Figure 1In an optional embodiment, the power semiconductor device includes a buried region 11 of a first conductive type, such as a P-type, extending from the first doped region 10 to the interior of the substrate P-SUB at the lower side of the second well region N-WELL. The depth of the buried region 11 is deeper than the first doped region 10. Here, the depth of the buried region 11 makes it adjacent to the first doped region 10, for example, it can be located below the first doped region 10, and the depth of the buried region 11 makes it adjacent to the substrate P-SUB or, preferably, a portion of the buried region 11 can extend directly into the interior of the substrate P-SUB. The depth here is based on the front process and is the depth seen from the front of the substrate P-SUB, or the depth of ion implantation from the front.

[0072] See also Figure 1 In an optional embodiment, the power semiconductor device further includes a third doping region 13 of a first conductivity type, such as a P type, and a fourth doping region 15 of a second conductivity type, such as an N type, located on the back side of the substrate P-SUB in the first well region P-WELL. The dopant of the third doping region is, for example, a dopant of the first conductivity type, such as a P doping type, and the dopant of the fourth doping region is, for example, a dopant of the second conductivity type, such as an N doping type. As shown in the figure, it can be considered that the third doping region 13 and the fourth doping region 15 are formed in a local area of ​​the first well region located on the back side of the substrate P-SUB.

[0073] See also Figure 1 In an optional embodiment, the power semiconductor device includes a drift region 14 of a second conductivity type, such as an N-type, extending from the fourth doping region 15 to the substrate P-SUB on the upper side of the first well region P-WELL. The depth of the drift region is deeper than the fourth doping region 15. Here, the depth of the drift region 14 makes it adjacent to the fourth doping region 15, for example, it can be located above the fourth doping region 15, and the depth of the drift region 14 makes it adjacent to the substrate P-SUB or, preferably, a part of the drift region 14 can extend directly into the substrate P-SUB. The depth here is based on the back process and is the depth seen from the back of the substrate P-SUB, or the depth of ion implantation from the back.

[0074] See also Figure 1 As shown in the figure, the buried region 11 and the third doped region 13 at least partially overlap (or completely overlap each other) in the direction perpendicular to the substrate P-SUB. In an optional embodiment, when the node (PN-junction) between the first doped region 10 and the buried region 11 is reversely broken down, a vertical current path is formed between the buried region 11 and the third doped region 13, and this node can be called a main node. Because the doping concentration of the first well region P-WELL and the substrate P-SUB is much lower than that of the third doped region 13, there will be an obvious resistance value on the vertical current path.

[0075] See also Figure 1In an optional embodiment, the reason why the node between the first doped region 10 and the buried region 11 is reversely broken down includes guiding the interference voltage at the memory port I / O to couple to the first doped region 10. If the interference voltage on the I / O port is too low, the main node will not be reversely broken down, such as the voltage level of the interference voltage fluctuates within the range of high and low levels that the I / O port can tolerate. However, if the interference voltage on the I / O port reaches a certain level, the main node will be reversely broken down.

[0076] See also Figure 1 In an optional embodiment, when the node between the first doping region 10 and the buried region 11 is reversely broken down, a vertical current path is formed between the buried region 11 and the third doping region 13, and this vertical current path triggers the bipolar transistor Q1 between the second doping region 12, the substrate P-SUB, and the drift region 14 to turn on. For example, the voltage drop on the vertical current path is applied to the base of the bipolar transistor Q1. The bipolar transistor Q1 can be called the first bipolar transistor and the conduction of the bipolar transistor Q1 forms a current discharge path between the second doping region 12 and the fourth doping region 15 to allow the interference voltage of the I / O port to be discharged or released through the current generated by the current discharge path. Therefore, the actual voltage (such as interference voltage) loaded on the port should be coupled to the first doping region 10 and the second doping region 12. Note that alternative terms for the I / O port mentioned in the context of this application include I / O interface, I / O pin, etc., which have the same meaning.

[0077] See also Figure 1 In an optional embodiment, the third doping region 13 and the fourth doping region 15 should also be coupled to a reference potential with a lower voltage, such as a negative voltage or a zero potential or a reference ground GND, etc. The reference potential can also be a lower positive voltage, such as a voltage approximately similar to the level of a low level representing data.

[0078] See also Figure 1 In an optional embodiment, a top dielectric layer 20 is disposed on the front side of the substrate P-SUB, and a top metal layer 20a insulated from the substrate P-SUB through the top dielectric layer 20 is disposed on the front side of the substrate, and the top metal layer 20a contacts the first doping region 10 and the second doping region 12 through a via penetrating the top dielectric layer 20. The top dielectric layer 20 may be made of insulating films such as silicon oxide and silicon nitride.

[0079] See also Figure 1In an optional embodiment, a bottom dielectric layer 21 is provided on the back of the substrate P-SUB, and a bottom metal layer 21a insulated from the substrate P-SUB through the bottom dielectric layer 21 is provided on the back of the substrate, and the bottom metal layer 21a contacts the third doping region 13 and the fourth doping region 15 through a via penetrating the bottom dielectric layer 21. The bottom dielectric layer 21 may be made of an insulating film such as silicon oxide or silicon nitride.

[0080] See also Figure 1 In an optional embodiment, as shown in the figure, it is assumed that the power semiconductor device is soldered to a circuit board and the circuit board is represented by PCB, and the circuit board PCB is also used to carry a memory such as an SSD. A certain I / O port (I / O interface) of the memory that needs to be guaranteed to be coupled to the first doped region 10 and to the second doped region 12 by a lead WB can be designed, and then this I / O port is considered safe without worrying about the aforementioned interference voltage. The bottom metal layer 21a of the power semiconductor device can be designed to be soldered to a reference potential such as GND of the PCB through solder 30. The top metal layer 20a of the power semiconductor device can be designed to be connected to the I / O port of the memory through a lead WB. At this time, the memory and the power semiconductor device are separated. But further, both the memory and the power semiconductor device can be packaged together in the semiconductor packaging process stage: in the packaging (Assembly) process, the PCB is used to carry the memory and the power semiconductor device, and the protected I / O port of the memory chip (Die) or particle such as NAND or NOR and the top metal layer 20a of the power semiconductor device are bonded by wire WB, and then the memory chip or particle and the power semiconductor device are sealed inside with a plastic compound (compound) or a cover, and the ball grid array (ball grid array) of the PCB provides external electrical connection contacts for the respective I / O ports of the memory chip or particle and the power semiconductor device. This is taking BGA packaging as an example, and the top metal layer 20a and the bottom metal layer 21a of the power semiconductor device belong to the I / O port of the power semiconductor device itself.

[0081] See also Figure 2 In an optional embodiment, regarding the method of ensuring the security of a memory interface, a power semiconductor device is used to protect the security of a memory interface (such as SPI, I2C, USB, SATA, NVME, eMMC, and other common storage-class communication protocols or related interfaces of other communication protocols not listed here) during data communication.

[0082] See also Figure 2In an optional embodiment, a NAND with an I / O port or interface is taken as an example. Assuming that the physical structure of the port or interface of this memory is a metal pad or a connecting finger, the port or interface of the memory can directly contact the top metal layer 20a through its metal pad or connecting finger, and even the port or interface of the memory can be freely plugged in and out at the top metal layer 20a: convenient touch and flexible separation.

[0083] See also Figure 2 In an optional embodiment, the normal phenomenon of the I / O port or interface of a memory such as NAND during data communication is shown in the figure: the communication signal Data_V with high level and low level is roughly in the form of a rectangular wave, and the high level of the communication signal Data_V is, for example, a high potential representing a data code element such as one, and the low level is another low potential representing the opposite data code element such as zero. The voltage levels of the high potential and the low potential usually fluctuate only within the range of the high level and the low level that the memory can tolerate. Then the I / O port or interface will hardly be damaged.

[0084] See also Figure 2 In an optional embodiment, the abnormal phenomenon of the I / O port or interface of a memory such as NAND during data communication is shown in the figure: the communication signal Data_V is mixed with the interference signal Ring_V. There are various unexpected situations for the actual voltage applied by the interference signal to the memory port or interface. Assuming that there are various high-frequency switching power supply clutter noises generated based on power supply requirements on some adjacent wires (also belonging to the PCB) of the direct lead WB connected to the I / O port or interface on the PCB, and the lead WB of the circuit board PCB can usually be represented by wiring or routing, then these noises are the manifestation types of the interference signal Ring_V, and the interference signal Ring_V will transmit the interference voltage to the I / O port or interface of the memory through spatial coupling on the circuit board PCB. For another example, the working environment of NAND is a relatively humid environment or encounters a season full of water vapor. At this time, the creepage current of various electronic components near the NAND will creep to the I / O port or interface of the memory in the form of leakage phenomenon, that is, other surrounding electronic components generate an interference signal Ring_V in the form of creepage voltage to the port or interface of the memory. For example, the moment of NAND powering on or off usually generates an arc signal coupled to the memory port or interface, which is a type of interference signal Ring_V. In addition, interference sources caused by accidentally touching or touching the memory port or interface are also a type of interference signal Ring_V. The above situations are common sources of interference signal Ring_V, and other interference sources are not listed one by one. In fact, based on Fourier transform, it can be considered that different signal sources of mixing, such as Data_V and coexisting Ring_V in different frequency bands, have a superposition effect.

[0085] See also Figure 2 In an optional embodiment, the normal phenomenon of the I / O port or interface of a memory such as NAND during data communication is shown in the figure: the communication signal Data_V is an exemplary small code element of 0x1c mounted on the I / O. Binary identifiable data is loaded on the memory port or interface: 11100, which is the data source represented by Cont_IO at this time. At this time, the communication signal Data_V is also applied to the first doping area 10, the second doping area 12 and the top metal layer 20a, but the leakage current IVSS detected at the third doping area 13, the fourth doping area 15 and the bottom metal layer 21a does not exist and the leakage current IVSS is the current detected for Data_V at the reference potential (such as GND), represented by NA.

[0086] See also Figure 2 In an optional embodiment, the normal phenomenon of the I / O port or interface of a memory such as NAND during data communication is shown in the figure: the communication signal Data_V is an exemplary small segment code element of 0x1a mounted on the I / O. Binary identifiable data is loaded on the memory port or interface: 11010, which is the data source represented by Cont_IO at this time. Similarly, the leakage current IVSS detected at the third doping region 13, the fourth doping region 15 and the bottom metal layer 21a does not exist and the leakage current IVSS is the current detected for Data_V at the reference potential (such as GND), represented by NA.

[0087] See also Figure 2 In an optional embodiment, the normal phenomenon of the I / O port or interface of a memory such as NAND during data communication is shown in the figure: the communication signal Data_V is an exemplary small code element of 0x1f mounted on the I / O. Binary identifiable data is loaded on the memory port or interface: 11111 is the data source represented by Cont_IO at this time. Similarly, the leakage current IVSS detected at the third doping region 13 and the fourth doping region 15 and the bottom metal layer 21a does not exist and the leakage current IVSS is the current detected for Data_V at the reference potential (such as GND), represented by NA.

[0088] See also Figure 2In an optional embodiment, the abnormal phenomenon of the I / O port or interface of a memory such as NAND during data communication is shown in the figure: the interference signal Ring_V mixes the communication signal Data_V on the I / O. Unrecognizable data is loaded on the port: that is, the data source represented by Cont_IO has no actual meaning and can be represented by NA. At this time, the discharge current IVSS detected at the third doping region 13, the fourth doping region 15 and the bottom metal layer 21a already exists and the discharge current IVSS is the current detected for Data_V at the reference potential (such as GND), for example, 55mA. As mentioned above, the node between the first doping region 10 and the buried region 11, such as the main node, will reversely break down. The interference signal usually accumulates a large amount of high-level voltage such as arc or static electricity or creepage in a relatively short period of time. The actual voltage of the higher level is one of the main reasons for the reverse breakdown of the main node. For the interference signal Ring_V, based on the parasitic capacitance and parasitic inductance that must exist in the circuit, another negative feature is that the interference signal is easy to cause further ringing at the I / O. The interference signal superimposed on the periodic communication signal Data_V will amplify the voltage level of the interference signal and cause oscillation. The oscillating voltage carried by the oscillation will repeatedly impact the I / O port. If the main node is reversely broken down, the actual voltage such as the interference signal Ring_V with a higher voltage level as shown in the figure will produce a pressure relief or pressure relief path: the vertical current path between the buried area 11 and the third doped area 13 will trigger an integrated circuit component such as a bipolar transistor Q1 between the second doped area 12, the substrate P-SUB, and the drift area 14 to be turned on (turn-on), and Q1 is recorded as the first bipolar transistor. In view of providing a pressure relief or pressure relief path for the actual voltage at this time, the discharge current IVSS detected at the third doped area 13 and the fourth doped area 15 and the bottom metal layer 21a is not zero, and the higher the voltage level of the interference signal Ring_V, the greater the IVSS.

[0089] See also Figure 2In an optional embodiment, the depth of the first well region P-WELL is assumed to be D2, that is, the doping depth of the first well region P-WELL as seen from the back of the substrate. The depth from the interface of the second well region N-WELL and the substrate P-SUB to the back of the substrate is assumed to be D1. The value of the depth D2 is adjusted by the implantation depth of P-WELL, and its value partially determines the trigger sensitivity of the aforementioned vertical current path. For example, a deeper D2 is more beneficial to provide a relatively large vertical current, but it will reduce the parasitic resistance on the path and suppress the base voltage when Q1 is triggered. Therefore, the implantation depth of the first well region and its doping concentration need to achieve a certain balance. D1 minus D2 is the thickness of the remaining substrate after the first well region and the second well region are implanted in the substrate. That is, the first well region of the first conductivity type implanted on the back of the substrate P-SUB and the second well region of the second conductivity type implanted on the front of the substrate P-SUB, then the remaining part of the substrate P-SUB is between the first well region P-WELL and the second well region N-WELL, which is the part of D1 minus D2.

[0090] See also Figure 2 In an optional embodiment, the vertical current path (vetical path) provided inside the semiconductor power device for triggering the discharge event can ensure the fastest response speed of the release of the external interference voltage applied to the I / O port or interface. Inside the integrated circuit, the vertical current path is the shortest trigger path. At the moment when the vertical current breaks through the main node, the current can trigger Q1 to turn on without traveling a long distance.

[0091] See also Figure 2 In an optional embodiment, the interface (I / O) for transmitting data of the memory is connected to the top metal layer 20a, and the bottom metal layer 21a is connected to the reference potential (such as the reference ground GND). If the actual voltage loaded on the interface (such as Data_V, Ring_V or their superimposed voltage, or other voltage) exceeds the preset threshold, a current discharge path is generated between the actual voltage and the reference potential (such as the reference ground GND) through the triggered bipolar transistor Q1. For example, this current discharge path includes the discharge path where the bipolar transistor Q1 is located. The preset threshold can be adjusted by adjusting the doping concentration of the first doping region 10 and the buried region 11. The preset threshold includes, for example, the reverse breakdown voltage of the main node; or slightly higher than the reverse breakdown voltage.

[0092] See also Figure 3In an optional embodiment, in this example, the power semiconductor device and the chip IC are directly integrated or prepared on the same wafer (Die) or particle. In addition to the power semiconductor device, other chip ICs are also prepared on the same substrate P-SUB. The chip IC includes memory chips such as NAND or NOR, especially vertical three-dimensional memory circuits. The top metal layer 20a on the front side of the substrate P-SUB located on the side of the power semiconductor device can be directly extended laterally to the side of the front side of the substrate P-SUB located on the chip IC, and the lateral extension portion of the top metal layer 20a is electrically connected to the protected I / O port or interface of the chip IC.

[0093] See also Figure 3 Regarding ensuring the security of the memory interface, the power semiconductor device protects the security of the memory interface during data communication: the power semiconductor device and the memory can be separated from each other or integrated with each other.

[0094] See also Figure 4 In an optional embodiment, a first conductive type, such as a P-type floating island region 25 is provided on the front side of the second well region N-WELL on the substrate P-SUB. The volume of the floating island region 25 is much smaller than that of the first doping region 10 or the second doping region 12, and the floating island region 25 exhibits the characteristics of a small range and an isolated region.

[0095] See also Figure 4 In an optional embodiment, in a direction perpendicular to the substrate P-SUB, the floating island region 25 is offset from the third doping region 13, the fourth doping region 15, the drift region 14, etc. without overlapping. The buried region 11 at least partially overlaps with the third doping region 13 in a direction perpendicular to the substrate P-SUB. If the configuration of the integrated circuit is unreasonable, various parasitic devices that are bound to exist will have irregular effects on key elements such as the vertical current path, such as the electric field of some unreasonable parasitic junctions inducing the vertical current path to bend.

[0096] See also Figure 4In an optional embodiment, when the bipolar transistor Q1 between the second doping region 12, the substrate P-SUB, and the drift region 14 is triggered to turn on, the current under the on-condition of the bipolar transistor Q1 will continue to trigger the bipolar transistor Q2 between the floating island region 25, the second well region N-WELL, and the substrate P-SUB to turn on. For example, the on-current of the bipolar transistor Q1 will generate a voltage drop between the emitter and the base of the bipolar transistor Q2. Note that the aforementioned second doping region 12 has a greater doping concentration than the second well region N-WELL. At this time, the second well region N-WELL will parasitize lateral and longitudinal resistances between the aforementioned second doping region 12 and the base of the bipolar transistor Q2. Also note that the aforementioned first doping region 10 has a greater doping concentration than the second well region N-WELL.

[0097] See also Figure 4 In an optional embodiment, the bipolar transistor Q1, i.e., the first bipolar transistor, is triggered to turn on and the bipolar transistor Q2, i.e., the second bipolar transistor, is triggered to turn on, which means that a pair of current discharge paths are generated on the I / O interface to form a ratio Figure 1 The separate current discharge path of Q1 has a larger discharge current. If the main node reversely breaks down, the actual voltage with a higher voltage level, such as the interference signal Ring_V, will release or discharge the voltage faster. The current flowing through a pair of current discharge paths is much larger than the current flowing through a single current discharge path. Figure 4 IVSS ratio Figure 1 The IVSS is large.

[0098] See also Figure 4 In summary, the layout structure of the vertical current path that triggers the discharge event avoids the negative effects of various parasitic devices inside the power semiconductor device on the vertical current path related to current bifurcation, current startup hysteresis, etc. If no constraints are imposed, the parasitic components inside the integrated circuit may actively or passively absorb part of the vertical current to generate bifurcated currents. The parasitic components may also cause the interference signal to preferentially start the parasitic components themselves rather than triggering the circuits related to the vertical current path such as the bipolar transistor Q1 at the first time. The layout structure shown in the figure can avoid the occurrence of these negative situations to the greatest extent. Therefore, the release of the external interference voltage at the I / O port or interface almost reaches a transient response, and the interference degree of the I / O port or interface to the code element is minimized.

[0099] See also Figure 5In an optional embodiment, a floating island region 25 of a first conductivity type, such as a P type, is provided on the front side of the substrate P-SBU in the second well region N-WELL, and a body region 18 (or a connecting region) of a second conductivity type, such as an N type, adjacent to the floating island region 25 is provided on the front side of the substrate P-SBU in the second well region N-WELL. A steering diode is formed between the floating island region 25 and the connecting region or the so-called body region 18, as described below for details. Therefore, the power semiconductor device also includes a floating island region 25 of a first conductivity type located on the front side of the substrate P-SBU in the second well region R-WELL, and also includes a body region 18 of a second conductivity type adjacent to the floating island region 25. The current of the steering diode can activate the bipolar transistor Q2 earlier and in advance than the current of Q1, and the base of Q2 is sensitive to the current of the steering diode. It is worth noting that the steering diode will forcibly share a large part of the reverse voltage (such as the actual voltage on the interface), which is conducive to the quick activation of Q2 on the one hand and can slow down or avoid the depletion or punch-through of the heavily doped region 40 on the other hand.

[0100] See also Figure 5 In an optional embodiment, the second well region N-WELL is located on the front side of the substrate P-SBU and is provided with a heavily doped region 40 of a second conductivity type, such as an N-type. The power semiconductor device includes a heavily doped region 40 adjacent to the first doped region 10 and having a doping concentration exceeding that of the first doped region 10, and adjacent to the buried region 11. There is a main node between the first doped region 10 and the buried region 11, and there is a secondary node between the heavily doped region 40 and the buried region 11.

[0101] See also Figure 5 In an optional embodiment, a trench 37 extending from the heavily doped region 40 to the body region 18 is opened in the second well region N-WELL on the front side of the substrate P-SBU, and an isolation layer such as oxide is formed on the inner wall (sidewall) of the trench 37. The isolation layer 37b is, for example, silicon dioxide, silicon nitride, or silicate glass.

[0102] See also Figure 5 In an optional embodiment, the interior of the originally hollow trench 37 formed by etching is filled with a conductive material 37a that couples the heavily doped region 40 to the body region 18. The conductive material 37a is filled into the trench by deposition and the excess material is removed by etching back, leaving only the conductive material 37a in the trench 37. The conductive material 37a can be, for example, a doped semiconductor material or single crystal silicon or polycrystalline silicon or a metal material. The conductive material 37a contacts the heavily doped region 40 on the one hand and contacts the body region 18 on the other hand, so the heavily doped region 40 and the body region 18 are isolated from each other but are electrically connected to each other.

[0103] See also Figure 5In an optional embodiment, section AA is a schematic diagram of a vertical section selected at the intersection of the heavily doped region 40 and the groove 37. An isolation layer 37b is formed on the inner wall or side wall of the groove 37. The interior of the groove 37 is filled with a conductive material 37a. At section AA, a hole may be opened at the bottom of the groove 37 so that the conductive material 37a filled in the groove 37 can electrically contact the heavily doped region 40 below the groove 37 at the opening. Of course, the side of the groove 37 can also be opened by etching or other processes so that the conductive material 37a filled in the groove 37 can electrically contact the heavily doped regions 40 on both sides of the groove 37 at the side openings.

[0104] See also Figure 5 At the cross section AA, the power semiconductor device includes a trench 37 opened in the second well region N-WELL and located on the front side of the substrate, extending from the heavily doped region 40 to the body region 18, an isolation layer 37b is formed on the inner wall of the trench, and the interior of the trench is filled with a conductive material 37a electrically connected to the heavily doped region 40.

[0105] See also Figure 5 In an optional embodiment, section BB is a schematic vertical cross-sectional view of a position where the second doping region 12 and the trench 37 intersect each other. An isolation layer 37b is formed on the inner wall or sidewall of the trench 37. The interior of the trench 37 is filled with a conductive material 37a. At section BB, no holes are opened on each side of the trench 37, so that the conductive material 37a filled in the trench 37 is electrically insulated from the second doping region 12 near the trench 37.

[0106] See also Figure 5 At the cross section BB, the power semiconductor device includes a trench 37 extending from the heavily doped region 40 to the body region 18 in the second well region N-WELL, an isolation layer 37b is formed on the inner wall of the trench, and the interior of the trench is filled with a conductive material 37a electrically insulated from the second doped region 12, etc. Note that the portion of the conductive material 37a filled in the trench near the body region 18 is directly electrically connected to the body region 18.

[0107] See also Figure 5 , referring to the cross sections AA and BB, the heavily doped region 40 and the conductive material 37a are covered by the insulating layer 35 at the top of the trench 37. The insulating layer 35 is, for example, silicon dioxide, silicon nitride, or silicate glass. Therefore, the conductive material 37a inside the trench and the heavily doped region 40 are insulated at the front side of the substrate P-SBU.

[0108] See also Figure 5In an optional embodiment, preferably, spacers 41, 42 are provided on the front side of the substrate in the second well region N-WELL. The spacers 41, 42 are, for example, silicon dioxide or silicon nitride. The spacer 41 can isolate the heavily doped region from the second doped region, and the spacer 42 can isolate the second doped region from the body region and the floating island region. Note that the spacer is not necessary, because the vertical structure can largely ignore the disadvantages of the non-isolated layout.

[0109] See also Figure 5 In an optional embodiment, in the direction perpendicular to the substrate P-SBU, the floating island region 25 is set to be offset from the third doping region 13, the fourth doping region 15, and the drift region 14 without overlapping. The body region 18 is also set to be offset from the third doping region 13, the fourth doping region 15, and the drift region 14 without overlapping. The layout structure of the vertical current path that triggers the discharge event also avoids the negative impact of various parasitic devices inside the power semiconductor device on the vertical current path related to current bifurcation, current start-up hysteresis, etc. The layout structure can avoid the occurrence of these negative situations to the greatest extent. As mentioned above, the release of the external interference voltage at the I / O port or interface almost reaches a transient response, and the interference degree of the I / O port or interface to the code element is minimized.

[0110] See also Figure 6 In an optional embodiment, a top dielectric layer 20 is provided on the front side of the substrate P-SUB, and a top metal layer 20a insulated from the substrate P-SUB through the top dielectric layer 20 is provided on the front side of the substrate. The top metal layer 20a contacts the first doped region 10 through some vias penetrating the top dielectric layer 20, and the top metal layer 20a contacts the second doped region 12 through other vias penetrating the top dielectric layer 20. Furthermore, the top metal layer 20a contacts the floating island region 25 through other vias penetrating the top dielectric layer 20. Therefore, a top metal layer insulated from the substrate through the top dielectric layer is provided on the front side of the substrate, and the top metal layer contacts the first doped region, the second doped region, and the floating island region at the same time through the vias penetrating the top dielectric layer.

[0111] See also Figure 6 , the conductive material 37 a inside the trench 37 is insulated from the top metal layer 20 a .

[0112] See also Figure 6 , the heavily doped region 40 is insulated from the top metal layer 20 a.

[0113] See also Figure 6 The top dielectric layer 20 may be made of insulating films such as silicon oxide and silicon nitride.

[0114] See also Figure 6In an optional embodiment, a bottom dielectric layer 21 is provided on the back of the substrate P-SUB, and a bottom metal layer 21a is provided on the back of the substrate and is insulated from the substrate P-SUB through the bottom dielectric layer 21. The bottom metal layer 21a contacts the third doping region 13 through some vias penetrating the bottom dielectric layer 21, and the bottom metal layer 21a contacts the fourth doping region 15 through other vias penetrating the bottom dielectric layer 21. Therefore, a bottom metal layer is provided on the back of the substrate and is insulated from the substrate through the bottom dielectric layer, and the bottom metal layer contacts the third doping region and the fourth doping region at the same time through the vias penetrating the bottom dielectric layer.

[0115] See also Figure 6 The bottom dielectric layer 21 may be made of insulating films such as silicon oxide and silicon nitride.

[0116] See also Figure 6 In an optional embodiment, when the node between the first doped region 10 and the buried region 11 reaches the reverse breakdown condition but does not break down, this is an anomaly; and the control diode between the floating island region 25 and the body region (or junction region) 18 guides the node between the heavily doped region 40 and the buried region 11 to break through, and at this time a vertical current path is generated between the buried region 11 and the third doped region 13. The voltage drop on the vertical current path is applied to the base of the bipolar transistor Q1 and causes the bipolar transistor Q1 to start conducting. The bipolar transistor Q1 (for example, the first bipolar transistor) between the second doped region 12, the substrate P-SUB, and the drift region 14 is thereby triggered to turn on. The heavily doped region 40 and the buried region 11 adjacent to the first doped region 10 and having a doping concentration exceeding that of the first doped region 10 are turned on.

[0117] See also Figure 6 The advantages of using vertical integrated circuits in this application are: the vertical current path is shorter and the parasitic devices on the vertical current path, such as diodes or transistors, have less impact on the main current path, so the vertical current path can immediately generate a current discharge path due to breakdown in a very short time. This discharge sensitivity, which is sensitive to the actual voltage at the I / O port, increases the response speed by about 15% compared to planar devices of the same size chip.

[0118] See also Figure 6 In an optional embodiment, when the bipolar transistor Q1 between the second doping region 12, the substrate P-SUB, and the drift region 14 is triggered to turn on, the current under the on condition of the bipolar transistor Q1 will continue to trigger the bipolar transistor Q2 between the floating island region 25, the second well region N-WELL, and the substrate P-SUB to turn on. For example, the on current of the bipolar transistor Q1 will generate a voltage drop between the emitter and the base of the bipolar transistor Q2.

[0119] See also Figure 6 In an optional embodiment, there is a main node between the first doped region 10 and the buried region 11, and there is a secondary node between the heavily doped region 40 and the buried region 11. The conduction of the bipolar transistor Q1 forms a current discharge path between the second doped region 12 and the fourth doped region 15, so that the actual voltage of the I / O port, such as the interference voltage Ring_V, is discharged or released through the current generated by the current discharge path. The actual voltage (such as the interference voltage) loaded on the port is preferably coupled to the first doped region 10, the second doped region 12, and the floating island region 25 at the same time. When the bipolar transistor between the second doped region, the substrate, and the drift region is triggered to turn on, the current under its conduction condition triggers another bipolar transistor (such as the second bipolar transistor) between the floating island region, the second well region, and the substrate to be further turned on.

[0120] See also Figure 6 As mentioned above, the main node between the first doped region 10 and the buried region 11 reaches the reverse breakdown condition but does not break down, which is an anomaly. There are various inducing mechanisms for this type of anomaly. For example, the reverse voltage applied to the main node (such as the actual voltage on the interface, etc.) causes the second well region N-WELL to be exhausted to the vicinity of the first doped region 10, thereby reducing the effective contact surface of the node (such as the main node) between the first doped region 10 and the buried region 11. In particular, the reverse voltage is slowly and gradually raised in steps, or the depth of the second well region does not match the doping concentration. This obviously cannot protect the safety of the I / O interface. In the vertical integrated circuit layout structure of the power semiconductor device, the above-mentioned abnormal conditions are more common than those of the lateral device, but the vertical integrated circuit of the power semiconductor device has a fast response speed. For another example, the reverse voltage applied to the main node causes the second well region N-WELL to penetrate, so that the effective contact surface of the node between the first doped region 10 and the buried region 11 almost disappears. Other inducing mechanisms include the first doped region 10 and the buried region 11 becoming slightly or severely avalanched under repeated impacts of the interference voltage, etc. This is related to the application scenario of the memory I / O interface. The above abnormal mechanisms will cause the so-called main node between the first doped region 10 and the buried region 11 to have the situation that "the node between the first doped region and the buried region reaches the reverse breakdown condition but does not break down".

[0121] See also Figure 5Based on the aforementioned disadvantages, in order to solve the aforementioned problem “when the node between the first doped region and the buried region reaches the condition for reverse breakdown but fails to break down”, the solution is as follows: a floating island region 25 of a first conductivity type and a body region 18 of a second conductivity type adjacent to the floating island region 25 are provided on the front side of the substrate in the second well region N-WELL; a heavily doped region 40 is provided adjacent to the first doped region 10 and the doping concentration exceeds that of the first doped region 10; a trench 37 extending from the heavily doped region 40 to the body region 18 is opened on the front side of the substrate in the second well region N-WELL, an isolation layer 37b is generated on the inner wall of the trench 37, and the interior of the trench is filled with a conductive material 37a that couples the heavily doped region 40 to the body region 18, and the heavily doped region 40 and the filled conductive material 37a are both covered by an insulating layer 35. The specific explanation is as follows: when the node between the first doped region 10 and the buried region 11 reaches the reverse breakdown condition but does not break down, at this time, the steering diode between the floating island region 25 and the body region 18 guides the node between the heavily doped region 40 and the buried region 11 to break through, so as to trigger the bipolar transistor Q1 between the second doped region 12, the substrate P-SUB and the drift region 14 to turn on. One of the purposes is: when the depletion layer between the second well region 12 and the substrate P-SUB is close to the first doped region 10 or penetrates the first doped region 10, the combination of the steering diode and the heavily doped region 40 with a higher doping concentration than the first doped region 10 is used, so that the actual breakdown voltage that triggers the bipolar transistor Q1 between the second doped region 12, the substrate P-SUB and the drift region 14 to turn on on the vertical current path is set to be lower than the breakdown voltage of the node between the first doped region 10 and the buried region 11. Obviously, by combining a reverse breakdown path of a controlled heavily doped region 40 with a bipolar transistor Q1, the entire semiconductor power device can still respond quickly and be sensitive to interference voltage, etc. when the main node does not reversely break down or breaks down with a delay. The layout structure of the above integrated circuit can make up for the disadvantages of the vertical architecture. The depletion layer approaches the first doping region or penetrates the first doping region only in the mode of using a vertical current path between the buried region and the third doping region, otherwise it is not easy to happen. The second purpose of the above scheme is: if the actual breakdown voltage lower than the breakdown voltage of the node between the first doping region 10 and the buried region 11 triggers the bipolar transistor Q1 between the second doping region 12, the substrate P-SUB, and the drift region 14 to turn on, the current provided by the vertical current path to the steering diode activates the bipolar transistor Q2 between the floating island region 25, the second well region N-WELL, and the substrate P-SUB, so as to form positive feedback between the bipolar transistor Q2 and the bipolar transistor Q1. When the bipolar transistor Q1 between the second doped region 12, the substrate P-SUB, and the drift region 14 is triggered to turn on, the current under its on condition triggers another bipolar transistor Q2 between the floating island region 25, the second well region N-WELL, and the substrate P-SUB to be further turned on, which is positive feedback.When the bipolar transistor Q2 between the floating island region 25, the second well region N-WELL, and the substrate P-SUB is triggered to turn on, then according to the same principle, the current under its on condition triggers the bipolar transistor Q1 between the second doping region 12, the substrate P-SUB, and the drift region 14 to turn on, that is, positive feedback. The steering diode is more sensitive and easier to turn on than the node, so it is easier to establish positive feedback between Q1 and Q2. The entire power semiconductor device is more sensitive to the actual voltage such as Ring_V, and the discharge current under positive feedback conditions is larger.

[0122] See also Figure 6 , when the node between the first doped region and the buried region reaches the reverse breakdown condition but does not break down, the steering diode between the floating island region and the body region guides the node between the heavily doped region and the buried region to break through, thereby triggering the bipolar transistor Q1 between the second doped region, the substrate, and the drift region to turn on. Therefore: in the case where the depletion layer between the second well region and the substrate approaches the first doped region or penetrates the first doped region, based on the combination of the steering diode and the heavily doped region with a higher doping concentration than the first doped region, the actual breakdown voltage on the vertical current path that triggers the bipolar transistor Q1 between the second doped region, the substrate, and the drift region to turn on is set to be lower than the breakdown voltage of the node between the first doped region and the buried region. When the actual breakdown voltage, which is lower than the breakdown voltage of the node between the first doped region and the buried region, tends to trigger the bipolar transistor Q1 between the second doped region, the substrate, and the drift region to turn on, the current provided by the vertical current path to the control diode activates the bipolar transistor Q2 between the floating island region, the second well region, and the substrate, thereby forming positive feedback between the bipolar transistor Q1 and the bipolar transistor Q2.

[0123] See also Figure 6 The present application also relates to a method for ensuring the security of a memory interface, which utilizes a power semiconductor device to protect the security of a memory interface (I / O) during data communication.

[0124] See also Figure 6 , a substrate P-SUB of the first conductivity type, a first well region P-WELL of the first conductivity type implanted on the back side of the substrate P-SUB, and a second well region N-WELL of the second conductivity type implanted on the front side of the substrate P-SUB. The specific modules, units or components included in the power semiconductor device are described as follows.

[0125] See also Figure 6, a first doping region 10 and a second doping region 12 of the second conductivity type located on the front side of the substrate P-SUB in the second well region N-WELL, and a buried region 11 of the first conductivity type extending from the first doping region 10 to the inside of the substrate at the lower side of the second well region N-WELL. A third doping region 13 and a fourth doping region 15 of the first conductivity type located on the back side of the substrate in the first well region P-WELL, and a drift region 14 of the second conductivity type extending from the fourth doping region 15 to the substrate on the upper side of the first well region P-WELL. The buried region 11 and the third doping region 13 at least partially overlap in a direction perpendicular to the substrate P-SUB, and under the condition that the node between the first doping region 10 and the buried region 11 is reversely broken down, at this time, a bipolar transistor Q1 between the second doping region 12, the substrate and the aforementioned drift region 14 is designed to be turned on by a vertical current path between the buried region 11 and the third doping region 13. The method for ensuring I / O safety is described as follows.

[0126] See also Figure 6 The method includes: the I / O port or interface needs to be coupled to the first doping region 10 and the second doping region 12 at the same time, and the third doping region 13 and the fourth doping region 15 are coupled to a reference potential (for example, a reference ground potential GND) at the same time. If the actual voltage loaded on the I / O port or interface, such as Ring_V, exceeds the preset threshold, a current discharge path is generated between the actual voltage and the reference potential through the triggered bipolar transistor Q1 (at the second doping region 12, the substrate P-SUB, and the drift region 14). Depressurize or depressurize the I / O port and protect the I / O port.

[0127] See also Figure 6 A top metal layer 20a insulated from the substrate P-SUB by a top dielectric layer 20 is provided on the front side of the substrate P-SUB. The top metal layer 20a contacts the first doping region 10 and the second doping region 12 simultaneously through a via penetrating the top dielectric layer 20.

[0128] See also Figure 6 A bottom metal layer 21a insulated from the substrate P-SUB by a bottom dielectric layer 21 is provided on the back side of the substrate P-SUB. The bottom metal layer 21a contacts the third doping region 13 and the fourth doping region 15 simultaneously through a via penetrating the bottom dielectric layer 21.

[0129] See also Figure 6 , an interface (I / O) or port for transmitting data of a memory such as an SSD is connected to the top metal layer 20a, and the bottom metal layer 21a is connected to a reference potential. For example, if the actual voltage loaded on the interface (I / O) exceeds a preset threshold, a current discharge path is generated between the actual voltage and the reference potential through the bipolar transistor Q that is triggered to turn on.

[0130] See also Figure 6 A floating island region 25 of the first conductive type is designed on the front side of the second well region N-WELL located on the substrate P-SUB, and in a direction perpendicular to the substrate P-SUB, the floating island region 25 is designed to be offset from the third doping region 13, the fourth doping region 15, the drift region 14, etc. without overlapping.

[0131] See also Figure 6 When the first bipolar transistor between the second doped region 12, the substrate P-SUB, and the drift region 14 is triggered to turn on, that is, when Q1 is turned on, the current under the on condition of the bipolar transistor Q1 triggers another bipolar transistor Q2 between the floating island region 25 and the second well region N-WELL and the substrate P-SUB to be further turned on.

[0132] See also Figure 6 A floating island region 25 of the first conductivity type and a body region 18 of the second conductivity type adjacent to the floating island region 25 are provided on the front side of the second well region N-WELL on the substrate P-SUB. In this example, a heavily doped region 40 of the second conductivity type, such as N type, adjacent to the first doped region 10 and having a doping concentration higher than that of the first doped region 10 is also arranged.

[0133] See also Figure 5 A trench 37 extending from the second conductive type heavily doped region 40 to the body region 18 is provided on the front side of the second well region N-WELL located on the substrate P-SUB. An isolation layer 37b such as an oxide layer is formed on the inner wall of the trench 37, and a conductive material 37a coupling the N-type heavily doped region 40 to the body region 18 is filled inside the trench 37. Note that the heavily doped region 40 and the conductive material 37a are also designed to be covered by an insulating layer 35 such as an oxide layer.

[0134] See also Figure 6 , assuming that the substrate P-SUB is in the horizontal direction, the direction perpendicular to the substrate P-SUB can be considered as the vertical direction. In the direction perpendicular to the substrate P-SUB, the floating island region 25 is offset from the third doping region 13, the fourth doping region 15, the drift region 14, etc. without overlapping, and the body region 18 is also offset from the third doping region 13, the fourth doping region 15, the drift region 14, etc. without overlapping. This is a vertical integrated circuit layout.

[0135] See also Figure 6If the node between the first doped region 10 and the buried region 11 reaches the reverse breakdown condition but does not break down, the control diode between the floating island region 25 and the body region 18 guides the node between the heavily doped region 40 and the buried region 11 to break down, and with the help of the breakdown event, the bipolar transistor Q1 between the second doped region 12, the substrate P-SUB, and the drift region 14 is triggered to turn on. In this optional embodiment, it is essentially equivalent to the secondary node breaking down when the main node reaches the reverse breakdown condition but does not break down, so that a vertical current path is generated between the buried region 11 and the third doped region 13, and then the first bipolar transistor Q1 and the second bipolar transistor Q2 are turned on in sequence to achieve pressure relief.

[0136] See also Figure 6 A top metal layer 20a insulated from the substrate P-SUB by the top dielectric layer 20 is provided on the front side of the substrate P-SUB. The top metal layer 20a contacts the first doped region 10, the second doped region 20, and the floating island region 25 simultaneously through a through hole or a long strip groove penetrating the thickness of the top dielectric layer 20. For example, the top metal layer 20a can contact the first doped region 10 through a long strip groove penetrating the top dielectric layer 20, and for another example, the top metal layer 20a can contact the second doped region 20 through another long strip groove penetrating the top dielectric layer 20. In addition, the top metal layer 20a can contact the floating island region 25 through some circular through holes or square through holes or small-sized grooves penetrating the top dielectric layer 20.

[0137] See also Figure 6 A bottom metal layer 21a insulated from the substrate P-SUB by a bottom dielectric layer 21 is provided on the back of the substrate P-SUB. The bottom metal layer 21a contacts the third doping region 13 and the fourth doping region 15 simultaneously through a through hole or a long strip groove penetrating the thickness of the bottom dielectric layer 21. As shown in the figure, for example, the bottom metal layer 21a can contact the third doping region 13 through a long strip groove penetrating the bottom dielectric layer 21, and for another example, the bottom metal layer 21a can contact the fourth doping region 15 through another long strip groove penetrating the bottom dielectric layer 21.

[0138] See also Figure 6 When a bipolar transistor between the second doped region 12, the substrate P-SUB, and the drift region 14 is triggered to turn on, that is, Q1 is turned on, the current (such as collector current) under the on-condition of the bipolar transistor Q1 triggers the bipolar transistor Q2 between the floating island region 25, the second well region N-WELL, and the substrate P-SUB to turn on.

[0139] The above description and drawings provide typical embodiments of specific structures of specific embodiments, and the above utility model provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications to the true intention and scope of the present application. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intention and scope of the present application.

Claims

1. A power semiconductor device, characterized in that: include: A substrate of a first conductivity type, a first well region of the first conductivity type implanted on the back side of the substrate, and a second well region of the second conductivity type implanted on the front side of the substrate; First and second doped regions of the second conductivity type located on the front side of the substrate in the second well region, and a buried region of the first conductivity type extending from the first doped region to the inside of the substrate at the lower side of the second well region; A third doping region of the first conductivity type and a fourth doping region of the second conductivity type located on the back side of the substrate in the first well region, and a drift region of the second conductivity type extending from the fourth doping region to contact the substrate on the upper side of the first well region; The buried region and the third doped region at least partially overlap in a direction perpendicular to the substrate, and under the condition that the node between the first doped region and the buried region is reversely broken down, a bipolar transistor between the second doped region, the substrate, and the drift region is triggered to turn on by the vertical current path between the buried region and the third doped region.

2. The power semiconductor device according to claim 1, characterized in that: A top metal layer insulated from the substrate by a top dielectric layer is disposed on the front side of the substrate, and the top metal layer contacts the first and second doped regions simultaneously through a through hole penetrating the top dielectric layer; A bottom metal layer insulated from the substrate by a bottom dielectric layer is disposed on the back side of the substrate. The bottom metal layer contacts the third and fourth doped regions simultaneously through a through hole penetrating the bottom dielectric layer.

3. The power semiconductor device according to claim 2, characterized in that: The interface of the memory for transmitting data is connected to the top metal layer, and the bottom metal layer is connected to a reference potential. If the actual voltage loaded on the interface exceeds a preset threshold, a current discharge path is generated between the actual voltage and the reference potential through the bipolar transistor that is triggered to turn on.

4. The power semiconductor device according to claim 1, characterized in that: Also includes: A floating island region of the first conductivity type located on the front side of the substrate in the second well region, and in a direction perpendicular to the substrate, the floating island region is offset from the third and fourth doped regions and the drift region without overlapping; When the bipolar transistor between the second doped region, the substrate and the drift region is triggered to turn on, the current under the on condition triggers another bipolar transistor between the floating island region, the second well region and the substrate to be further turned on.

5. The power semiconductor device according to claim 1, characterized in that: Also includes: A floating island region of the first conductivity type located on the front side of the substrate in the second well region, and a body region of the second conductivity type adjacent to the floating island region; A heavily doped region adjacent to the first doped region and the buried region and having a doping concentration exceeding that of the first doped region; A trench is opened in the second well region and is located on the front side of the substrate and extends from the heavily doped region to the body region. An isolation layer is formed on the inner wall of the trench and the interior of the trench is filled with a conductive material that couples the heavily doped region to the body region. The heavily doped region and the conductive material are both covered by an insulating layer.

6. The power semiconductor device according to claim 5, characterized in that: In a direction perpendicular to the substrate, the floating island region is offset from the third and fourth doping regions and the drift region without overlapping, and the body region is offset from the third and fourth doping regions and the drift region without overlapping.

7. The power semiconductor device according to claim 5, characterized in that: When the node between the first doped region and the buried region reaches the reverse breakdown condition but fails to break down, the control diode between the floating island region and the body region guides the node between the heavily doped region and the buried region to break through, thereby triggering a bipolar transistor between the second doped region, the substrate, and the drift region to turn on.

8. The power semiconductor device according to claim 5, characterized in that: A top metal layer insulated from the substrate by a top dielectric layer is disposed on the front side of the substrate, and the top metal layer simultaneously contacts the first and second doped regions and the floating island region through a through hole penetrating the top dielectric layer; A bottom metal layer insulated from the substrate by a bottom dielectric layer is disposed on the back side of the substrate. The bottom metal layer contacts the third and fourth doped regions simultaneously through a through hole penetrating the bottom dielectric layer.

9. The power semiconductor device according to claim 5, characterized in that: When a bipolar transistor between the second doped region, the substrate and the drift region is triggered to turn on, the current under the on condition triggers another bipolar transistor between the floating island region, the second well region and the substrate to be further turned on.

10. The power semiconductor device according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

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