Computer mainboard

By introducing 10 Gigabit optical module connector and gigabit Ethernet transceiver on the computer motherboard, combined with ZX-200 bridge chip, the problem that the Feiteng D3000 processor can only support 5G/10G optical port speed is solved, and 1G optical port is realized Speed ​​support expands application scenarios.

CN222189798UActive Publication Date: 2024-12-17CHANGZHI ZHUOYI HENGTONG INFORMATION SECURITY CO LTD
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Patent Information

Application Number
CN202420010734.7
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-01-02
Publication Date
2024-12-17
Estimated Expiration
2034-01-02

AI Technical Summary

Technical Problem

The Feiteng D3000 processor can only support 5G/10G optical port speed, but cannot support 1G optical port speed, which limits its application scenarios.

Method used

Design a computer motherboard that includes a processor with a USXGMII interface, a 10G optical module connector and a Gigabit Ethernet transceiver to convert RGMII signals into 10G optical compliant via a ZX-200 bridge chip and a Gigabit Ethernet transceiver. The signal of the module connector interface protocol realizes the support of 1G optical port transmission rate.

Benefits of technology

The processor supports 5G/10G and 1G optical port transmission rates, which expands application scenarios, especially the Feiteng D3000 processor can form two optical port configurations for users to choose.

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Abstract

The utility model provides a computer mainboard. The computer mainboard comprises a processor with a USXGMII interface, a 10-gigabit optical module connector, a ZX-200 bridge chip and a gigabit Ethernet transceiver. And the USXGMII interface of the processor is connected to the 10-gigabit optical module connector so as to output a USXGMII signal to the 10-gigabit optical module connector. The processor is connected to the ZX-200 bridge chip through a PCIE (Peripheral Component Interface Express) bus, the ZX-200 bridge chip is provided with an RGMII (Register Gigabit Media Independent Interface) interface, and the RGMII interface is connected to the gigabit Ethernet transceiver so as to output an RGMII signal to the gigabit Ethernet transceiver. And the gigabit Ethernet transceiver is connected to the 10-gigabit optical module connector so as to convert the RGMII signal into a signal conforming to the interface protocol of the 10-gigabit optical module connector and output the signal to the 10-gigabit optical module connector. The optical port formed on the basis of the processor with the USXGMII interface not only can support 5G / 10G transmission rate, but also can support 1G transmission rate, and is wider in applicable application scene.
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Description

Technical Field

[0001] The utility model relates to the technical field of computers, in particular to a computer mainboard. Background Art

[0002] Both optical ports and electrical ports are interfaces used for network communication. Electrical ports are a general term for various twisted pair interfaces such as RJ45 in servers and networks. Since these interfaces use electricity as the carrier medium for information, they are collectively referred to as electrical ports. Optical ports, also known as fiber optic ports, are physical interfaces used to connect fiber optic cables, which use optical fiber as the transmission medium. Since optical ports use optical fiber as the transmission medium, their transmission rate and transmission distance are better than those of electrical ports, while electrical ports have more cost advantages, so the two have their own applicable scenarios.

[0003] In situations where large data transmission is required, such as enterprises, factories, data centers, etc., as the requirements for data transmission speed are getting higher and higher, the transmission speed of ordinary electrical ports can no longer meet their needs. Therefore, optical port transmission is used more and more frequently on servers and switches.

[0004] The USXGMII interface is a universal serial 10G media independent interface that can support high-speed data transmission. Existing processors with USXGMII interfaces can directly connect the USXGMII interface to the SFP+ connector to form an optical port and output high-speed optical signals. However, since the USXGMII signal is a branch of the SerDes signal, although it can form an optical signal, it cannot support the rate negotiation function during data transmission due to different protocols and can only support the forced mode. Therefore, using the USXGMII interface to form an optical port can only support 5G / 10G transmission rates, but not 1G transmission rates.

[0005] This is particularly evident in the Feiteng D3000 processor. The Feiteng D3000 processor has USXGMII and SGMII media independent interfaces, which only directly support USXGMII and SGMII signal outputs. Since the SGMII interface cannot be used directly as a SerDes interface, it can only be connected to the USXGMII interface to the SFP+ connector to form a 5G / 10G optical port. This means that the Feiteng D3000 processor can only support 5G / 10G optical port rates, but not 1G optical port rates.

[0006] Therefore, it is necessary to further improve the computer motherboard based on this type of processor with USXGMII interface so that its optical port can not only support 5G / 10G transmission rate, but also support 1G transmission rate, so as to be suitable for a wider range of application scenarios. Utility Model Content

[0007] The purpose of the utility model is to provide a computer motherboard based on a processor with a USXGMII interface, the optical port formed by which can not only support 5G / 10G transmission rate, but also support 1G transmission rate, and is applicable to a wider range of application scenarios.

[0008] To achieve the above-mentioned purpose, the utility model provides a computer motherboard, comprising a processor with a USXGMII interface, the computer motherboard also comprising a 10 Gigabit optical module connector, a ZX-200 bridge chip and a Gigabit Ethernet transceiver, wherein the USXGMII interface of the processor is connected to the 10 Gigabit optical module connector to output a USXGMII signal to the 10 Gigabit optical module connector; the processor is connected to the ZX-200 bridge chip via a PCIE bus, the ZX-200 bridge chip has an RGMII interface, the RGMII interface is connected to the Gigabit Ethernet transceiver to output an RGMII signal to the Gigabit Ethernet transceiver; the Gigabit Ethernet transceiver is connected to the 10 Gigabit optical module connector to convert the RGMII signal into a signal that complies with the interface protocol of the 10 Gigabit optical module connector and outputs it to the 10 Gigabit optical module connector.

[0009] Preferably, the processor is a Feiteng D3000 processor.

[0010] Preferably, the 10 Gigabit optical module connector is an SFP+ optical module connector.

[0011] Preferably, the Gigabit Ethernet transceiver is connected to the SFP+ optical module connector to convert the RGMII signal into an SFP signal and output it to the SFP+ optical module connector.

[0012] Preferably, the model of the Gigabit Ethernet transceiver is YT8521.

[0013] Beneficial effects of the present invention: The computer motherboard of the present invention is based on a processor with a USXGMII interface, and the optical port formed can not only support 5G / 10G transmission rate, but also support 1G transmission rate, and can provide users with different configuration designs according to their needs, and is applicable to a wider range of application scenarios; in particular, when the processor is a Feiteng D3000 processor, the computer motherboard of the present invention can support the processor with two output signals (USXGMII signal and PCIE signal) to form two optical port configurations, which respectively support 5G / 10G transmission rate and 1G transmission rate, so that users can choose different configuration designs according to their needs, which solves the problem that when the Feiteng D3000 processor is used to implement the optical port function, it can only support 5G / 10G optical port rate but cannot support 1G optical port rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are only provided for reference and explanation and are not intended to limit the present invention.

[0015] In the accompanying drawings,

[0016] Figure 1 It is a structural block diagram of the computer mainboard of the utility model. DETAILED DESCRIPTION

[0017] In order to further illustrate the technical means and effects adopted by the present invention, the preferred embodiments of the present invention and the accompanying drawings are described in detail below.

[0018] like Figure 1 As shown, the computer motherboard of the utility model includes a processor 10 with a USXGMII interface, a 10 Gigabit optical module connector 20, a ZX-200 bridge chip 30 and a Gigabit Ethernet transceiver 40. The USXGMII interface of the processor 10 is connected to the 10 Gigabit optical module connector 20 to output a USXGMII signal to the 10 Gigabit optical module connector 20; the processor 10 is also connected to the ZX-200 bridge chip 30 via a PCIE bus. The ZX-200 bridge chip 30 has an RGMII interface, and the RGMII interface is connected to the Gigabit Ethernet transceiver 40 to output an RGMII signal to the Gigabit Ethernet transceiver 40. The Gigabit Ethernet transceiver 40 is connected to the 10 Gigabit optical module connector 20 to convert the RGMII signal into a signal that complies with the interface protocol of the 10 Gigabit optical module connector 20 and output it to the 10 Gigabit optical module connector 20.

[0019] Specifically, the USXGMII interface of the processor 10 of the computer motherboard of the present invention is connected to the 10 Gigabit optical module connector 20, and an optical port can be formed by the 10 Gigabit optical module connector 20 to support a transmission rate of 5G / 10G; at the same time, the processor 10 of the computer motherboard of the present invention is connected to the ZX-200 bridge chip 30 via the PCIE bus, and the ZX-200 bridge chip 30 is also connected to the 10 Gigabit optical module connector 20 via the Gigabit Ethernet transceiver 40, and an optical port is formed by the 10 Gigabit optical module connector 20 to support a transmission rate of 1G.

[0020] Therefore, although the processor 10 on the computer motherboard of the present invention can only form a 5G / 10G optical port through its USXGMII interface, it can also form a 1G optical port at the same time on the 10G optical module connector 20 through the ZX-200 bridge chip 30 and the Gigabit Ethernet transceiver 40. It can be seen that the processor of the computer motherboard of the present invention can actually support two output signals (USXGMII signal and PCIE signal), forming two optical port configurations, respectively supporting 5G / 10G transmission rate and 1G transmission rate, so that users can choose different configuration designs according to their needs.

[0021] Further, the processor 10 may be a Feiteng D3000 processor, and the 10G optical module connector 20 may be an SFP+ optical module connector. The USXGMII interface of the Feiteng D3000 processor 10 is connected to the SFP+ optical module connector 20 to form a 5G / 10G optical port, supporting a 5G / 10G transmission rate.

[0022] Moreover, the Gigabit Ethernet transceiver 40 is connected to the SFP+ optical module connector 20 to convert the RGMII signal into an SFP signal and output it to the SFP+ optical module connector 20, thereby forming a 1G optical port and supporting a 1G transmission rate.

[0023] Since the media independent interfaces of the Feiteng D3000 processor are USXGMII interface and SGMII interface, only USXGMII signal and SGMII signal output are directly supported, and the SGMII interface cannot be directly used as a SerDes interface, therefore, a 5G / 10G optical port can only be formed by connecting the USXGMII interface to the SFP+ optical module connector. However, in the present invention, the Feiteng D3000 processor 10 is also connected to the ZX-200 bridge chip 30 via the PCIE bus, and the ZX-200 bridge chip 30 outputs the RGMII signal to the Gigabit Ethernet transceiver 40, and the Gigabit Ethernet transceiver 40 converts the RGMII signal into an SFP signal, which is also output to the SFP+ optical module connector 20, so that the same SFP+ optical module connector 20 can be used to form a 1G optical port. In this way, the computer motherboard based on the Feiteng D3000 processor can support two output signals (USXGMII signal and PCIE signal), forming two optical port configurations, supporting 5G / 10G transmission rate and 1G transmission rate respectively, so that users can choose different configuration designs according to their needs, thereby solving the problem that when using the Feiteng D3000 processor to implement the optical port function, it can only support 5G / 10G optical port rate but not 1G optical port rate.

[0024] In a preferred embodiment, the model of the Gigabit Ethernet transceiver is YT8521.

[0025] In summary, the computer motherboard of the utility model is based on a processor with a USXGMII interface, and the optical port formed can not only support 5G / 10G transmission rate, but also support 1G transmission rate, and can provide users with different configuration designs according to their needs, and is applicable to a wider range of application scenarios. In particular, when the processor is a Feiteng D3000 processor, the computer motherboard of the utility model can support the processor to form two optical port configurations with two output signals (USXGMII signal and PCIE signal), respectively supporting 5G / 10G transmission rate and 1G transmission rate, so that users can choose different configuration designs according to their needs, which solves the problem that when using the Feiteng D3000 processor to realize the optical port function, it can only support 5G / 10G optical port rate but cannot support 1G optical port rate.

[0026] As described above, for ordinary technicians in this field, various other corresponding changes and modifications can be made according to the technical scheme and technical concept of the utility model, and all these changes and modifications should fall within the protection scope of the claims of the utility model.

Claims

1. A computer motherboard, comprising a processor having a USXGMII interface, It is characterized in that The computer motherboard also includes a 10 Gigabit optical module connector, a ZX-200 bridge chip and a Gigabit Ethernet transceiver, wherein the USXGMII interface of the processor is connected to the 10 Gigabit optical module connector to output a USXGMII signal to the 10 Gigabit optical module connector; the processor is connected to the ZX-200 bridge chip via a PCIE bus, the ZX-200 bridge chip has an RGMII interface, and the RGMII interface is connected to the Gigabit Ethernet transceiver to output an RGMII signal to the Gigabit Ethernet transceiver; the Gigabit Ethernet transceiver is connected to the 10 Gigabit optical module connector to convert the RGMII signal into a signal that complies with the interface protocol of the 10 Gigabit optical module connector and outputs it to the 10 Gigabit optical module connector.

2. The computer motherboard according to claim 1, It is characterized in that The processor is a Feiteng D3000 processor.

3. The computer motherboard according to claim 1 or 2, It is characterized in that The 10 Gigabit optical module connector is an SFP+ optical module connector.

4. The computer motherboard according to claim 3, It is characterized in that The Gigabit Ethernet transceiver is connected to the SFP+ optical module connector to convert the RGMII signal into an SFP signal and output the SFP signal to the SFP+ optical module connector.

5. The computer motherboard according to claim 4, It is characterized in that The model of the Gigabit Ethernet transceiver is YT8521.