Solar cell, cell assembly and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides a solar cell, a cell module and a photovoltaic system. The solar cell comprises a doping layer, a conductive layer and an electrode which are sequentially stacked on a substrate, and the conductive layer comprises an I CO: H layer, an AZO layer and an I TO layer which are sequentially stacked in the direction from the doping layer to the electrode. Therefore, due to the fact that the stacked structure of the I CO: H layer, the AZO layer and the I TO layer is adopted between the doping layer and the electrode to serve as the conducting layer, the I CO: H layer can be used for reducing parasitic absorption of the conducting layer and reducing contact resistance between the conducting layer and the doping layer, the AZO layer can be used for reducing the use amount of indium elements, cost is reduced, the I TO layer can be used for preventing water and oxygen in air from entering the AZO layer, and the service life of the electrode is prolonged. And the contact resistance between the conductive layer and the electrode is reduced. Therefore, the photoelectric conversion efficiency of the solar cell is improved, and the cost is reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of solar cells, and in particular to a solar cell, a battery assembly and a photovoltaic system. Background Art

[0002] In order to better collect current and reduce reflection, a conductive layer is usually set between the doped layer and the electrode of the solar cell. In the related art, ITO is usually used as the conductive layer. However, the conductivity and light transmittance of the ITO layer cannot be achieved at the same time, which makes it difficult to improve the photoelectric conversion efficiency of the solar cell. Moreover, the price of indium element is expensive, resulting in a high cost of the ITO layer. Based on this, how to design the conductive layer to improve the photoelectric conversion efficiency and reduce the cost has become a problem to be solved urgently. Utility Model Content

[0003] The present application provides a solar cell, a battery assembly and a photovoltaic system, aiming to solve the problem of how to design a conductive layer to improve photoelectric conversion efficiency and reduce costs.

[0004] The solar cell provided in the present application comprises a doping layer, a conductive layer and an electrode stacked in sequence on a substrate. Along the direction from the doping layer to the electrode, the conductive layer comprises an I CO:H layer, an AZO layer and an I TO layer stacked in sequence.

[0005] Specifically, the thickness of the I CO:H layer is less than the thickness of the AZO layer;

[0006] And / or, the thickness of the ITO layer is less than the thickness of the AZO layer.

[0007] Specifically, the thickness of the I CO:H layer is 5nm-30nm.

[0008] Specifically, the sheet resistance of the I CO:H layer is 50Ω / □-250Ω / □, and the light transmittance is 90%-99%.

[0009] Specifically, the thickness of the AZO layer is 50nm-100nm;

[0010] And / or, the thickness of the ITO layer is 5nm-30nm.

[0011] The battery assembly provided in the present application includes any of the above-mentioned solar cells.

[0012] The photovoltaic system provided in the present application includes any one of the above-mentioned battery components.

[0013] The solar cell, battery assembly and photovoltaic system of the embodiment of the present application use a stacked structure of an ICO:H layer, an AZO layer and an ITO layer as a conductive layer between the doping layer and the electrode, so the ICO:H layer can be used to reduce the parasitic absorption of the conductive layer and reduce the contact resistance between the conductive layer and the doping layer, the AZO layer can be used to reduce the amount of indium element, thereby reducing the cost, and the ITO layer can be used to block water and oxygen in the air from entering the AZO layer and reduce the contact resistance between the conductive layer and the electrode. In this way, it is beneficial to improve the photoelectric conversion efficiency of the solar cell and reduce the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

[0015] Figure 2 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application;

[0016] Description of main component symbols:

[0017] Solar cell 100, silicon substrate 101, first intrinsic amorphous silicon layer 111, N-type doped nanocrystalline silicon layer 112, N-type doped nanocrystalline silicon oxide layer 113, second intrinsic amorphous silicon layer 121, P-type doped nanocrystalline silicon layer 122, doping layer 21, conductive layer 22, I CO:H layer 221, AZO layer 222, I TO layer 223, electrode 23. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0019] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0023] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0024] In the present application, since a stacked structure of an ICO:H layer, an AZO layer, and an ITO layer is used as a conductive layer between the doped layer and the electrode, the ICO:H layer can be used to reduce the parasitic absorption of the conductive layer and reduce the contact resistance between the conductive layer and the doped layer, the AZO layer can be used to reduce the amount of indium element, thereby reducing the cost, and the ITO layer can be used to block water and oxygen in the air from entering the AZO layer and reduce the contact resistance between the conductive layer and the electrode. In this way, it is beneficial to improve the photoelectric conversion efficiency of the solar cell and reduce the cost.

[0025] Embodiment 1

[0026] See also Figure 1 The solar cell 100 of the embodiment of the present application includes a doping layer 21, a conductive layer 22 and an electrode 23 stacked in sequence on a substrate. Along the direction from the doping layer 21 to the electrode 23, the conductive layer 22 includes an I CO:H layer 221, an AZO layer 222 and an I TO layer 223 stacked in sequence.

[0027] The solar cell 100 of the embodiment of the present application uses a stacked structure of an ICO:H layer 221, an AZO layer 222, and an ITO layer 223 as the conductive layer 22 between the doped layer 21 and the electrode 23. Therefore, the ICO:H layer 221 can be used to reduce the parasitic absorption of the conductive layer 22 and reduce the contact resistance between the conductive layer 22 and the doped layer 21. The AZO layer 222 can be used to reduce the amount of indium element, thereby reducing the cost. The ITO layer 223 can be used to block water and oxygen in the air from entering the AZO layer 222 and reduce the contact resistance between the conductive layer 22 and the electrode 23. In this way, the photoelectric conversion efficiency of the solar cell 100 is improved and the cost is reduced.

[0028] Specifically, the solar cell 100 may be a thin film cell or a crystalline silicon cell. Examples of thin film cells are perovskite cells, GI GS cells, etc. Examples of crystalline silicon cells are HJT cells, PERC cells, TopCon cells, etc. The solar cell 100 may be a single cell or a stacked cell. The solar cell 100 may be a double-sided contact cell or a back contact cell. The specific form of the solar cell 100 is not limited herein.

[0029] The following explanation and description will be given by taking the solar cell 100 as an HJT cell as an example, but this does not represent a limitation on the specific form of the solar cell 100 .

[0030] Specifically, the base includes a silicon substrate 101, a first intrinsic amorphous silicon layer 111, an N-type doped nanocrystalline silicon layer 112 and an N-type doped nanocrystalline silicon oxide layer 113. The first intrinsic amorphous silicon layer 111, the N-type doped nanocrystalline silicon layer 112 and the N-type doped nanocrystalline silicon oxide layer 113 are sequentially stacked on the silicon substrate 101, and the doping layer 21 includes the N-type doped nanocrystalline silicon layer 112 and the N-type doped nanocrystalline silicon oxide layer 113.

[0031] In this way, the N-type nanocrystalline silicon oxide layer can be used to reduce the parasitic absorption of short waves, so that the doped layer 21 that easily absorbs short waves can better transmit short waves. At the same time, compared with other doped layers 21 such as doped amorphous silicon layers, the N-type doped nanocrystalline silicon layer 112 has better doping performance and conductive performance while ensuring optical performance.

[0032] It can be understood that the band gap of the N-type nanocrystalline silicon oxide layer is relatively wide. As a window layer, it can effectively reduce the parasitic absorption phenomenon, which is beneficial to improve the short-circuit current density of the solar cell 100. At the same time, the work function of the N-type nanocrystalline silicon oxide layer and the conductive layer 22 is more matched, and the contact resistance between the N-type nanocrystalline silicon oxide layer and the conductive layer 22 can be reduced. However, due to the poor work function matching between the N-type nanocrystalline silicon oxide layer and the intrinsic amorphous silicon layer, it will cause an increase in contact resistance and a decrease in fill factor. Therefore, the N-type doped nanocrystalline silicon layer 112 can be used to maintain a high short-circuit current density and optimize the fill factor, which can effectively reduce the contact resistance between the doped layer 21 and the intrinsic amorphous silicon layer, and at the same time reduce the parasitic absorption of the doped layer 21.

[0033] It is understandable that in other embodiments, the N-type nanocrystalline silicon oxide layer may also be omitted.

[0034] Specifically, the silicon substrate 101 may be N-type crystalline silicon. It is understood that in other embodiments, the silicon substrate 101 may also be a P-type silicon substrate 101 .

[0035] Specifically, the thickness of the first intrinsic amorphous silicon layer 111 is 2nm-10nm, for example 2nm, 5nm, 8nm, 10nm. In this way, the thickness of the intrinsic amorphous silicon layer is within a suitable range, which can avoid poor passivation performance caused by too small thickness, and can also avoid poor optical and electrical performance caused by too large thickness.

[0036] Specifically, the thickness of the N-type doped nanocrystalline silicon layer 112 is 5nm-20nm. For example, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm, 20nm. In this way, the thickness of the N-type doped nanocrystalline silicon layer 112 is within a suitable range, which can avoid poor performance of selective contact caused by too small thickness, and can also avoid too strong parasitic absorption caused by too large thickness.

[0037] It can be understood that the thickness of the doped layer 21 is usually kept constant, so that the overall refractive index and transmittance of the doped layer 21 are relatively stable. Therefore, if the thickness of the N-type doped nanocrystalline silicon layer 112 is increased, the thickness of the N-type doped nanocrystalline silicon oxide layer 113 will decrease. Compared with N-type doped nanocrystalline silicon, the parasitic absorption of short waves by N-type doped nanocrystalline silicon oxide is weaker. Therefore, if the thickness of the N-type doped nanocrystalline silicon layer 112 is too large, the thickness of the N-type doped nanocrystalline silicon oxide layer 113, which has weaker parasitic absorption of short waves, will be too small, resulting in serious parasitic absorption.

[0038] Specifically, the thickness of the N-type doped nanocrystalline silicon oxide layer 113 is 1nm-5nm. For example, 1nm, 2nm, 3nm, 4nm, 5nm. In this way, the thickness of the N-type doped nanocrystalline silicon oxide layer 113 is within a suitable range, which can avoid poor optical performance caused by too small thickness, and can also avoid too small thickness of the N-type doped nanocrystalline silicon layer 112 and poor selective contact performance caused by too large thickness of the N-type doped nanocrystalline silicon oxide layer 113, and poor electrical performance of the doped layer 21 as a whole.

[0039] It can be understood that the thickness of the doped layer 21 is usually kept constant, so that the overall refractive index and transmittance of the doped layer 21 are relatively stable. Therefore, if the thickness of the N-type doped nanocrystalline silicon oxide layer 113 is increased, the thickness of the N-type doped nanocrystalline silicon layer 112 will decrease, resulting in poor selective contact performance and electrical performance.

[0040] Specifically, the base includes a silicon substrate 101, a second intrinsic amorphous silicon layer 121 and a P-type doped nanocrystalline silicon layer 122, the second intrinsic amorphous silicon layer 121 and the P-type doped nanocrystalline silicon layer 122 are sequentially stacked on the silicon substrate 101, and the doping layer 21 includes the P-type doped nanocrystalline silicon layer 122. In this way, the P-type doped nanocrystalline silicon layer 122 can be used to replace the traditional P-type amorphous silicon layer, thereby enhancing the conductivity of the transmitter and effectively reducing the contact resistance with the conductive layer 22, thereby improving the fill factor of the solar cell 100.

[0041] Specifically, the thickness of the P-type doped nanocrystalline silicon layer 122 is 1 nm-20 nm. For example, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm. In this way, the thickness of the P-type doped nanocrystalline silicon layer 122 is within a suitable range, which can avoid poor performance of selective contact caused by too small thickness, and can also avoid too strong parasitic absorption caused by too large thickness.

[0042] exist Figure 1 In the example of , both sides of the solar cell 100 are formed with sequentially stacked doping layers 21, conductive layers 22 and electrodes 23. It can be understood that in other embodiments, the sequentially stacked doping layers 21, conductive layers 22 and electrodes 23 can be formed on one side of the solar cell 100.

[0043] Specifically, the I CO:H layer 221 refers to a hydrogenated cerium-doped indium oxide layer.

[0044] Specifically, the AZO layer 222 is aluminum-doped zinc oxide (AZO).

[0045] Specifically, the square resistance of the AZO layer 222 is 50Ω / □-500Ω / □, and the light transmittance is 90%-95%. The square resistance of the AZO layer 222 is, for example, 50Ω / □, 80Ω / □, 100Ω / □, 250Ω / □, 400Ω / □, 500Ω / □. The light transmittance of the AZO layer 222 is, for example, 90%, 91%, 92%, 93%, 94%, 95%. In this way, the square resistance and transmittance of the AZO layer 222 are both in a suitable range, so that the AZO layer 222 has better light transmittance, lower current loss, moderate cost, and better overall effect.

[0046] Specifically, the ITO layer 223 is indium tin oxide (ITO).

[0047] Specifically, the square resistance of the ITO layer 223 is 100Ω / □-500Ω / □, and the light transmittance is 85%-95%. The square resistance of the ITO layer 223 is, for example, 100Ω / □, 200Ω / □, 300Ω / □, 400Ω / □, 500Ω / □. The light transmittance is, for example, 85%, 88%, 90%, 92%, 95%. In this way, the square resistance and transmittance of the ITO layer 223 are both in a suitable range, so that the electrical performance of the ITO layer 223 is better, the current loss is lower, the cost is moderate, and the overall effect is better.

[0048] It can be understood that for the conductive layer 22, the smaller the square resistance, the less current loss. However, if the square resistance is too small, the transmittance will be worse. Therefore, the square resistance and transmittance are both in the appropriate range to achieve a balance, so that the overall effect is better.

[0049] Specifically, the electrode 23 includes a silver electrode 23, an aluminum electrode 23, a copper electrode 23, etc.

[0050] Embodiment 2

[0051] In some embodiments, the thickness of the I CO:H layer 221 is less than the thickness of the AZO layer 222 .

[0052] In this way, the thickness of the AZO layer 222 is relatively large, so that the AZO layer 222 has better optical performance at a moderate cost, which is conducive to the transmission of light. At the same time, the thickness of the I CO:H layer 221 is relatively small, and when the overall thickness of the conductive layer 22 is generally constant, a margin is provided for increasing the thickness of the AZO layer 222. Moreover, Ce is a rare earth element, and the relatively small thickness of the I CO:H layer 221 is conducive to reducing costs.

[0053] In some embodiments, the thickness of the ITO layer 223 is less than the thickness of the AZO layer 222 .

[0054] In this way, the thickness of the AZO layer 222 is relatively large, so that the optical performance of the AZO layer 222 is better at a moderate cost, which is conducive to the transmission of light. At the same time, the thickness of the ITO layer 223 is relatively small, and when the overall thickness of the conductive layer 22 is generally constant, a margin is provided for increasing the thickness of the AZO layer 222. Moreover, the ITO layer 223 is relatively expensive and harmful to the environment, and the relatively small thickness of the ITO layer 223 is conducive to reducing costs and protecting the environment.

[0055] Embodiment 3

[0056] In some embodiments, the thickness of the I CO:H layer 221 is 5 nm-30 nm, for example, 5 nm, 8 nm, 10 nm, 15 nm, 20 nm, 22 nm, 25 nm, 28 nm, or 30 nm.

[0057] In this way, the thickness of the I CO:H layer 221 is within an appropriate range, which can avoid poor electrical performance due to too small a thickness and also avoid too high a cost due to too large a thickness.

[0058] Embodiment 4

[0059] In some embodiments, the sheet resistance of the I CO:H layer 221 is 50Ω / □-250Ω / □, and the light transmittance is 90%-99%.

[0060] In this way, the square resistance and light transmittance of the I CO:H layer 221 are within a suitable range, so that the electrical performance of the I CO:H layer 221 is better, the current loss is lower, the cost is moderate, and the overall effect is better.

[0061] It can be understood that for the conductive layer 22, the smaller the square resistance, the less current loss. However, if the square resistance is too small, the transmittance will be worse. Therefore, the square resistance and transmittance are both in the appropriate range to achieve a balance, so that the overall effect is better.

[0062] Specifically, the sheet resistance of the I CO:H layer 221 is, for example, 50Ω / □, 80Ω / □, 100Ω / □, 150Ω / □, 200Ω / □, or 250Ω / □.

[0063] Specifically, the light transmittance of the I CO:H layer 221 is, for example, 90%, 92%, 95%, 98%, or 99%.

[0064] Embodiment 5

[0065] In some embodiments, the thickness of the AZO layer 222 is 50 nm-100 nm, for example, 50 nm, 70 nm, 90 nm, or 100 nm.

[0066] In this way, the thickness of the AZO layer 222 is within an appropriate range, which can avoid the larger thickness and higher cost of the I CO:H layer 221 and the I TO layer 223 caused by too small thickness, and can also avoid poor electrical performance caused by too large thickness.

[0067] In some embodiments, the thickness of the ITO layer 223 is 5 nm-30 nm, for example, 5 nm, 8 nm, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm.

[0068] In this way, the thickness of the ITO layer 223 is within an appropriate range, which can avoid poor blocking and protection effects and poor electrical performance caused by too small a thickness, and can also avoid too high a cost caused by too large a thickness.

[0069] Embodiment 6

[0070] See also Figure 1 and Figure 2 The method for manufacturing the solar cell 100 according to the embodiment of the present application comprises:

[0071] Step S11: providing a substrate on which a conductive layer 22 is to be fabricated;

[0072] Step S12: forming an I CO:H layer 221 on the doping layer 21 of the substrate;

[0073] Step S13: forming an AZO layer 222 on the I CO:H layer 221;

[0074] Step S14: forming an ITO layer 223 on the AZO layer 222;

[0075] Step S15 : forming an electrode 23 on the ITO layer 223 .

[0076] In the manufacturing method of the solar cell 100 of the embodiment of the present application, since the stacked structure of the ICO:H layer 221, the AZO layer 222 and the ITO layer 223 is used as the conductive layer 22 between the doped layer 21 and the electrode 23, the ICO:H layer 221 can be used to reduce the parasitic absorption of the conductive layer 22 and reduce the contact resistance between the conductive layer 22 and the doped layer 21, the AZO layer 222 can be used to reduce the amount of indium element, thereby reducing the cost, and the ITO layer 223 can be used to block water and oxygen in the air from entering the AZO layer 222 and reduce the contact resistance between the conductive layer 22 and the electrode 23. In this way, the photoelectric conversion efficiency of the solar cell 100 is improved and the cost is reduced.

[0077] Please note that the explanation and description of the method for manufacturing the solar cell 100 can be cross-referenced with the explanation and description of the solar cell 100 in the previous text. To avoid redundancy, the repeated parts will not be repeated.

[0078] Specifically, after step S11, the substrate may be cleaned to prevent dirt on the substrate from affecting the subsequent film production.

[0079] Specifically, in step S12 , at least one of a sputtering process, a PECVD process, and a PVD process may be used to form the I CO:H layer 221 on the doping layer 21 of the substrate.

[0080] Please note that in step S12, the I CO:H layer 221 may be formed by manufacturing the I CO:H layer 221 in the doping layer 21, or the I CO:H layer 221 may be formed in the process of manufacturing other film layers in the doping layer 21. In other words, the I CO:H layer 221 may be a byproduct formed in the process of manufacturing other film layers.

[0081] Specifically, in step S13 , at least one of a sputtering process, a PECVD process, and a PVD process may be used to form the AZO layer 222 on the ICO:H layer 221 .

[0082] Please note that in step S13, the AZO layer 222 may be formed by manufacturing the AZO layer 222 on the I CO:H layer 221, or the AZO layer 222 may be formed in the process of manufacturing other film layers on the I CO:H layer 221. In other words, the AZO layer 222 may be a byproduct formed in the process of manufacturing other film layers.

[0083] Specifically, step S13 includes:

[0084] Using a sputtering process, an AZO layer 222 is formed on the I CO:H layer 221;

[0085] The deposition power is 6.5 kW-8 kW, the deposition pressure is 0.1 Pa-0.6 Pa, the sputtering gas includes oxygen and argon, and the oxygen content is 0.5%-5%.

[0086] In this way, the AZO layer 222 has fewer impurities, better film uniformity and compactness, and is more firmly attached to the I CO:H layer 221. Moreover, the various process parameters for making the AZO layer 222 are all within a suitable range, and the various process parameters cooperate with each other, so that the quality of the AZO layer 222 is better. In this way, the quality of the conductive layer 22 is improved.

[0087] Furthermore, the sputtering process includes a DC magnetron sputtering process. In other embodiments, an AC sputtering process, a reactive sputtering process, etc. may also be used, which is not limited here.

[0088] Further, the deposition power is, for example, 6.5 kW, 6.8 kW, 7 kW, 7.2 kW, 7.5 kW, 7.8 kW, and 8 kW.

[0089] Furthermore, the deposition pressure is, for example, 0.1Pa, 0.2Pa, 0.3Pa, 0.4Pa, 0.5Pa, or 0.6Pa.

[0090] Furthermore, the oxygen content is, for example, 0.5%, 0.8%, 1%, 1.5%, 3%, 4.5%, or 5%.

[0091] Specifically, in step S14 , at least one of a sputtering process, a PECVD process, and a PVD process may be used to form the ITO layer 223 on the AZO layer 222 .

[0092] Please note that in step S14, the ITO layer 223 may be formed by manufacturing the ITO layer 223 on the AZO layer 222, or the ITO layer 223 may be formed in the process of manufacturing other film layers on the AZO layer 222. In other words, the ITO layer 223 may be a byproduct formed in the process of manufacturing other film layers.

[0093] Specifically, step S14 includes:

[0094] Using a sputtering process, an ITO layer 223 is formed on the AZO layer 222;

[0095] The deposition power is 1 kW-5 kW, the deposition pressure is 0.1 Pa-0.8 Pa, the sputtering gas includes oxygen and argon, and the oxygen content is 0.5%-5%.

[0096] In this way, the ITO layer 223 has fewer impurities, better film uniformity and compactness, and is more firmly attached to the AZO layer 222. Moreover, the various process parameters for making the ITO layer 223 are all within a suitable range, and the various process parameters cooperate with each other, so that the quality of the ITO layer 223 is better. In this way, the quality of the conductive layer 22 is improved.

[0097] Furthermore, the sputtering process includes a DC magnetron sputtering process. In other embodiments, an AC sputtering process, a reactive sputtering process, etc. may also be used, which is not limited here.

[0098] Furthermore, the deposition power is, for example, 1 kW, 2 kW, 3 kW, 4 kW, or 5 kW.

[0099] Furthermore, the deposition pressure is, for example, 0.1Pa, 0.3Pa, 0.4Pa, 0.5Pa, 0.7Pa, or 0.8Pa.

[0100] Furthermore, the oxygen content is, for example, 0.5%, 0.8%, 1%, 1.5%, 3%, 4.5%, or 5%.

[0101] Specifically, in step S15, a screen printing process can be used to print a paste on the ITO layer 223, and the paste printed on the ITO layer 223 is dried and cured to form the electrode 23. Specifically, the paste includes a low-temperature silver paste. It is understood that in other embodiments, an evaporation process, a sputtering process, an electroplating process, etc. can also be used to form the electrode 23, which is not limited here. It is understood that in other embodiments, the electrode 23 can also be an aluminum electrode 23, a copper electrode 23, etc., which is not limited here.

[0102] Specifically, before step S11, a stacked first intrinsic amorphous silicon layer 111, an N-type doped nanocrystalline silicon layer 112 and an N-type doped nanocrystalline silicon oxide layer 113 may be sequentially formed on the silicon substrate 101, and the doped layer 21 includes the N-type doped nanocrystalline silicon layer 112 and the N-type doped nanocrystalline silicon oxide layer 113. In this way, the N-type nanocrystalline silicon oxide layer can be used to reduce the parasitic absorption of short waves, so that the doped layer 21 that easily absorbs short waves can better transmit short waves. At the same time, compared with other doped layers 21 such as doped amorphous silicon layers, the N-type doped nanocrystalline silicon layer 112 has better doping performance and conductive performance while ensuring optical performance.

[0103] Furthermore, the silicon substrate 101 may be N-type crystalline silicon. It is understood that in other embodiments, the silicon substrate 101 may also be a P-type silicon substrate 101 .

[0104] Furthermore, the silicon substrate 101 can be cleaned and textured to form a texture layer on the silicon substrate 101. In this way, the texture layer can be used to reduce the reflection of light, so that more light is absorbed and converted by the silicon substrate 101, which is conducive to improving the photoelectric conversion efficiency.

[0105] Furthermore, the first intrinsic amorphous silicon layer 111 may be formed by a PECVD process. The power is 12 mW / cm 2 -16mW / cm 2 The chamber temperature is 180°C-220°C, and the deposition pressure is 100mTorr-200mTorr. Furthermore, the power is, for example, 12mW / cm 2 、13mW / cm 2 、14mW / cm 2 、15mW / cm 2 、16mW / cm 2 The chamber temperature is, for example, 180°C, 190°C, 200°C, 210°C, or 220°C. The deposition pressure is, for example, 100mTorr, 120mTorr, 150mTorr, 180mTorr, or 200mTorr. In this way, the first intrinsic amorphous silicon layer 111 has a dense film layer, few pinholes, and good adhesion. Moreover, the various process parameters for making the first intrinsic amorphous silicon layer 111 are all within a suitable range, and the various process parameters cooperate with each other, so that the quality of the first intrinsic amorphous silicon layer 111 is better.

[0106] Further, the N-type doped nanocrystalline silicon layer 112 can be formed by a PECVD process. Wherein, the doping gas includes phosphine, hydrogen and silane, the ratio of the flow rate of hydrogen to the flow rate of silane is 400 times-800 times, the ratio of the flow rate of phosphine to the flow rate of hydrogen is 2%-5%, the power of the coating equipment is 8kW-15kW, and the deposition pressure is 5Torr-10Torr. Further, the ratio of the flow rate of hydrogen to the flow rate of silane is, for example, 400 times, 450 times, 600 times, 700 times, 750 times, 800 times. The ratio of the flow rate of phosphine to the flow rate of hydrogen is, for example, 2%, 2.5%, 3%, 4%, 4.5%, 5%. The power of the coating equipment is, for example, 8kW, 9kW, 10kW, 11kW, 12kW, 13kW, 14kW, 15kW. The deposition pressure is, for example, 5 Torr, 6 Torr, 7 Torr, 8 Torr, 9 Torr, and 10 Torr. In this way, the N-type doped nanocrystalline silicon layer 112 has a dense film layer, few pinholes, and good adhesion. Moreover, all process parameters for making the N-type doped nanocrystalline silicon layer 112 are within a suitable range, and the various process parameters cooperate with each other, so that the quality of the N-type doped nanocrystalline silicon layer 112 is better.

[0107] Further, the N-type doped nanocrystalline silicon oxide layer 113 can be formed by PECVD process. Wherein, the doping gas includes phosphine, hydrogen, silane and carbon dioxide, the ratio of the flow rate of hydrogen to the flow rate of silane is 200-600 times, the ratio of the flow rate of phosphine to the flow rate of hydrogen is 0.5%-3%, the power of the coating equipment is 5kW-10kW, and the deposition pressure is 3Torr-8Torr. Further, the ratio of the flow rate of hydrogen to the flow rate of silane is, for example, 200 times, 250 times, 400 times, 500 times, 580 times, 600 times. The ratio of the flow rate of phosphine to the flow rate of hydrogen is, for example, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%. The power of the coating equipment is, for example, 5kW, 6kW, 7kW, 8kW, 9kW, 10kW. The deposition pressure is, for example, 3Torr, 4Torr, 5Torr, 6Torr, 7Torr, 8Torr. In this way, the N-type doped nanocrystalline silicon oxide layer 113 has a dense film layer, few pinholes, and good adhesion. Moreover, the various process parameters for making the N-type doped nanocrystalline silicon oxide layer 113 are all within a suitable range, and the various process parameters cooperate with each other, making the quality of the N-type doped nanocrystalline silicon oxide layer 113 better.

[0108] Specifically, before step S11, a stacked second intrinsic amorphous silicon layer 121 and a P-type doped nanocrystalline silicon layer 122 may be sequentially formed on the silicon substrate 101, and the doped layer 21 includes the P-type doped nanocrystalline silicon layer 122. In this way, the P-type doped nanocrystalline silicon layer 122 may be used to replace the traditional P-type amorphous silicon layer, thereby enhancing the conductivity of the transmitter and effectively reducing the contact resistance with the conductive layer 22, thereby improving the fill factor of the solar cell 100.

[0109] Furthermore, the second intrinsic amorphous silicon layer 121 may be formed by a PECVD process. The power is 12 mW / cm 2 -16mW / cm 2 The chamber temperature is 180°C-220°C, the deposition pressure is 100mTorr-200mTorr. The power is, for example, 12mW / cm 2 、13mW / cm 2 、14mW / cm 2 、15mW / cm 2 、16mW / cm 2The chamber temperature is, for example, 180°C, 190°C, 200°C, 210°C, or 220°C. The deposition pressure is, for example, 100mTorr, 120mTorr, 150mTorr, 180mTorr, or 200mTorr. In this way, the second intrinsic amorphous silicon layer 121 has a dense film layer, few pinholes, and good adhesion. Moreover, all process parameters for making the second intrinsic amorphous silicon layer 121 are within a suitable range, and the various process parameters cooperate with each other, so that the quality of the second intrinsic amorphous silicon layer 121 is better.

[0110] Further, the P-type doped nanocrystalline silicon layer 122 can be formed by PECVD process. The doping gas includes borane, hydrogen and silane, the ratio of the flow rate of hydrogen to the flow rate of silane is 50-200 times, the ratio of the flow rate of borane to the flow rate of silane is 0.1%-3%, the power of the coating equipment is 0.5kW-20kW, and the pressure is 40Pa-1000Pa. Further, the ratio of the flow rate of hydrogen to the flow rate of silane is, for example, 50 times, 80 times, 100 times, 120 times, 150 times, 200 times. The ratio of the flow rate of borane to the flow rate of silane is, for example, 0.1%, 1%, 1.5%, 2%, 2.5%, 3%. The power of the coating equipment is, for example, 0.5kW, 1kW, 5kW, 10kW, 15kW, 20kW. The deposition pressure is, for example, 40Pa, 80Pa, 100Pa, 500Pa, 800Pa, and 1000Pa. In this way, the P-type doped nanocrystalline silicon layer 122 has a dense film layer, few pinholes, and good adhesion. Moreover, all process parameters for making the P-type doped nanocrystalline silicon layer 122 are within a suitable range, and the various process parameters cooperate with each other, so that the quality of the P-type doped nanocrystalline silicon layer 122 is better.

[0111] Embodiment 7

[0112] In some embodiments, step S12 includes:

[0113] Using a sputtering process, an I CO:H layer 221 is formed on the doping layer 21 of the substrate;

[0114] The deposition power is 1 kW-2 kW, the deposition pressure is 0.2 Pa-0.7 Pa, the sputtering gas includes oxygen, hydrogen and argon, the oxygen content is 1%-3%, and the hydrogen content is 5%-15%.

[0115] In this way, the I CO:H layer 221 has fewer impurities, better film uniformity and compactness, and is more firmly attached to the doping layer 21. Moreover, various process parameters for making the I CO:H layer 221 are within a suitable range, and various process parameters cooperate with each other, so that the quality of the I CO:H layer 221 is better. In this way, the quality of the conductive layer 22 is improved.

[0116] Furthermore, the sputtering process includes a DC magnetron sputtering process. In other embodiments, an AC sputtering process, a reactive sputtering process, etc. may also be used, which is not limited here.

[0117] Furthermore, the deposition power is, for example, 1 kW, 1.2 kW, 1.5 kW, 1.8 kW, or 2 kW.

[0118] Furthermore, the deposition pressure is, for example, 0.2Pa, 0.3Pa, 0.4Pa, 0.5Pa, 0.6Pa, or 0.7Pa.

[0119] Furthermore, the oxygen content is, for example, 1%, 1.5%, 1.8%, 2%, 2.5%, or 3%.

[0120] Furthermore, the content of hydrogen is, for example, 5%, 8%, 10%, 11%, 13%, or 15%.

[0121] It can be understood that if the hydrogen content is too low, it is easy to cause the carrier concentration and mobility of the I CO:H layer 221 to be low, resulting in poor conductivity of the I CO:H layer 221. If the hydrogen content is too high, it is easy to cause the carrier concentration of the I CO:H layer 221 to be large, resulting in large parasitic absorption and poor optical performance. Therefore, the hydrogen content is 5%-15%, so that the hydrogen content is in a suitable range when the I CO:H layer 221 is manufactured, which is conducive to improving the quality of the I CO:H layer 221.

[0122] Specifically, in the step of forming the I CO:H layer 221 on the doping layer 21 of the substrate by sputtering, the doping concentration of Ce in the target material is 1%-3%. For example, 1%, 1.5%, 2%, 2.5%, 3%. In this way, the content of Ce in the target material is within a suitable range, which can avoid the Ce doping concentration in the I CO:H layer 221 being too low or even unable to be doped due to too low content, and can also avoid the Ce doping concentration in the I CO:H layer 221 being too high due to too high content, even wasting materials and increasing costs.

[0123] In summary, the solar cell 100 of the present application adopts a high-mobility I CO:H layer 221, which can effectively reduce the parasitic absorption phenomenon of the conductive layer 22, and can effectively reduce the contact resistance between the conductive layer 22 and the nanocrystalline silicon oxide layer. Since the initial crystallinity of the AZO layer 222 when deposited on the N-type doped nanocrystalline silicon oxide layer 113 is poor, the direct use of the AZO layer 222 will result in a higher contact resistance, thereby increasing the overall series resistance of the solar cell 100, affecting the improvement of the battery efficiency. The I CO:H layer 221 can effectively avoid the problem of high contact resistance. The AZO layer 222 can reduce the amount of indium element in the solar cell 100, thereby reducing the manufacturing cost of the battery. The AZO layer 222 has optical properties comparable to those of the I TO layer 223, but the electrical properties are relatively poor, and the AZO layer 222 has poor resistance to humid and hot environments. The present application uses the I TO layer 223 as the capping layer of the AZO layer 222, which can effectively prevent water and oxygen in the air from entering the AZO layer 222. Depositing the ITO layer 223 on the AZO layer 222 can simultaneously reduce the contact resistance with the electrode 23, and further optimize the electrical contact performance of the conductive layer 22. Compared with the prior art, the present application can reduce costs and optimize electrical performance by improving the structure of the conductive layer 22, and can reduce the content of indium in the conductive layer 22 by more than 30%, thereby greatly reducing the cost of the solar cell 100.

[0124] Embodiment 8

[0125] The solar cell 100 of the embodiment of the present application is manufactured by using the manufacturing method of the solar cell 100 of the sixth embodiment or the seventh embodiment.

[0126] The solar cell 100 of the embodiment of the present application uses a stacked structure of an ICO:H layer 221, an AZO layer 222, and an ITO layer 223 as the conductive layer 22 between the doped layer 21 and the electrode 23. Therefore, the ICO:H layer 221 can be used to reduce the parasitic absorption of the conductive layer 22 and reduce the contact resistance between the conductive layer 22 and the doped layer 21. The AZO layer 222 can be used to reduce the amount of indium element, thereby reducing the cost. The ITO layer 223 can be used to block water and oxygen in the air from entering the AZO layer 222 and reduce the contact resistance between the conductive layer 22 and the electrode 23. In this way, the photoelectric conversion efficiency of the solar cell 100 is improved and the cost is reduced.

[0127] Embodiment 9

[0128] The battery assembly of the embodiment of the present application includes the solar cell 100 of any one of the first to fifth embodiments or the eighth embodiment.

[0129] In the battery assembly of the embodiment of the present application, since the solar cell 100 uses a stacked structure of an ICO:H layer 221, an AZO layer 222, and an ITO layer 223 as the conductive layer 22 between the doped layer 21 and the electrode 23, the ICO:H layer 221 can be used to reduce the parasitic absorption of the conductive layer 22 and reduce the contact resistance between the conductive layer 22 and the doped layer 21, the AZO layer 222 can be used to reduce the amount of indium element, thereby reducing the cost, and the ITO layer 223 can be used to block water and oxygen in the air from entering the AZO layer 222 and reduce the contact resistance between the conductive layer 22 and the electrode 23. In this way, the photoelectric conversion efficiency of the solar cell 100 is improved and the cost is reduced.

[0130] In this embodiment, a plurality of solar cells 100 in the battery assembly can be connected in series in sequence to form a battery string, thereby realizing the series bus output of the current. For example, the series connection of the battery cells can be realized by setting welding strips (bus bars, interconnecting strips), conductive backplanes, etc.

[0131] It is understandable that in such an embodiment, the battery assembly may further include a metal frame, a back plate, photovoltaic glass and an adhesive film. The adhesive film may be filled between the front and back of the solar cell 100 and the photovoltaic glass, adjacent cells, etc. As a filler, it may be a transparent colloid with good light transmission and aging resistance. For example, the adhesive film may be an EVA adhesive film or a POE adhesive film. The specific selection may be based on actual conditions and is not limited here.

[0132] Photovoltaic glass can cover the adhesive film on the front side of the solar cell 100. The photovoltaic glass can be ultra-white glass, which has high light transmittance, high transparency, and excellent physical, mechanical and optical properties. For example, the light transmittance of ultra-white glass can reach more than 92%, which can protect the solar cell 100 without affecting the efficiency of the solar cell 100 as much as possible. At the same time, the adhesive film can bond the photovoltaic glass and the solar cell 100 together, and the presence of the adhesive film can seal and insulate the solar cell 100 and make it waterproof and moisture-proof.

[0133] The backplane can be attached to the adhesive film on the back of the solar cell 100. The backplane can protect and support the solar cell 100 and has reliable insulation, water resistance and aging resistance. There are multiple options for the backplane, which can usually be tempered glass, organic glass, aluminum alloy TPT composite adhesive film, etc. It can be set according to specific circumstances and is not limited here. The whole composed of the backplane, solar cell 100, adhesive film and photovoltaic glass can be set on a metal frame. The metal frame serves as the main external support structure of the entire battery assembly and can stably support and install the battery assembly. For example, the battery assembly can be installed at the required location through the metal frame.

[0134] Embodiment 10

[0135] The photovoltaic system of the embodiment of the present application includes the battery assembly of the ninth embodiment.

[0136] In the photovoltaic system of the embodiment of the present application, since the solar cell 100 uses a stacked structure of an ICO:H layer 221, an AZO layer 222, and an ITO layer 223 as the conductive layer 22 between the doped layer 21 and the electrode 23, the ICO:H layer 221 can be used to reduce the parasitic absorption of the conductive layer 22 and reduce the contact resistance between the conductive layer 22 and the doped layer 21, the AZO layer 222 can be used to reduce the amount of indium element, thereby reducing the cost, and the ITO layer 223 can be used to block water and oxygen in the air from entering the AZO layer 222 and reduce the contact resistance between the conductive layer 22 and the electrode 23. In this way, the photoelectric conversion efficiency of the solar cell 100 is improved and the cost is reduced.

[0137] In this embodiment, the photovoltaic system can be applied to photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple battery components. For example, multiple battery components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0138] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0139] In addition, the above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that: The invention comprises a doping layer, a conductive layer and an electrode which are sequentially stacked on a substrate. Along the direction from the doping layer to the electrode, the conductive layer comprises an ICO:H layer, an AZO layer and an ITO layer which are sequentially stacked.

2. The solar cell according to claim 1, characterized in that The thickness of the ICO:H layer is smaller than the thickness of the AZO layer.

3. The solar cell according to claim 1, characterized in that The thickness of the ITO layer is smaller than the thickness of the AZO layer.

4. The solar cell according to claim 1, characterized in that The thickness of the ICO:H layer is 5nm-30nm.

5. The solar cell according to claim 1, characterized in that: The sheet resistance of the ICO:H layer is 50Ω / □-250Ω / □, and the light transmittance is 90%-99%.

6. The solar cell according to claim 1, characterized in that The thickness of the AZO layer is 50nm-100nm.

7. The solar cell according to claim 1, characterized in that The thickness of the ITO layer is 5nm-30nm.

8. A battery assembly, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 7.

9. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 8.

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