Three-phase four-wire system inverter circuit and energy storage system

Abstract

The utility model relates to a three-phase four-wire system inverter circuit and an energy storage system. Comprising a first capacitor and a second capacitor which are connected in series and are connected in parallel to two ends of a direct-current voltage; a three-phase inverter circuit; the three-level balancing circuit comprises a first switch, a second switch, a third switch and a fourth switch which are connected in series and then connected in parallel with direct current voltage; two ends of the third capacitor are connected in parallel to two ends of the second switch and the third switch; one end of the first inductor is connected between the second switch and the third switch, and the other end of the first inductor is connected to the bus as the output of the three-level balancing circuit; and the balancing circuit controller enables the voltage output by the three-level balancing circuit to be equal to half of the direct-current voltage. According to the utility model, the balance circuit controller controls the output potential of the three-level balance circuit to be equal to half of the input voltage, and the neutral point of the three-phase AC phase voltage is pulled to a balance point. Therefore, under the three-phase unbalanced load, the three-phase phase voltage is balanced.

Description

Technical Field

[0001] The disclosed embodiments relate to the technical field of power electronic converters, and in particular to a three-phase four-wire inverter circuit and an energy storage system. Background Art

[0002] Power inverters widely use three-level inverters, which are power electronic conversion devices that can convert DC voltage into AC voltage. The working principle of the three-level inverter is: the three-level inverter is composed of two capacitors connected to active switches of positive and negative polarity and an intermediate capacitor connected between the positive and negative poles. When the capacitor is in a charging state, the circuit automatically switches to another capacitor and charges the intermediate capacitor to the same voltage level as the previous capacitor. The three-level inverter can generate three different output voltage levels, thereby achieving high-efficiency power conversion. The use of a three-level inverter can reduce the loss of the switch and achieve higher conversion efficiency.

[0003] In the prior art, the I-type three-level inverter is a very common inverter topology circuit, which usually adopts a three-phase three-wire system and space vector pulse width modulation (SVPWM) for space vector control. In order to enable the inverter to carry a three-phase unbalanced load, a balanced bridge arm is added to form a three-phase four-wire inverter. At present, the voltage stress platform of each switching device is half of the DC input voltage, which greatly reduces the switching loss of the hanging device.

[0004] Regarding the above technical solution, the following problems are found: the three-level inverter has a characteristic that in order to maintain the voltage stress of the inner tube, the timing logic requirement of the inner tube being turned on first and the outer tube being turned on later when turning on and the outer tube being turned off first and the inner tube being turned off later when turning off must be maintained. If all four bridge arms adopt the I-type three-level bridge arm, four logic circuits are required. For the I-type inverter that usually adopts three bridge arms, adding an inverter bridge arm often leads to a shortage of existing control resources.

[0005] Therefore, it is necessary to improve one or more problems existing in the above-mentioned related technical solutions.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content

[0007] The purpose of the embodiments of the present disclosure is to provide a three-phase four-wire inverter circuit and an energy storage system, thereby at least solving one or more problems existing in the above-mentioned related technical solutions.

[0008] The purpose of the utility model is achieved by the following technical solutions:

[0009] In a first aspect, the utility model first provides a three-phase four-wire inverter circuit, comprising:

[0010] A voltage balancing circuit, the voltage balancing circuit comprising: a first capacitor and a second capacitor connected in series and connected in parallel to both ends of a DC voltage;

[0011] A three-phase inverter circuit, which is connected in parallel to both ends of the DC voltage and outputs a three-phase AC voltage and a bus;

[0012] A three-level balancing circuit, the three-level balancing circuit comprising: a third capacitor, a first inductor, and a first switch, a second switch, a third switch, and a fourth switch which are sequentially connected in series and connected in parallel to a DC voltage; wherein two ends of the third capacitor are connected in parallel to two ends of the second switch and the third switch; one end of the first inductor is connected between the second switch and the third switch, and the other end of the first inductor is connected to the bus as an output of the three-level balancing circuit;

[0013] A balancing circuit controller, wherein the balancing circuit controller is used to make the first switch and the fourth switch serve as a first complementary switch group, the second switch and the third switch serve as a second complementary switch group, and the first complementary switch group and the second complementary switch group have a phase difference of 180 degrees; and to keep the output voltage of the three-level balancing circuit equal to half of the DC voltage.

[0014] Optionally, when the output voltage of the three-level balancing circuit is greater than half of the DC voltage, the balancing circuit controller drives the first complementary switch group and the second complementary switch group so that the duty cycle of the on-time of the first switch is greater than 50%, so that the three-level balancing circuit operates in a boost discharge mode.

[0015] Optionally, when the output voltage of the three-level balancing circuit is less than half of the DC voltage, the balancing circuit controller drives the first complementary switch group and the second complementary switch group so that the duty cycle of the on-time of the first switch is less than 50%, so that the three-level balancing circuit operates in a buck charging mode.

[0016] Optionally, when the voltage difference between the output voltage of the three-level balancing circuit and half of the DC voltage is within a preset threshold range, the balancing circuit controller turns off driving the first complementary switch group and the second complementary switch group.

[0017] Optionally, a neutral line is connected between the first capacitor and the second capacitor of the voltage balancing circuit, and the neutral line is connected to the busbar by grounding.

[0018] Optionally, a neutral line is connected between the first capacitor and the second capacitor of the voltage balancing circuit, and the neutral line and the bus are not connected to each other.

[0019] Optionally, the three-level balancing circuit also includes a pre-charging circuit, which includes a resistor and a reverse diode connected in series in sequence, one end of the pre-charging circuit is connected between the first capacitor and the second capacitor, and the other end of the pre-charging circuit is connected between the third switch and the fourth switch, for pre-charging the third capacitor to half of the DC voltage.

[0020] Optionally, the three-phase inverter circuit adopts an I-type three-level inverter, and the I-type three-level inverter includes: a fifth switch, a sixth switch, a seventh switch and an eighth switch which are sequentially connected in series and then connected in parallel to a DC voltage, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch which are sequentially connected in series and then connected in parallel to the DC voltage, and a thirteenth switch, a fourteenth switch, a fifteenth switch and a sixteenth switch which are sequentially connected in series and then connected in parallel to the DC voltage; a first diode and a second diode are sequentially connected in series and then connected in reverse parallel to both ends of the sixth switch and the seventh switch, and the first diode and the second diode are connected between the first capacitor and the second capacitor; a third diode and a fourth diode are sequentially connected in series and then connected in reverse parallel to both ends of the tenth switch and the eleventh switch, and the third diode and the fourth diode are connected between the first capacitor and the second capacitor; a fifth diode and a sixth diode are sequentially connected in series and then connected in reverse parallel to both ends of the fourteenth switch and the fifteenth switch, and the fifth diode and the sixth diode are connected between the first capacitor and the second capacitor;

[0021] One end of the second inductor is connected between the sixth switch and the seventh switch, and the other end of the second inductor serves as the output of one phase among the three phases; one end of the third inductor is connected between the tenth switch and the eleventh switch, and the other end of the third inductor serves as the output of one phase among the three phases; one end of the fourth inductor is connected between the fourteenth switch and the fifteenth switch, and the other end of the fourth inductor serves as the output of one phase among the three phases; one end of the fourth capacitor is connected to the other end of the second inductor, and the other end of the fourth capacitor is connected to the bus; one end of the fifth capacitor is connected to the other end of the third inductor, and the other end of the fifth capacitor is connected to the bus; one end of the sixth capacitor is connected to the other end of the fourth inductor, and the other end of the sixth capacitor is connected to the bus.

[0022] Optionally, the three-phase inverter circuit adopts a T-type three-level inverter, and the T-type three-level inverter includes: a fifth switch and an eighth switch which are sequentially connected in series and then connected in parallel to the DC voltage, a sixth switch and a seventh switch are connected in series, one end of which is connected between the fifth switch and the eighth switch, and the other end is connected between the first capacitor and the second capacitor through grounding; a ninth switch and a twelfth switch which are sequentially connected in series and then connected in parallel to the DC voltage, a tenth switch and an eleventh switch are connected in series, one end of which is connected between the ninth switch and the twelfth switch, and the other end is connected between the first capacitor and the second capacitor through grounding; a thirteenth switch and a sixteenth switch which are sequentially connected in series and then connected in parallel to the DC voltage, a fourteenth switch and a fifteenth switch are connected in series, one end of which is connected between the thirteenth switch and the sixteenth switch, and the other end is connected between the first capacitor and the second capacitor through grounding;

[0023] One end of the second inductor is connected between the fifth switch and the eighth switch, and the other end of the second inductor serves as the output of one phase among the three phases; one end of the third inductor is connected between the ninth switch and the twelfth switch, and the other end of the third inductor serves as the output of one phase among the three phases; one end of the fourth inductor is connected between the thirteenth switch and the sixteenth switch, and the other end of the fourth inductor serves as the output of one phase among the three phases; one end of the fourth capacitor is connected to the other end of the second inductor, and the other end of the fourth capacitor is connected to the bus; one end of the fifth capacitor is connected to the other end of the third inductor, and the other end of the fifth capacitor is connected to the bus; one end of the sixth capacitor is connected to the other end of the fourth inductor, and the other end of the sixth capacitor is connected to the bus.

[0024] In a second aspect, the utility model further provides an energy storage system, comprising: an input power supply, a load, and a three-phase four-wire inverter circuit, wherein the three-phase four-wire inverter circuit adopts any one of the three-phase four-wire inverter circuits described above.

[0025] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects:

[0026] In the embodiment of the present disclosure, the output potential of the three-level balancing circuit is controlled by the balancing circuit controller to be equal to half of the input voltage, thereby pulling the midpoint of the three-phase AC phase voltage to the balance point, thereby maintaining the three-phase phase voltage balanced under the three-phase unbalanced load.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic structural diagram of a three-phase four-wire inverter circuit in an exemplary embodiment of the present disclosure is shown;

[0030] Figure 2 A schematic diagram of a topology circuit of an I-type three-level inverter in the related art is shown;

[0031] Figure 3 A schematic diagram showing a driving waveform timing of a boost discharge mode in an exemplary embodiment of the present disclosure;

[0032] Figure 4 A current loop schematic diagram showing a boost discharge mode state 1 in an exemplary embodiment of the present disclosure;

[0033] Figure 5 A current loop schematic diagram showing a boost discharge mode state 2 in an exemplary embodiment of the present disclosure;

[0034] Figure 6 A current loop schematic diagram showing a boost discharge mode state 3 in an exemplary embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram showing a driving waveform timing sequence of a buck charging mode in an exemplary embodiment of the present disclosure;

[0036] Figure 8 A current loop schematic diagram showing a buck charging mode state 1 in an exemplary embodiment of the present disclosure;

[0037] Fig. 9 A current loop schematic diagram showing a buck charging mode state 2 in an exemplary embodiment of the present disclosure;

[0038] Fig.10 A current loop schematic diagram showing a buck charging mode state 3 in an exemplary embodiment of the present disclosure;

[0039] Fig.11 A schematic structural diagram of a three-phase four-wire inverter circuit using a pre-charging circuit in an exemplary embodiment of the present disclosure is shown;

[0040] Fig.12 A schematic structural diagram of a three-phase four-wire inverter circuit using an I-type inverter with a disconnected midpoint in an exemplary embodiment of the present disclosure is shown;

[0041] Fig.13 A schematic structural diagram of a three-phase four-wire inverter circuit using a midpoint-connected T-type inverter in an exemplary embodiment of the present disclosure is shown;

[0042] Fig.14 A schematic structural diagram of a three-phase four-wire inverter circuit using a T-type inverter with a disconnected midpoint in an exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0044] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0045] In this exemplary embodiment, a three-phase four-wire inverter circuit is first provided. Figure 1 As shown in , it includes: a voltage equalizing circuit, a three-phase inverter circuit, a three-level balancing circuit and a balancing circuit controller.

[0046] The voltage equalizing circuit includes: a first capacitor C1 and a second capacitor C2 connected in series and connected in parallel to two ends of the DC voltage.

[0047] The three-phase inverter circuit is connected in parallel to both ends of the DC voltage and outputs a three-phase AC voltage and a bus.

[0048] The three-level balancing circuit includes: a third capacitor C3, a first inductor L1, and a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4 which are connected in series in sequence and connected in parallel to a DC voltage; wherein two ends of the third capacitor C3 are connected in parallel to two ends of the second switch S2 and the third switch S3; one end of the first inductor L1 is connected between the second switch S2 and the third switch S3, and the other end of the first inductor L1 is connected to the bus as an output of the three-level balancing circuit.

[0049] The balancing circuit controller is used to make the first switch S1 and the fourth switch S4 serve as a first complementary switch group, the second switch S2 and the third switch S3 serve as a second complementary switch group, and the first complementary switch group and the second complementary switch group have a phase difference of 180 degrees; so that the output voltage of the three-level balancing circuit remains equal to half of the DC voltage.

[0050] It should be understood that the circuit structure takes a three-phase three-wire inverter of type I three-level structure as an example, and adds a flying capacitor three-level bridge arm on this basis, and a three-level balancing circuit composed of switches S1~S4, a first inductor L1 and a third capacitor C3, and the first inductor L1 is connected to the midpoint of the bridge arm and the neutral point of the three-phase inverter output. Among them, the balancing circuit controller is used to control the output of the three-level balancing circuit to always be equal to half of the input. In addition, in addition to the balancing circuit controller used to control the three-level balancing circuit, the three-phase inverter circuit also has its corresponding three-phase inverter controller.

[0051] It should also be understood that the phases of the first complementary switch group and the second complementary switch group differ by 180 degrees, that is, the first complementary switch group and the second complementary switch group operate alternately.

[0052] It is also necessary to understand that Figure 2 This is a topology circuit of a type I three-level inverter in the related art. In order to enable the inverter to carry a three-phase unbalanced load, a balanced bridge arm is added to form a three-phase four-wire inverter. Figure 2 As shown, the voltage stress platform of each switching device is half of the DC input voltage, which greatly reduces the switching loss of the switching device.

[0053] It is also necessary to understand that the working principle of the three-level balancing circuit is to take energy from the total DC input, and the neutral point of the inverter is used as the control output, and the output voltage is always controlled to be equal to half of the input power supply. Specifically, the control logic of the balancing circuit controller is: when the potential of the neutral point of the three-phase inverter is greater than half of the total DC input voltage, the three-level balancing circuit needs to work in the boost discharge mode. When the potential of the neutral point of the three-phase inverter is less than half of the total DC input voltage, the three-level balancing circuit needs to work in the buck charging mode.

[0054] It is also necessary to understand that a neutral line is connected between the first capacitor and the second capacitor of the voltage balancing circuit, and the neutral line is connected to the busbar through grounding.

[0055] It should also be understood that the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are insulated gate bipolar transistors (IGBT) of the same model and specification, or metal-oxide semiconductor field effect transistors (MOSFET) of the same model and specification.

[0056] It is also necessary to understand that the flying capacitor three-level is applied to the balanced bridge arm in the I-type three-level inverter. When all four bridge arms are I-type three-level, the blocking protection logic takes up a lot of resources. After replacing one of the bridge arms with a flying three-level balanced circuit, the timing of the protection logic driving the wave is not so demanding.

[0057] It is also necessary to understand that, during normal operation, the average voltage of the third capacitor C3 is half of the total input voltage. During switch protection, there are no strict requirements for the timing of the inner and outer tubes. Assuming that the outer tube S1 is turned on before the inner tube S2, the voltage borne by the other outer tube S4 is the total power supply voltage minus the voltage of the third capacitor C3, and the total voltage of S2 and S3 will not exceed the voltage of the third capacitor C3. Therefore, the outer tube turning on first will not cause any switch to be overstressed. Similarly, assuming that the inner tube S2 is turned off before the outer tube S3, the total voltage of S2 and S3 will not exceed the voltage of the third capacitor C3, so there will be no risk of overvoltage stress after the inner tube is turned off. Therefore, the three-level balanced circuit retains the benefits of the three-level circuit, but solves the limitation problem that the inner and outer tubes have strict timing logic requirements during wave protection.

[0058] Therefore, the three-phase four-wire inverter circuit of the utility model adopts SVPWM modulation control to control the three-phase inverter to output a symmetrical three-phase AC line voltage. The balance circuit controller always controls the output potential of the three-level balance circuit to be equal to half of the input voltage, thereby pulling the midpoint of the three-phase AC phase voltage to the balance point. Thus, the three-phase phase voltage is also balanced under the three-phase unbalanced load. The function and performance are consistent with the existing I-type three-level three-phase four-wire inverter.

[0059] Below, reference Figures 1 to 14 The above-mentioned three-phase four-wire inverter circuit in this example embodiment is described in more detail.

[0060] Optionally, refer to Figures 3 to 6 As shown in FIG. 1 , when the output voltage of the three-level balancing circuit is greater than half of the DC voltage, the balancing circuit controller drives the first complementary switch group and the second complementary switch group to make the duty cycle of the on-time of the first switch S1 greater than 50%, so that the three-level balancing circuit operates in the boost discharge mode. It should be understood that the on-time of S1 is used as the duty cycle. The driving waveform timing reference issued by the balancing circuit controller Figure 3 As shown: S1 and S4 drive complementary, S2 and S3 drive complementary, S1 and S2 duty cycle equal, phase difference 180 degrees. In a complete working cycle, there are 4 working stages, the working state of the device in each stage is shown in the following table.

[0061] For a switch, 1 represents on and 0 represents off.

[0062] stage state S1 S2 S3 S4 L1 C1 C2 C3 Phase 1 State 1 0 1 0 1 Energy Storage constant Discharge Charge Phase II State 2 1 1 0 0 Freewheeling Charge constant constant Phase 3 State 3 1 0 1 0 Energy Storage Charge constant Discharge Stage 4 State 2 1 1 0 0 Freewheeling Charge constant constant

[0063] refer to Figure 4 In the current loop shown, in the first stage: S1 is turned off, S2 is turned on, S3 is turned off; S4 is turned on; during this process, the first inductor L1 stores energy, the third capacitor C3 is charged, the second capacitor C2 is discharged, and the first capacitor C1 remains unchanged. The circuit works in state 1.

[0064] refer to Figure 5 The current loop shown, the second stage: S1 is turned on, S2 is turned on, S3 is turned off; S4 is turned off; in this process, the first inductor L1 continues to release energy, the voltage of the third capacitor C3 remains unchanged, the second capacitor C2 remains unchanged, and the first capacitor C1 is charged. The circuit works in state 2.

[0065] refer to Figure 6 The current loop shown, the third stage: S1 is turned on, S2 is turned off, S3 is turned on; S4 is turned off; during this process, the first inductor L1 stores energy, the third capacitor C3 discharges, the second capacitor C2 remains unchanged, and the first capacitor C1 continues to charge. The circuit works in state 3.

[0066] refer to Figure 5 The current loop shown, the fourth stage: S1 is turned on, S2 is turned on, S3 is turned off; S4 is turned off; in this process, the first inductor L1 continues to release energy, the voltage of the third capacitor C3 remains unchanged, the voltage of the second capacitor C2 remains unchanged, and the first capacitor C1 continues to charge. The circuit works in state 2.

[0067] There are four stages in one cycle, and the energy transfer process is: in the first stage, the second capacitor C2 discharges, and the energy is transferred to the first inductor L1 and the third capacitor C3 respectively; from the second to the fourth stage, the first inductor L1 and the third capacitor C3 transfer the energy to the first capacitor C1 respectively, completing the voltage balancing process of the second capacitor C2 and the first capacitor C1.

[0068] Optionally, refer to Figures 7 to 10 As shown, when the output voltage of the three-level balancing circuit is less than half of the DC voltage, the balancing circuit controller drives the first complementary switch group and the second complementary switch group to make the duty cycle of the first switch S1 less than 50%, so that the three-level balancing circuit works in the buck charging mode. It should be understood that the specific working process also uses the on-time of S1 as the duty cycle. The driving waveform timing reference issued by the balancing circuit controller Figure 7 As shown in the figure: S1 and S4 are driven complementary, S2 and S3 are driven complementary, the duty cycles of S1 and S2 are equal, and the phase difference is 180 degrees. In a complete working cycle, the working state is divided into 4 stages in sequence, and the working state of the device in each stage is shown in the following table. For a switch, 1 represents on and 0 represents off.

[0069] stage state S1 S2 S3 S4 L1 C1 C2 C3 Phase 1 State 1 1 0 1 0 Energy Storage Phase II State 2 0 0 1 1 Freewheeling Phase 3 State 3 0 1 0 1 Energy Storage Paragraph 4 State 2 0 0 1 1 Freewheeling

[0070] refer to Figure 8 The current loop shown, the first stage: S1 is turned on, S2 is turned off, S3 is turned on; S4 is turned off; in this process, the first inductor L1 stores energy, the third capacitor C3 discharges, the second capacitor C2 discharges, and the first capacitor C1 charges. The circuit works in state 1.

[0071] refer to Fig. 9 The current loop shown, the second stage: S1 is turned off, S2 is turned off, S3 is turned on; S4 is turned on; in this process, the first inductor L1 continues to release energy, the voltage of the third capacitor C3 remains unchanged, the second capacitor C2 continues to discharge, and the first capacitor C1 continues to charge. The circuit works in state 2.

[0072] refer to Fig.10 The current loop shown, the third stage: S1 is turned off, S2 is turned on, S3 is turned off; S4 is turned on; in this process, the first inductor L1 stores energy, the third capacitor C3 is charged, the second capacitor C2 is discharged, and the first capacitor C1 is charged. The circuit works in state 3.

[0073] refer to Fig. 9 The current loop shown, the fourth stage: S1 is turned off, S2 is turned off, S3 is turned on; S4 is turned on; in this process, the first inductor L1 continues to release energy, the voltage of the third capacitor C3 remains unchanged, the second capacitor C2 is discharged, and the first capacitor C1 is charged. The circuit works in state 2.

[0074] Similarly, in one cycle, the energy transfer process is as follows: in the first process, the first capacitor C1 is discharged, and the energy is transferred to the first inductor L1 and the third capacitor C3 respectively; in the second to fourth stages, the first inductor L1 and the third capacitor C3 transfer the energy to the second capacitor C2 respectively, thus completing the voltage balancing process of the first capacitor C1 and the second capacitor C2.

[0075] Optionally, refer to Figure 1 As shown, when the voltage difference between the output voltage of the three-level balancing circuit and half of the DC voltage is within a preset threshold range, the balancing circuit controller turns off the driving of the first complementary switch group and the second complementary switch group. It should be understood that the preset threshold range can be adjusted according to the magnitude of the DC voltage. When the bus voltage difference is within the threshold range, the balancing circuit controller turns off the driving of the first complementary switch group and the second complementary switch group, reducing system losses by sacrificing a little balance.

[0076] Optionally, refer to Fig.12 and Fig.14As shown, a neutral line is connected between the first capacitor C1 and the second capacitor C2 of the voltage balancing circuit, and the neutral line is not connected to the busbar. It should be understood that if the neutral point of the three-phase inverter is not connected to the midpoint of the series voltage balancing capacitor, there will be no risk of voltage imbalance of the series voltage balancing capacitor. Usually, the capacity of the voltage balancing capacitor is equal. If the two midpoints are not connected together, the voltage of each capacitor is equal to half of the total DC input by default, and there will be no extra loops to flow current into or out of the first capacitor C1 and the second capacitor C2, so the first capacitor C1 and the second capacitor C2 will not cause uneven voltage. As long as the voltage at the midpoint of the three-phase inverter is controlled to be half of the voltage of the total DC input, the potential of the midpoint of the capacitor can be kept the same as the potential of the neutral point of the three-phase inverter, which is equivalent to connecting the two midpoints together, but it will not cause capacitor uneven voltage.

[0077] Optionally, refer to Fig.11 As shown, the three-level balancing circuit also includes a pre-charging circuit, which includes a resistor R and a reverse diode D connected in series in sequence, one end of the pre-charging circuit is connected between the first capacitor C1 and the second capacitor C2, and the other end of the pre-charging circuit is connected between the third switch S3 and the fourth switch S4, which is used to pre-charge the third capacitor C3 to half of the DC voltage. It should be understood that in order to allow the three-level balancing circuit to work from startup to normal operation, the average voltage of the third capacitor C3 is half of the total input voltage, and the resistor R and the reverse diode D are used as a pre-charging circuit to charge the third capacitor C3 to half of the bus voltage. At startup, S1 is first turned on, and the current flows through S1, the third capacitor C3, D, and R back to the midpoint of the series capacitor. Since the voltage at the midpoint of the series capacitor is equal to half of the input voltage, the voltage of the first capacitor C1 is only half of the input voltage, that is, the desired target voltage.

[0078] Optionally, refer to Figure 1 and Fig.12As shown, the three-phase inverter circuit adopts an I-type three-level inverter, and the I-type three-level inverter includes: a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8 which are sequentially connected in series and then connected in parallel to a DC voltage, a ninth switch S9, a tenth switch S10, an eleventh switch S11 and a twelfth switch S12 which are sequentially connected in series and then connected in parallel to the DC voltage, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15 and a sixteenth switch S16 which are sequentially connected in series and then connected in parallel to the DC voltage; a first diode D1 and a second diode D2 which are sequentially connected in series and then connected in reverse parallel to the sixth switch S6 and the seventh switch The two ends of the switch S7 are connected, the first diode D1 and the second diode D2 are connected to the first capacitor C1 and the second capacitor C2; the third diode D3 and the fourth diode D4 are connected in series in sequence and then reversely connected in parallel to the two ends of the tenth switch S10 and the eleventh switch S11, and the third diode D3 and the fourth diode D4 are connected to the first capacitor C1 and the second capacitor C2; the fifth diode D5 and the sixth diode D6 are connected in series in sequence and then reversely connected in parallel to the two ends of the fourteenth switch S14 and the fifteenth switch S15, and the fifth diode D5 and the sixth diode D6 are connected to the first capacitor C1 and the second capacitor C2.

[0079] One end of the second inductor L2 is connected between the sixth switch S6 and the seventh switch S7, and the other end of the second inductor L2 serves as the output of one phase among the three phases; one end of the third inductor L3 is connected between the tenth switch S10 and the eleventh switch S11, and the other end of the third inductor L3 serves as the output of one phase among the three phases; one end of the fourth inductor L4 is connected between the fourteenth switch S14 and the fifteenth switch S15, and the other end of the fourth inductor L4 serves as the output of one phase among the three phases; one end of the fourth capacitor C4 is connected to the other end of the second inductor L2, and the other end of the fourth capacitor C4 is connected to the bus; one end of the fifth capacitor C5 is connected to the other end of the third inductor L3, and the other end of the fifth capacitor C5 is connected to the bus; one end of the sixth capacitor C6 is connected to the other end of the fourth inductor L6, and the other end of the sixth capacitor C6 is connected to the bus.

[0080] It should be understood that when using a type I three-level inverter, the reference Figure 1 The midpoint of the grading capacitor and the busbar are connected to ground. Fig.12 The midpoint of the voltage-equalizing capacitor and the busbar are not grounded and are not connected to each other. By controlling the voltage of the midpoint of the three-phase inverter to half of the total DC input voltage, the potential of the midpoint of the capacitor can be kept the same as the potential of the neutral point of the three-phase inverter, which is equivalent to connecting the two midpoints together, but will not cause capacitor voltage inequality.

[0081] Optionally, refer to Fig.13 and Fig.14As shown, the three-phase inverter circuit adopts a T-type three-level inverter, and the T-type three-level inverter includes: a fifth switch S5 and an eighth switch S8 which are sequentially connected in series and then connected in parallel to a DC voltage; a sixth switch S6 and a seventh switch S7 are connected in series, one end of which is connected between the fifth switch S5 and the eighth switch S8, and the other end is connected between the first capacitor C1 and the second capacitor C2 through grounding; a ninth switch S9 and a twelfth switch S12 which are sequentially connected in series and then connected in parallel to a DC voltage; a tenth switch S10 and an eleventh switch S11 which are connected in series, one end of which is connected between the ninth switch S9 and the twelfth switch S12, and the other end is connected between the first capacitor C1 and the second capacitor C2 through grounding; a thirteenth switch S13 and a sixteenth switch S16 which are sequentially connected in series and then connected in parallel to a DC voltage; a fourteenth switch S14 and a fifteenth switch S15 which are connected in series, one end of which is connected between the thirteenth switch S13 and the sixteenth switch S16, and the other end is connected between the first capacitor C1 and the second capacitor C2 through grounding.

[0082] One end of the second inductor L2 is connected between the fifth switch S5 and the eighth switch S8, and the other end of the second inductor L2 serves as the output of one phase among the three phases; one end of the third inductor L3 is connected between the ninth switch S9 and the twelfth switch S12, and the other end of the third inductor L3 serves as the output of one phase among the three phases; one end of the fourth inductor L4 is connected between the thirteenth switch S13 and the sixteenth switch S16, and the other end of the fourth inductor L4 serves as the output of one phase among the three phases; one end of the fourth capacitor C4 is connected to the other end of the second inductor L2, and the other end of the fourth capacitor C4 is connected to the bus; one end of the fifth capacitor C5 is connected to the other end of the third inductor L3, and the other end of the fifth capacitor C5 is connected to the bus; one end of the sixth capacitor C6 is connected to the other end of the fourth inductor L4, and the other end of the sixth capacitor C6 is connected to the bus.

[0083] It should be understood that when using a T-type three-level inverter, the reference Fig.13 The midpoint of the grading capacitor and the busbar are connected to ground. Fig.14 The midpoint of the voltage-equalizing capacitor is grounded, while the busbar is not grounded, and the midpoint of the voltage-equalizing capacitor and the busbar are not connected to each other. This can prevent current from flowing in and out of the voltage-equalizing capacitor, and prevent the capacitor from being unbalanced when the three-phase inverter carries a three-phase unbalanced load. As long as the potential of the neutral point of the three-phase inverter is controlled to be equal to the potential of the midpoint of the voltage-equalizing capacitor, it can be equivalent to being connected together.

[0084] Furthermore, in this example implementation, based on the same concept, an energy storage system is also provided, including: an input power supply, a load, and a three-phase four-wire inverter circuit, wherein the three-phase four-wire inverter circuit adopts any of the three-phase four-wire inverter circuits described above.

[0085] It should be understood that the implementation of the part of the energy storage system involving the three-phase four-wire inverter circuit can refer to the implementation of the above-mentioned three-phase four-wire inverter circuit, and the repeated parts will not be repeated.

[0086] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and implementation modes are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A three-phase four-wire inverter circuit, It is characterized in that include: A voltage balancing circuit, the voltage balancing circuit comprising: a first capacitor and a second capacitor connected in series and connected in parallel to both ends of a DC voltage; A three-phase inverter circuit, which is connected in parallel to both ends of the DC voltage and outputs a three-phase AC voltage and a bus; A three-level balancing circuit, the three-level balancing circuit comprising: a third capacitor, a first inductor, and a first switch, a second switch, a third switch, and a fourth switch which are sequentially connected in series and connected in parallel to a DC voltage; wherein two ends of the third capacitor are connected in parallel to two ends of the second switch and the third switch; one end of the first inductor is connected between the second switch and the third switch, and the other end of the first inductor is connected to the bus as an output of the three-level balancing circuit; A balancing circuit controller, the balancing circuit controller is used to make the first switch and the fourth switch serve as a first complementary switch group, the second switch and the third switch serve as a second complementary switch group, the first complementary switch group and the second complementary switch group have a phase difference of 180 degrees; and keep the output voltage of the three-level balancing circuit equal to half of the DC voltage.

2. The three-phase four-wire inverter circuit according to claim 1, It is characterized in that When the output voltage of the three-level balancing circuit is greater than half of the DC voltage, the balancing circuit controller drives the first complementary switch group and the second complementary switch group so that the duty cycle of the on-time of the first switch is greater than 50%, so that the three-level balancing circuit operates in a boost discharge mode.

3. The three-phase four-wire inverter circuit according to claim 1, It is characterized in that When the output voltage of the three-level balancing circuit is less than half of the DC voltage, the balancing circuit controller drives the first complementary switch group and the second complementary switch group so that the duty cycle of the on-time of the first switch is less than 50%, so that the three-level balancing circuit operates in a buck charging mode.

4. The three-phase four-wire inverter circuit according to claim 1, It is characterized in that When the voltage difference between the output voltage of the three-level balancing circuit and half of the DC voltage is within a preset threshold range, the balancing circuit controller turns off driving the first complementary switch group and the second complementary switch group.

5. The three-phase four-wire inverter circuit according to claim 1, It is characterized in that A neutral line is connected between the first capacitor and the second capacitor of the voltage balancing circuit, and the neutral line is connected to the busbar by grounding.

6. The three-phase four-wire inverter circuit according to claim 1, It is characterized in that A neutral line is connected between the first capacitor and the second capacitor of the voltage balancing circuit, and the neutral line and the busbar are not connected to each other.

7. The three-phase four-wire inverter circuit according to any one of claims 1 to 6, It is characterized in that The three-level balancing circuit also includes a pre-charging circuit, which includes a resistor and a reverse diode connected in series in sequence, one end of the pre-charging circuit is connected between the first capacitor and the second capacitor, and the other end of the pre-charging circuit is connected between the third switch and the fourth switch, for pre-charging the third capacitor to half of the DC voltage.

8. The three-phase four-wire inverter circuit according to any one of claims 1 to 6, It is characterized in that The three-phase inverter circuit adopts an I-type three-level inverter, which includes: a fifth switch, a sixth switch, a seventh switch and an eighth switch which are sequentially connected in series and then connected in parallel to a DC voltage, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch which are sequentially connected in series and then connected in parallel to the DC voltage, and a thirteenth switch, a fourteenth switch, a fifteenth switch and a sixteenth switch which are sequentially connected in series and then connected in parallel to the DC voltage; a first diode and a second diode which are sequentially connected in series and then connected in reverse parallel to both ends of the sixth switch and the seventh switch, and a connection between the first diode and the second diode and between the first capacitor and the second capacitor; a third diode and a fourth diode which are sequentially connected in series and then connected in reverse parallel to both ends of the tenth switch and the eleventh switch, and a connection between the third diode and the fourth diode and between the first capacitor and the second capacitor; a fifth diode and a sixth diode which are sequentially connected in series and then connected in reverse parallel to both ends of the fourteenth switch and the fifteenth switch, and a connection between the fifth diode and the sixth diode and between the first capacitor and the second capacitor; One end of the second inductor is connected between the sixth switch and the seventh switch, and the other end of the second inductor serves as the output of one phase among the three phases; one end of the third inductor is connected between the tenth switch and the eleventh switch, and the other end of the third inductor serves as the output of one phase among the three phases; one end of the fourth inductor is connected between the fourteenth switch and the fifteenth switch, and the other end of the fourth inductor serves as the output of one phase among the three phases; one end of the fourth capacitor is connected to the other end of the second inductor, and the other end of the fourth capacitor is connected to the bus; one end of the fifth capacitor is connected to the other end of the third inductor, and the other end of the fifth capacitor is connected to the bus; one end of the sixth capacitor is connected to the other end of the fourth inductor, and the other end of the sixth capacitor is connected to the bus.

9. The three-phase four-wire inverter circuit according to any one of claims 1 to 6, It is characterized in that The three-phase inverter circuit adopts a T-type three-level inverter, and the T-type three-level inverter includes: a fifth switch and an eighth switch which are sequentially connected in series and then connected in parallel to a DC voltage, a sixth switch and a seventh switch which are connected in series and then have one end connected between the fifth switch and the eighth switch, and the other end connected between the first capacitor and the second capacitor by grounding; a ninth switch and a twelfth switch which are sequentially connected in series and then connected in parallel to a DC voltage, a tenth switch and an eleventh switch which are connected in series and then have one end connected between the ninth switch and the twelfth switch, and the other end connected between the first capacitor and the second capacitor by grounding; a thirteenth switch and a sixteenth switch which are sequentially connected in series and then connected in parallel to a DC voltage, a fourteenth switch and a fifteenth switch which are connected in series and then have one end connected between the thirteenth switch and the sixteenth switch, and the other end connected between the first capacitor and the second capacitor by grounding; One end of the second inductor is connected between the fifth switch and the eighth switch, and the other end of the second inductor serves as the output of one phase among the three phases; one end of the third inductor is connected between the ninth switch and the twelfth switch, and the other end of the third inductor serves as the output of one phase among the three phases; one end of the fourth inductor is connected between the thirteenth switch and the sixteenth switch, and the other end of the fourth inductor serves as the output of one phase among the three phases; one end of the fourth capacitor is connected to the other end of the second inductor, and the other end of the fourth capacitor is connected to the bus; one end of the fifth capacitor is connected to the other end of the third inductor, and the other end of the fifth capacitor is connected to the bus; one end of the sixth capacitor is connected to the other end of the fourth inductor, and the other end of the sixth capacitor is connected to the bus.

10. An energy storage system, It is characterized in that include: An input power supply, a load and a three-phase four-wire inverter circuit, wherein the three-phase four-wire inverter circuit adopts the three-phase four-wire inverter circuit according to any one of claims 1 to 9.

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