Electronic device, device and sensor

Abstract

The utility model relates to electronic equipment and a sensor. An electronic device includes a first diffusion resistor; and a second diffusion resistor; wherein the first diffusion resistor and the second diffusion resistor are in contact with each other to form a PN junction; wherein the PN junction is reversely biased; and wherein the potential difference between the first resistor and the second resistor is constant at any point of the PN junction. The electronic equipment is used in the field of electronic or electrical elements. The utility model aims to solve all or part of defects of known equipment comprising a diffusion resistor.

Description

[0001] Priority declaration

[0002] This application claims priority to French patent application No. 2302099, filed on March 7, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to devices including resistors and control methods thereof. Background Art

[0004] A resistor is an electronic or electrical component whose main characteristic is a higher or lower resistance against the flow of electric current. In integrated circuit technology, two main types of resistors are known: polysilicon resistors and diffused or implanted resistors, i.e., using different types (usually P and N) of dopants in a semiconductor substrate (usually made of silicon). The present disclosure relates to the second type of resistors (i.e., diffused or implanted integrated circuit resistors).

[0005] There is a need in the art to address all or some of the disadvantages of known devices including diffused resistors. Utility Model Content

[0006] The object of the present invention is to provide a technically improved electronic device, device and sensor, thereby solving all or part of the disadvantages of known devices including diffused resistors.

[0007] An embodiment provides an electronic device comprising a first diffused resistor and a second diffused resistor contacting each other to form a PN junction, the device being configured so that a potential difference between the first resistor and the second resistor is constant at any point of the PN junction, the device being configured to reverse bias the PN junction.

[0008] Preferably, each of the first diffused resistor and the second diffused resistor is made of a doped semiconductor material, the first diffused resistor and the second diffused resistor being doped with opposite conductivity types.

[0009] Preferably, the first diffused resistor includes a first layer and a first well buried in the substrate, the first well extending from the periphery of the first layer to the first surface of the substrate, the first layer and the first well being made of a doped semiconductor material of a first conductivity type; and the second diffused resistor includes a second layer resting on the first layer, the second layer being made of a doped semiconductor material of a second conductivity type.

[0010] Preferably, the second diffused resistor comprises a third doped semiconductor layer of the first conductivity type, the third layer being flush with the upper surface of the substrate; and the first diffused resistor comprises a second layer made of a doped semiconductor material of the second conductivity type, the third layer resting on the second layer.

[0011] Preferably, the device also includes a third diffused resistor, which includes a first layer and a first well buried in the substrate, the first well extending from the periphery of the first layer to the first surface of the substrate, the first layer and the first well are made of doped semiconductor material of the first conductivity type, and the first layer and the first well define the second layer.

[0012] Preferably, the PN junctions serving as the first and third resistors are configured to be reverse biased.

[0013] Preferably, the first diffused resistor comprises a semiconductor well in the substrate, which is doped with a type opposite to that of the substrate; and the second diffused resistor comprises a third doped semiconductor layer of a type opposite to that of the semiconductor well, the third layer being flush with the upper surface of the substrate.

[0014] Preferably, each of the diffused resistors comprises a first end and a second end, each diffused resistor comprising, at the level of the first end and the second end, a semiconductor region that is more heavily doped than the rest of the resistor, thereby forming terminals of said diffused resistor.

[0015] Preferably, each of the first diffused resistor and the second diffused resistor comprises a first terminal and a second terminal, the second terminals of the first diffused resistor and the second diffused resistor being coupled to a same first node to which a reference voltage is applied.

[0016] Preferably, the device comprises a control circuit configured to supply a potential across the terminals of the first and second resistors.

[0017] Preferably, the control circuit includes a first transistor coupled in series with a first resistor between a second node of application of a power supply voltage and the first node and a second transistor coupled in series with a second resistor between the second node and the first node, the first transistor and the second transistor being diode mounted.

[0018] Preferably, the channel width-to-length ratio of the first transistor is equal to the channel width-to-length ratio of the second transistor multiplied by a quotient of a value of the second resistor and a value of the first resistor.

[0019] Preferably, the device is configured so that the potential difference between the first resistor and the second resistor is zero at any point of the PN junction.

[0020] Another embodiment provides a sensor comprising a device such as previously described, the sensor being configured such that a measured value of the sensor depends on the resistance value of a second resistor.

[0021] Another embodiment provides a device comprising a first region of doped semiconductor material having a first conductivity type; a second region of doped semiconductor material having a second conductivity type opposite to the first conductivity type; a first electrical contact located at a first end of the first region; a second electrical contact located at a second end of the first region; wherein the first region forms a first diffused resistor between the first electrical contact and the second electrical contact; a third electrical contact located at the first end of the second region; a fourth electrical contact located at the second end of the second region; wherein the second region forms a second diffused resistor between the third electrical contact and the fourth electrical contact; wherein the first region contacts the second region to form a PN junction; wherein a first voltage difference is applied between the first terminal and the second terminal; wherein the second voltage difference is applied between the third terminal and the fourth terminal; and wherein the first voltage difference and the second voltage difference are configured such that the PN junction is reverse biased.

[0022] Preferably, the device further comprises a control circuit configured to supply a first voltage difference between the first terminal and the second terminal and a second voltage difference between the third terminal and the fourth terminal.

[0023] Preferably, the device further comprises a first transistor coupled in series with the first diffusion resistor between the power supply voltage and the first terminal; and a second transistor coupled in series with the second diffusion resistor, the power supply node and the third terminal.

[0024] Preferably, the first transistor and the second transistor are each diode-connected transistors.

[0025] Preferably, the first transistor has a first channel width-to-length ratio, and the second transistor has a second channel width-to-length ratio different from the first channel width-to-length ratio.

[0026] Preferably, the difference between the first channel width-to-length ratio and the second channel width-to-length ratio is a function of a quotient of a resistance of the second diffusion resistor and a resistance of the first diffusion resistor.

[0027] Another embodiment provides a sensor comprising a device such as previously described, the sensor being configured such that a measured value of the sensor depends on the resistance value of one of a first diffused resistor and a second diffused resistor.

[0028] Another embodiment provides a method of controlling a device, the device comprising a first diffused resistor and a second diffused resistor contacting each other to form a PN junction, the potential difference between the first resistor and the second resistor being constant at any point of the PN junction, the device being configured to reverse bias the PN junction. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of this disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0030] Figure 1A is a top view of an embodiment of a device including a diffused resistor;

[0031] Figure 1B yes Figure 1A A cross-sectional view of an embodiment of the present invention;

[0032] Figure 1C yes Figure 1A Another cross-sectional view of an embodiment of;

[0033] Figure 2A is a top view of another embodiment of a device including a diffused resistor;

[0034] Figure 2B yes Figure 2A A cross-sectional view of an embodiment of the present invention;

[0035] Figure 2C yes Figure 2A A cross-sectional view of an embodiment of the present invention;

[0036] Figure 2D yes Figure 2A A cross-sectional view of an embodiment of the present invention;

[0037] Figure 3 An example of a circuit including a diffused resistor is shown;

[0038] Figure 4 Another circuit including a diffused resistor is shown;

[0039] Figure 5 The application of the aforementioned embodiment is shown;

[0040] Fig. 6A is a top view of another embodiment of a device including a diffused resistor;

[0041] Figure 6B yes Fig. 6A A cross-sectional view of an embodiment of; and

[0042] Figure 6C yes Fig. 6A A cross-sectional view of an embodiment of the present invention. DETAILED DESCRIPTION

[0043] Similar features are denoted by similar reference numerals in the various drawings. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties.

[0044] For clarity, only the steps and elements that are useful for understanding the described embodiments are illustrated and described in detail.

[0045] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0046] In the following description, when referring to terms defining absolute positions (such as terms “front”, “back”, “up”, “down”, “left”, “right”, etc.) or terms defining relative positions (such as terms “above”, “below”, “upper”, “lower”, etc.) or terms defining directions (such as terms “horizontal”, “vertical”, etc.), unless otherwise specified, it refers to the orientation of the drawing.

[0047] Unless otherwise specified, the expressions “about”, “approximately”, “substantially” and “around” mean plus or minus 10%, preferably plus or minus 5%.

[0048] A diffusion (or implantation) resistor is formed in a semiconductor substrate, such as one made of silicon, with a region generally extending as a rod of a first conductivity type (P or N) in a well or substrate of a second conductivity type (N or P). The contact regions at both ends of the rod define the terminals of the resistor and the well is biased so that the PN junction is reverse biased.

[0049] In addition to other problems caused by the presence of the PN junction and the need to reverse bias this junction to obtain the resistance effect between the two ends of the rod, diffused resistors also suffer from the lack of stability of the resistance value with voltage changes. In other words, the resistance value changes with the voltage applied across it.

[0050] The described embodiments provide for making the value of a diffused (or implanted) resistor voltage-stable, ie making the resistance value independent of the potential applied across it.

[0051] According to the described embodiment, a bias is provided for the area around the resistor rod (well and buried area) to compensate for the voltage instability effect. More particularly, a specific bias is provided for the area around the resistor rod so that the potential difference at the level of each point of the interface between the resistor rod and the surrounding area is constant between the resistor rod and the surrounding area. Thus, the voltage gradient generated in the longitudinal direction in the area around the resistor rod is the same as the voltage gradient generated in the resistor rod. Then the potential difference between the resistor rod and the area of ​​the opposite type surrounding it is obtained, which is constant regardless of the longitudinal position between the two terminals of the resistor rod. This is equivalent to using the longitudinal resistance of the area with the opposite conductivity type where the resistor rod is located (in the direction of the resistor rod). Thereby avoiding the change of the space charge volume between the P region and the N region in the longitudinal direction of the resistor rod, which makes the resistance value independent of the voltage applied to each of its terminals. In other words, the resistor has a value independent of the potential at its two ends and therefore independent of the potential difference at its two ends.

[0052] Figure 1A is a top view of an embodiment of device 10 . Figure 1B It is along Figure 1A A cross-sectional view of line BB. Figure 1C It is along Figure 1A Cross-sectional view of line CC.

[0053] The device 10 comprises a substrate 14 (P-) made of a semiconductor material, such as silicon. The substrate 14 is doped, preferably of the P type.

[0054] The device 10 comprises a well 18 of a conductivity type (N) opposite to that of the substrate 14, and a layer 16 or plate of the same conductivity type (N) as the well buried below the well 18 in the substrate 14. The well 18 is, for example, a ring of rectangular shape. The well 18 and the buried region 16 delimit on the front surface side a region 26 of the substrate of the first conductivity type (P-) forming the resistor bar 12. The well 18 and the region 16 form another resistor 12'.

[0055] The layer 16 is formed into, for example, a strip. The layer 16 has, for example, a shape approximately equal to a rectangular parallelepiped. The well 18 has a shape of a rectangular ring extending from the front surface or upper surface of the substrate 14 to the buried layer 16. The well 18 includes a first end 18a and a second end 18b. The first end 18a and the second end 18b preferably correspond to two opposite sides of the well 18 that are farthest from each other.

[0056] The front surface of the substrate and therefore of the device 10 is covered by an insulating layer 15. More precisely, the layer 15 preferably partially covers the upper surface of the substrate 14. For greater clarity, Figure 1A Layer 15 is not shown.

[0057] Contact regions 20 and 24 are provided in the respective vicinity of the longitudinal ends of well 18 and region 26. Regions 20 and 24 are overdoped with N+ and P+, respectively, and contacts 22 and 28 define terminals for electrical connection of respective regions 20 and 24.

[0058] An example of a method of forming the device 10 includes forming a well 18 in a semiconductor substrate, for example doped of P type. The formation of the well 18 is performed, for example, by a doping step, for example through an opening of a mask located on the upper surface of the substrate. The doping step causes the well to extend from the upper surface of the substrate. The method then includes a step of forming a layer 16, for example by implanting a doping through an opening of another mask located on the upper surface of the substrate. The layer 16 is formed in such a way that it extends partially in the well 18. Thus, there is electrical continuity between the layer 16 and the well 18.

[0059] For example, layer 15 is formed after forming well 18. Layer 15 corresponds to shallow trench insulation (STI), for example. Layer 15 is formed, for example, by a known shallow trench insulation formation method, for example, including the formation of a mask that exposes the position of layer 15, partial etching of the substrate, and filling the obtained cavity with an insulating material. Alternatively, the material of layer 15 can be obtained from the material of the substrate, for example, by oxidation.

[0060] At the level of the ends 18a and 18b of the well 18, the layer 15 comprises openings 19a and 19b intended for forming a contact area 20 flush with the upper surface of the substrate. Preferably, the thickness of the area 20 is less than the height of the layer 15.

[0061] Similarly, layer 15 is open near the end of region 26 for forming contact region 24 and contact 28. In other words, layer 15 comprises openings 19c and 19d intended for forming contact region 24 flush with the upper surface of the substrate. Preferably, the thickness of region 24 is less than the height of layer 15.

[0062] The method of manufacturing the device 10 comprises, for example, a step of forming the region 20, for example by doping the substrate through an opening of another mask situated on the upper surface of the substrate. More precisely, the formation of the region 20 comprises doping a portion of the well 18 flush with the upper surface of the substrate. Preferably, the opening of the mask completely exposes the openings 19a and 19b.

[0063] Well 18 and layer 16 form resistor 12'. Resistor 12' is a diffusion resistor of conductivity type N. Region 20 located in opening 19a forms a first terminal B1 of resistor 12'. Region 20 located in opening 19b forms a second terminal B2 of resistor 12'. Contact 22 is intended to contact region 20 to couple resistor 12' to an electronic circuit. The value of resistor 12' corresponds to the resistance between terminals B1 and B2. The X direction extending from terminal B1 to terminal B2 corresponds to the main direction of resistor 12' and is Figure 1A and 1C The arrow in indicates.

[0064] The method of manufacturing the device 10 comprises, for example, a step of forming the region 24, for example by doping the substrate through openings of a mask located on the upper surface of the substrate. Preferably, the openings of the mask completely expose the openings 19c and 19d.

[0065] Region 26 forms resistor 12. Resistor 12 is a diffusion resistor of conductivity type P. Region 24 located in opening 19c forms a first terminal A1 of resistor 12. Region 24 located in opening 19d forms a second terminal A2 of resistor 12. Contact 28 is intended to contact region 24 to couple resistor 12 to an electronic circuit. The value of resistor 12 corresponds to the resistance between terminals A1 and A2. The main direction of resistor 12 is the same X direction as the main direction of resistor 12'.

[0066] Thus, the resistor 12 is separated from the rest of the P-doped substrate 14 by the resistor 12'. The resistor 12 is separated from the rest of the P-doped substrate by a structure formed by a well 18 and a layer 16, known in the art as a triple well. The resistors 12 and 12' are in contact with each other. More precisely, the resistor 12 rests on the resistor 12'.

[0067] The resistors 12 and 12' are diffused resistors of opposite conductivity types. The resistors 12 and 12', and more precisely the interface between the resistors 12 and 12', form a PN junction.

[0068] Reference symbol VA refers to the voltage applied between the terminals of the resistor 12, that is, the potential difference VA1-VA2 between the terminals A1 and A2, and VB refers to the voltage applied between the terminals of the resistor 12', that is, the potential difference VB1-VB2 between the terminals B1 and B2, and the voltage differences VB1-VA1 and VB2-VA2 are configured so that the PN junction formed between the resistors 12 and 12' is reverse biased. In other words, at each contact point P between the resistor 12 and the resistor 12', the potential VAP of the resistor 12 at the point P is less than or equal to the potential VBP of the resistor 12' at the point P. Reverse bias will also include a case where the PN junction is zero biased (in other words, a case where the potential difference is substantially equal to zero).

[0069] The device is also configured so that the difference between the potential of resistor 12' and the potential of resistor 12 is constant over the entire interface between resistors 12 and 12' in the X direction. In other words, at any point P of the interface between resistor 12 and resistor 12', the difference between the potential VAP (i.e., the potential of resistor 12 at point P) and the potential VBP (i.e., the potential of resistor 12' at point P) is substantially equal to a constant value k. Therefore, the device is configured so that the following equation applies over the entire interface between resistor 12 and resistor 12' in the X direction: VAP-VBP=k. The k value is a constant, positive or zero value, and is independent of the voltage values ​​VA and VB. In particular, this equation applies to the levels of terminals A1, A2, B1, B2. Therefore, the following equation applies in the device: VA1-VB1=VA2-VB2=k.

[0070] For example, the value k is strictly constant, strictly positive, and may include a value substantially equal to 0. Therefore, at any point P of the interface between resistor 12 and resistor 12', the potential VAP of resistor 12 is substantially equal to the potential VBP of resistor 12'.

[0071] The value of the resistor 12 is voltage-stable but not temperature-stable. Therefore, the above embodiment can be used as a temperature sensor. The resistor 12 then corresponds to a variable element of the sensor, and a change in the resistance value of the resistor 12 indicates a change measured by the sensor, such as a temperature change. For example, the sensor has an output having an output signal that depends on the resistance value generated by the resistor 12 thereon.

[0072] At least one end of each resistor 12, 12' is coupled and not connected to the relevant end of the other resistor 12, 12'. In other words, either the terminals A1 and B1 are coupled and not connected to each other, or the terminals A2 and B2 are coupled and not connected to each other, or the terminals A1 and B1 are coupled and not connected to each other, and the terminals A2 and B2 are coupled and not connected to each other. By coupled and not connected to each other, it is meant that the terminals (e.g., terminals A1 and B1) are not short-circuited. In other words, the terminals (e.g., terminals A1 and B1) are coupled by at least one electrical element. For example, the terminals are coupled by at least a transistor, a resistor (except resistors 12 and 12'), an amplifier, or any other electrical element that does not present a short-circuit connection. For example, each terminal is coupled to a source circuit that generates a bias voltage. The source circuits connected to the terminals are preferably different. The source circuits coupled to the terminals A1 and B1 are preferably independent of each other. Therefore, the terminals are configured to receive different voltages. In certain operating modes, these different voltages may have the same value, in which case the value k is equal to zero.

[0073] The advantage of biasing resistors 12 and 12' as described previously is that this makes the resistance value independent of the voltage applied to each of its terminals. In particular, this avoids thickness variations in the space charge region (i.e., a region without majority carriers and not participating in the conduction of the resistor). In a conventional diffused resistor, the greater the difference between the voltage VAP and the voltage VBP at a given point P of the interface between resistors 12 and 12', the greater the space charge region, which increases the resistance value. This dependence on the voltage applied to each terminal is particularly problematic when the resistor is used as a sensor (e.g., a temperature sensor). This space charge region does not appear in the Figures 1A to 1C and 2A to 2D.

[0074] Figure 2A is a top view of another embodiment of a device 30 having another diffused resistor 32 formed therein. Figure 2B yes Figure 2A An example along the lines of Figure 2A A cross-sectional view of line BB. Figure 2C It is along Figure 2A Cross-sectional view of line CC. Figure 2D It is along Figure 2A Cross-sectional view of plane DD.

[0075] Device 30 includes elements of device 10, which will not be described further. Specifically, device 30 includes substrate 14; layer 15, including openings 19a, 19b, 19c, and 19d; resistor 12', namely layer 16, well 18, and region 20; and resistor 12, namely region 26 and region 24.

[0076] The device 30 also includes a resistor 32 formed by N-type diffusion in the rod 12 from the front surface of the strip or region 36, so as to obtain a rectangular shape surrounded (on the sides and below) by the region 26. The layer 15 then includes an opening 34 located between the openings 19c and 19d. The opening 34 is separated from each of the openings 19c and 19d by a portion of the layer 15. The opening 34 is separated from each of the openings 19a and 19b by a portion of the layer 15 and the openings 19c or 19d. The strip 36 is flush with the upper surface of the substrate 14 in the opening 34.

[0077] The strip 36 has, for example, a rectangular parallelepiped shape. Figure 2A , the strip 36 has, for example, a rectangular shape. The strip 36 has a first end 36a and a second end 36b. The first end 36a and the second end 36b preferably correspond to two opposite sides of the strip 36 that are farthest from each other. A region 38 at the level of these ends 36a, 36b has the same N conductivity type and defines a contact region 40 intended to be coupled to an electronic circuit. The region 38 at the level of the end 36a forms the terminal C1 of the resistor 32. The region 38 at the level of the end 36b forms the terminal C2 of the resistor 32. Preferably, the strip 36 is not silicided outside the region 38. For example, the region 38 is silicided.

[0078] The value of the resistor 32 corresponds to the resistance between the terminals C1 and C2.

[0079] Reference symbol VC refers to the voltage across resistor 32, i.e., the potential difference VC1-VC2 between terminals C1 and C2, and reference symbol VA refers to the voltage applied across resistor 12, i.e., the potential difference VA1-VA2 between terminals A1 and A2. The device is configured so that the PN junction formed between resistors 12 and 32 is reverse biased. In other words, at each contact point P between resistor 12 and resistor 32, the potential VCP (i.e., the potential of resistor 32 at point P) is greater than the potential VAP (i.e., the potential of resistor 12 at point P). Therefore, the potential on terminal C1 is preferably higher than the voltage on terminal A1. Similarly, the potential on terminal C2 is preferably higher than the potential on terminal A2. Reverse bias will also include a situation where the PN junction is zero biased (in other words, a situation where the potential difference is substantially equal to zero).

[0080] The device is also configured so that the difference between the potential of resistor 32 and the potential of resistor 12 is constant across the interface between resistors 12 and 32 in the X direction. In other words, at any point P of the interface between resistor 12 and resistor 32, the difference between the potential VAP of resistor 12 and the potential VCP of resistor 32 is substantially equal to a constant value k. Therefore, the device is configured so that the following equation applies across the interface between resistor 12 and resistor 32 in the X direction: VAP-VCP=k. The value of k is a constant, positive or zero value, regardless of the voltage values ​​VA and VC.

[0081] For example, the value k is strictly constant, strictly positive, and may include a value substantially equal to zero. Thus, at any point P of the interface between resistor 12 and resistor 32 , the potential VAP of resistor 12 is substantially equal to the potential VCP of resistor 32 .

[0082] The device is configured so that the junction between the resistors 12 and 12' is not forward biased. The device is configured, for example, so that the junction between the resistors 12 and 12' is reverse biased. For example, the potentials VB1 and VB2 are equal to each other and equal to the maximum value between the potentials VA1 and VA2.

[0083] Figure 3 An example of a circuit including a diffused resistor is shown. More precisely, Figure 3 A delay generating circuit 42 including a diffused resistor 44 is shown.

[0084] The resistor 44 is, for example, Figures 1A to 1C Resistor 12 or FIG. 2A to FIG. 2D The resistor 32 corresponds to.

[0085] Device 42 includes transistor 46. Transistor 46 is, for example, an insulated gate field effect transistor or MOSFET transistor. Transistor 46 is, for example, a P-channel transistor.

[0086] Transistor 46 is coupled in series with resistor 44. Transistor 46 and resistor 44 are coupled in series between node 48 of application of power supply voltage VDD and node 50 of application of reference voltage (e.g., ground GND). Transistor 46 is coupled between node 48 and node 52. Resistor is coupled between node 52 and node 50. In other words, a conduction terminal (e.g., source) of transistor 46 is coupled, preferably connected, to node 48. Another conduction terminal (e.g., drain) of transistor 46 is coupled, preferably connected, to node 52. A terminal of resistor 44 (e.g., terminal A2 in the case of resistor 12 or terminal C2 in the case of resistor 32) is coupled, preferably connected, to node 52 and another terminal of resistor 44 (e.g., terminal A1 in the case of resistor 12 or terminal C1 in the case of resistor 32) is coupled, preferably connected, to node 50.

[0087] Transistor 46 is diode mounted. In other words, the control terminal (eg, gate) of transistor 46 is coupled, preferably connected, to the drain of transistor 46, i.e., coupled, for example,

[0088] Preferably connected, to node 52 .

[0089] Circuit 42 further includes transistor 54 and transistor 56. Transistor 54 is, for example, an insulated gate field effect transistor or a MOSFET transistor. Transistor 54 is, for example, a P-channel transistor. Transistor 56 is, for example, an insulated gate field effect transistor or a MOSFET transistor. Transistor 56 is, for example, an N-channel transistor.

[0090] Transistors 54 and 56 are coupled in series between node 48 and node 50. More precisely, transistor 54 is coupled between node 48 and node 58, and transistor 56 is coupled between node 58 and node 50. In other words, a conduction terminal (e.g., source) of transistor 54 is coupled, preferably connected, to node 48. Another conduction terminal (e.g., drain) of transistor 54 is coupled, preferably connected, to node 58. Additionally, a conduction terminal (e.g., drain) of transistor 56 is coupled, preferably connected, to node 58. Another conduction terminal (e.g., source) of transistor 56 is coupled, preferably connected, to node 50. Transistor 54 is coupled in a manner that conducts a copy of the current flowing through transistor 46.

[0091] Transistor 56 is diode mounted. In other words, the control terminal (e.g., gate) of transistor 56 is coupled, preferably connected, to the drain of transistor 56, i.e., for example, coupled, preferably connected, to node 58. In addition, the control terminal (e.g., gate) of transistor 54 is coupled, preferably connected, to node 52.

[0092] Circuit 42 further includes transistor 60 and transistor 62. Transistor 60 is, for example, an insulated gate field effect transistor or a MOSFET transistor. Transistor 60 is, for example, a P-channel transistor. Transistor 62 is, for example, an insulated gate field effect transistor or a MOSFET transistor. Transistor 62 is, for example, an N-channel transistor.

[0093] Transistors 60 and 62 are coupled in series between node 48 and node 50. More precisely, transistor 60 is coupled between node 48 and node 64, and transistor 62 is coupled between node 64 and node 50. In other words, a conduction terminal (e.g., source) of transistor 60 is coupled, preferably connected, to node 48. Another conduction terminal (e.g., drain) of transistor 60 is coupled, preferably connected, to node 64. Additionally, a conduction terminal (e.g., drain) of transistor 62 is coupled, preferably connected, to node 64. Another conduction terminal (e.g., source) of transistor 62 is coupled, preferably connected, to node 50.

[0094] A control terminal (e.g., gate) of transistor 60 is coupled, preferably connected, to node 52. A control terminal of transistor 62 is coupled, preferably connected, to an output of inverter 66. An input of inverter 66 is coupled, preferably connected, to input node 68. An input signal IN is applied to node 68. Transistor 60 is coupled in a manner that conducts a copy of the current flowing through transistor 46.

[0095] Circuit 42 further includes transistor 70 and transistor 72. Transistor 70 is, for example, an insulated gate field effect transistor or a MOSFET transistor. Transistor 70 is, for example, a P-channel transistor. Transistor 72 is, for example, an insulated gate field effect transistor or a MOSFET transistor. Transistor 72 is, for example, an N-channel transistor.

[0096] Transistors 70 and 72 are coupled in series between node 48 and node 50. More precisely, transistor 70 is coupled between node 48 and node 74, and transistor 72 is coupled between node 74 and node 50. In other words, a conduction terminal (e.g., source) of transistor 70 is coupled, preferably connected, to node 48. Another conduction terminal (e.g., drain) of transistor 70 is coupled, preferably connected, to node 74. Additionally, a conduction terminal (e.g., drain) of transistor 72 is coupled, preferably connected, to node 74. Another conduction terminal (e.g., source) of transistor 72 is coupled, preferably connected, to node 50.

[0097] A control terminal (eg, gate) of transistor 70 is coupled, preferably connected, to node 64. Transistor 72 is coupled in a manner that conducts a copy of the current across transistor 56.

[0098] Circuit 42 includes capacitor 76. Capacitor 76 is coupled between node 64 and node 50. In other words, a terminal of capacitor 76 is coupled, preferably connected, to node 64, and another terminal of capacitor 76 is coupled, preferably connected, to node 50.

[0099] Node 74 is coupled to an output node 78, and circuit 42 generates an output signal OUT at output node 78. Output signal OUT corresponds to input signal IN to which a delay has been applied. Node 74 is coupled to node 78 through inverter 80. In other words, the input terminal of inverter 80 is coupled, preferably connected, to node 74, and the output terminal of inverter 80 is coupled, preferably connected, to node 78.

[0100] Circuit 42 also includes transistor 82 and resistor 84. Resistor 84 is a diffusion resistor. Figures 1A to 1C In the case of an embodiment the resistor 12' or FIG. 2A to FIG. 2D The transistor 82 is, for example, an insulated gate field effect transistor or a MOSFET transistor. The transistor 82 is, for example, a P-channel transistor.

[0101] Transistor 82 and resistor 84 are coupled in series between node 48 and node 50. More precisely, transistor 82 is coupled between node 48 and node 86. Resistor 84 is coupled between node 86 and node 50. In other words, a conduction terminal (e.g., source) of transistor 82 is coupled, preferably connected, to node 48, and another conduction terminal (e.g., drain) of transistor 82 is coupled, preferably connected, to node 86. The terminals (e.g., Figures 1A to 1C The resistor 12' is at the terminal B2 or FIG. 2A to FIG. 2D In the case of the embodiment of the resistor 12, the terminal A2 is coupled, preferably connected, to the node 86 and the other terminal of the resistor 84 (e.g., Figures 1A to 1C The resistor 12' is at the terminal B1 or FIG. 2A to FIG. 2D In the case of the embodiment of the resistor 12 , the terminal A1 ) is coupled, preferably connected, to the node 50 .

[0102] Transistor 82 is diode mounted. In other words, the control terminal (eg, gate) of transistor 82 is coupled, preferably connected, to the drain of transistor 82 , ie, for example, coupled, preferably connected, to node 58 .

[0103] The size of transistor 82 (i.e., the width-to-length ratio of the channel) is configured so that the voltage across resistor 84 is substantially equal to the voltage across resistor 44. In other words, the size of transistor 82 is configured so that the potential difference between the terminals of resistor 84 is substantially equal to the potential difference between the terminals of resistor 44. For example, the size of the transistor is equal to the size of transistor 46 multiplied by the quotient Q of the resistance value of resistor 44 and the resistance value of resistor 84. For example, transistor 46 is formed from one or more basic transistors that are identical. Compared to transistor 46, transistor 82 is formed from Q times the identical basic transistors.

[0104] The delay generation circuit 42 is configured to apply a delay T to the signal. In other words, when the signal IN takes a value (eg, a binary value "1") at time t, the output signal OUT takes that value at time t+T.

[0105] During operation of the circuit, the current flowing through transistor 46 is equal to (VDD-VtP) / R, VtP corresponds to the threshold voltage of transistor 46 and R corresponds to the value of resistor 44. The current flowing through transistor 60 is proportional to the current flowing through transistor 46, with a ratio of 1 / n, where n is a positive integer, and transistors 46 and 60 are assembled as a current mirror.

[0106] If the input signal IN has a low value, ie a value corresponding to the binary value “0”, the transistor 62 is turned on and the capacitor 76 is discharged via the transistor 62 with a larger current than the current flowing through the transistor 60 .

[0107] If the input signal IN has a high value, i.e., a value corresponding to a binary value "1", the transistor 62 is not conducting. Therefore, the capacitor 76 is charged via the transistor 60. The voltage V across the capacitor 76 satisfies the following equation V(t)=t*(VDD-VtP) / (n*R*C), where C is the capacitance value of the capacitor 76.

[0108] When capacitor 76 starts to charge, voltage V is less than VDD-VtP, so transistor 70 is turned on and output signal OUT has a binary value of "0". When V reaches the value VDD-VtP, that is, when t=T=n*R*C, transistor 70 becomes non-conductive and output signal OUT takes a binary value of "1".

[0109] exist Figure 3In the example of , the circuit 42 is configured so that the potentials on the terminals A1 and B1 are equal to each other and equal to the voltage VDD-VtP, and the potentials on the terminals A2 and B2 are equal to each other and equal to zero voltage. For this purpose, both terminals A2 and B2 are coupled to the node 50. In order to determine that the potentials on the terminals A1 and B1 are equal, the current density flowing through the transistors 82 and 46 must be exactly the same. More precisely, if the transistors 46 and 82 each correspond to a plurality of basic transistors that are identical to each other, then the current density in each basic transistor must be the same. Therefore, the potential difference between the resistor 44 and the resistor 84 (which corresponds to the well in which the resistor 44 is formed) is constant and is zero at any point of the interface between the resistors 44 and 84.

[0110] An advantage of using a resistor according to the described embodiments is that this makes the generated delay independent of variations in the voltage applied across the resistor, and therefore independent of the supply voltage.

[0111] More generally, embodiments of circuits for biasing diffused resistors (such as those described with respect to Figures 1A to 2D Those described) include a resistor (such as Figures 1A to 1C The resistor 12 of the embodiment or Figures 2A to 2D 32 of the embodiment of the present invention), and a resistor coupled in series with a diode mounted transistor such as transistor 82 (such as Figures 1A to 1C The resistor 12' or FIG. 2A to FIG. 2D The resistor 12 of the embodiment).

[0112] Figure 4 Another circuit including a diffused resistor is shown. More precisely, Figure 4 A circuit is shown which enables the voltage across a diffused resistor to be determined as previously described.

[0113] Circuit 100 includes diffused resistors 102 and 104. Resistor 102 is, for example, Figures 1A to 1C Resistor 12 or FIG. 2A to FIG. 2D The resistor 104 corresponds to the resistor 32. Figures 1A to 1C In the case of the embodiment of the resistor 12 'or FIG. 2A to FIG. 2D The resistor 102 includes a terminal 106 and a terminal 108, and the terminal 106 is connected to the resistor 12 in the embodiment. Figures 1A to 1C The resistor 12 is connected to the terminal A1 or FIG. 2A to FIG. 2D The terminal C1 of the resistor 32 corresponds to the terminal 108. Figures 1A to 1C The resistor 12 is connected to the terminal A2 or FIG. 2A to FIG. 2D The resistor 104 includes a terminal 110 and a terminal 112. The terminal 110 corresponds to the terminal C2 of the resistor 32. Figures 1A to 1C In the case of an embodiment of the resistor 12', the terminal B1 or FIG. 2A to FIG. 2D The terminal A1 of the resistor 12 in the embodiment corresponds to the terminal 112, and the terminal 112 corresponds to the Figures 1A to 1C In the case of an embodiment of the resistor 12' the terminal B2 or FIG. 2A to FIG. 2D The terminal A2 of the resistor 12 in the embodiment corresponds to.

[0114] Terminal 106 is coupled to terminal 110 through a voltage follower circuit. Similarly, terminal 108 is coupled to terminal 112 through a voltage follower circuit.

[0115] exist Figure 4 In the example of , each follower circuit comprises an operational amplifier. More precisely, terminals 106 and 110 are coupled via an operational amplifier 114, and terminals 108 and 112 are coupled via an operational amplifier 116. Amplifier 114 comprises an output terminal coupled, preferably connected, to terminal 110. Amplifier 114 comprises an input terminal coupled, preferably connected, to terminal 106. Amplifier 114 comprises another input terminal coupled, preferably connected, to the output terminal of amplifier 114. Amplifier 116 comprises an output terminal coupled, preferably connected, to terminal 112. Amplifier 116 comprises an input terminal coupled, preferably connected, to terminal 108. Amplifier 116 comprises another input terminal coupled, preferably connected, to the output terminal of amplifier 116.

[0116] Figure 5 The application of the aforementioned embodiment is shown. More precisely, Figure 5 The device 120 is shown, which includes a plurality of devices 10, four devices 10, referenced 10a, 10b, 10c and 10d, as shown in FIG. Figure 5 as shown in .

[0117] Each device 10a, 10b, 10c, 10d is combined with Figures 1A to 1C As described above. Each device 10a, 10b, 10c and 10d includes a resistor 12 and a resistor 12'. More precisely, the devices 10a, 10b, 10c and 10d include a resistor 12a, 12b, 12c or 12d and a resistor 12'a, 12'b, 12'c or 12'd, respectively. Each resistor 12a, 12b, 12c or 12d includes terminals A1 and A2. Similarly, each resistor 12'a, 12'b, 12'c or 12'd includes terminals B1 and B2.

[0118] Devices 10a, 10b, 10c and 10d are coupled in series. More precisely, resistors 12a, 12b, 12c or 12d are coupled in series to form a resistor of greater value. For example, terminal A2 of resistor 12a is coupled, preferably connected, to terminal A1 of resistor 12b, terminal A2 of resistor 12b is coupled, preferably connected, to terminal A1 of resistor 12c, and terminal A2 of resistor 12c is coupled, preferably connected, to terminal A1 of resistor 12d.

[0119] In addition, the resistor 12' is coupled in series in the same manner as the resistor 12. In other words, for each terminal of the resistor 12 coupled, preferably connected, to a terminal of another resistor 12, the terminals B1, B2 of the resistor 12 closest to said terminal of the resistor 12 are coupled, preferably connected, to each other. Thus, the terminal B2 of the resistor 12'a is coupled, preferably connected, to the terminal B1 of the resistor 12'b, the terminal B2 of the resistor 12'b is coupled, preferably connected, to the terminal B1 of the resistor 12'c, and the terminal B2 of the resistor 12'c is coupled, preferably connected, to the terminal B1 of the resistor 12'd.

[0120] The coupling of the resistors makes it possible to ensure the constancy of the potential difference between each resistor 12 and the associated resistor 12 ′. Thus, the device 120 comprises a resistor equal to the sum of the resistance values ​​of the four resistors 12 between the terminal A1 of the resistor 12a and the terminal A2 of the resistor 12d.

[0121] Fig. 6A is a top view of another embodiment of a device 130 including a diffused resistor. Figure 6B yes Fig. 6A A cross-sectional view of an embodiment along line BB. Figure 6C yes Fig. 6A A cross-sectional view of an embodiment along line CC.

[0122] Device 130 includes Figures 1A to 1C The elements of the device 10 are not described in detail. The device 130 comprises: a substrate 14, doped at P type; a layer 15, including openings 19c, 19d; a region 24 in the openings 19c and 19d; and a contact 28.

[0123] Device 130 includes a well 132 in substrate 14. Well 132 is located on the front surface side of substrate 14. Well 132 is of the second conductivity type (N). Well 132 forms a resistor bar. Well 132 extends at least from region 24 in opening 19c to region 24 in opening 19d. Well 132 is in contact with region 24. Region 24 and well 132 form a diffused resistor 136.

[0124] Device 130 also includes a resistor 138, similar to FIG. 2A to FIG. 2D The resistor 32 is formed by a P-type diffusion in the well 132 from the front surface of the strip or region 140, so as to obtain a rectangle surrounded (on the sides and below) by the well 132. The layer 15 then comprises an opening 142 located between the openings 19c and 19d. The opening 142 is separated from each of the openings 19c and 19d by a portion of the layer 15. The strip 140 is flush with the upper surface of the substrate 14 in the opening 142.

[0125] The strip 140 is flush with the front surface of the substrate 14. The strip 140 has, for example, a rectangular parallelepiped shape. Fig. 6A , the strip 140 has, for example, a rectangular shape. The strip 140 has a first end 140a and a second end 140b. The first end 140a and the second end 140b preferably correspond to two opposite sides of the strip 140 that are farthest from each other. An area 144 at the level of these ends 140a, 140b has the same P conductivity type and defines a contact area intended to be coupled to an electronic circuit. The area 144 at the level of the end 140a forms the terminal C1 of the resistor 138. The area 144 at the level of the end 140b forms the terminal C2 of the resistor 138. Preferably, the strip 140 is not silicided outside the area 144. For example, the area 144 is silicided.

[0126] The value of resistor 138 corresponds to the resistance between terminals C1 and C2.

[0127] FIG. 6A to FIG. 6C The resistors 136 and 138 are configured to be respectively Figures 1A to 1C Resistors 12 ′ and 12 of device 10 are biased in the same manner.

[0128] An advantage of the described embodiment is that the value of the diffused resistor is independent of the value of the voltage at each terminal of the resistor, and therefore independent of the supply voltage.

[0129] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations can be combined, and those skilled in the art will recognize other variations.

[0130] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. An electronic device, characterized in that: The electronic device comprises: a first diffused resistor; and a second diffused resistor; wherein the first diffused resistor and the second diffused resistor contact each other to form a PN junction; wherein the PN junction is reverse biased; and The potential difference between the first resistor and the second resistor is constant at any point of the PN junction.

2. The device according to claim 1, characterized in that Each of the first diffused resistor and the second diffused resistor is made of a doped semiconductor material, and the first diffused resistor and the second diffused resistor are doped with opposite conductivity types.

3. The device according to claim 1, characterized in that The first diffused resistor includes a first layer and a first well buried in the substrate, the first well extending from the periphery of the first layer to the first surface of the substrate, the first layer and the first well being made of a doped semiconductor material of a first conductivity type; as well as The second diffused resistor includes a second layer resting on the first layer, the second layer being made of a doped semiconductor material of a second conductivity type opposite to the first conductivity type.

4. The device according to claim 1, characterized in that The second diffused resistor includes a third doped semiconductor layer of the first conductivity type, the third doped semiconductor layer being flush with the upper surface of the substrate; as well as The first diffused resistor includes a second layer made of a doped semiconductor material of a second conductivity type opposite to the first conductivity type, and a third doped semiconductor layer rests on the second layer.

5. The device according to claim 4, characterized in that The device also includes a third diffused resistor, which includes a first layer and a first well buried in the substrate, the first well extending from the periphery of the first layer to the first surface of the substrate, the first layer and the first well are made of a doped semiconductor material of the first conductivity type, and the first layer and the first well define the second layer.

6. The device according to claim 5, characterized in that A PN junction between the first resistor and the third resistor is configured to be reverse biased.

7. The device according to claim 1, characterized in that The first diffused resistor includes a semiconductor well in the substrate, the semiconductor well being doped with a doping type opposite to that of the substrate; as well as The second diffused resistor includes a third doped semiconductor layer of a doping type opposite to that of the semiconductor well, the third doped semiconductor layer being flush with an upper surface of the substrate.

8. The device according to claim 1, characterized in that Each of the diffused resistors comprises a first end and a second end, each diffused resistor comprising, at the level of the first end and the second end, a semiconductor region that is more heavily doped than the rest of the doped resistor, the more heavily doped semiconductor region forming a terminal of the diffused resistor.

9. The device according to claim 1, characterized in that Each of the first diffused resistor and the second diffused resistor includes a first terminal and a second terminal, and the second terminals of the first diffused resistor and the second diffused resistor are coupled to the same first node to which the reference voltage is applied.

10. The device according to claim 1, characterized in that The apparatus also includes a control circuit configured to supply a potential across terminals of the first diffused resistor and the second diffused resistor.

11. The device according to claim 10, characterized in that The control circuit includes a first transistor coupled in series with a first diffusion resistor between a second node to which a power supply voltage is applied and a first node, and a second transistor coupled in series with a second diffusion resistor between the second node and the first node, the first transistor and the second transistor being diode mounted.

12. The device according to claim 11, characterized in that The channel width-to-length ratio of the first transistor is equal to the channel width-to-length ratio of the second transistor multiplied by a quotient of a value of a second resistance of the second diffusion resistor and a value of a first resistance of the first diffusion resistor.

13. The device according to claim 1, characterized in that The device is configured so that the potential difference between the first resistor and the second resistor is zero at any point of the PN junction.

14. A sensor, characterized in that: The sensor include: The device according to claim 1, the sensor is configured so that a measured value of the sensor depends on a resistance value of one of the first diffused resistor and the second diffused resistor.

15. A device, characterized in that The device comprises: a first region of doped semiconductor material having a first conductivity type; a second region of doped semiconductor material having a second conductivity type opposite to the first conductivity type; a first electrical contact located at a first end of the first region; a second electrical contact located at the second end of the first region; wherein the first region forms a first diffused resistor between the first electrical contact and the second electrical contact; a third electrical contact located at the first end of the second region; a fourth electrical contact located at the second end of the second region; wherein the second region forms a second diffused resistor between the third electrical contact and the fourth electrical contact; wherein the first region contacts the second region to form a PN junction; wherein a first voltage difference is applied between the first terminal and the second terminal; wherein the second voltage difference is applied between the third terminal and the fourth terminal; and The first voltage difference and the second voltage difference are configured to cause the PN junction to be reverse biased.

16. The device according to claim 15, characterized in that The device also includes a control circuit configured to supply a first voltage difference between the first terminal and the second terminal and a second voltage difference between the third terminal and the fourth terminal.

17. The device according to claim 15, characterized in that The device also includes: a first transistor coupled in series with the first diffused resistor between a power supply voltage and the first terminal; and A second transistor is coupled in series with the second diffusion resistor, the power supply node and the third terminal.

18. The apparatus of claim 17, wherein the first transistor and the second transistor are each diode-connected transistors.

19. The device according to claim 17, characterized in that The first transistor has a first channel width-to-length ratio, and the second transistor has a second channel width-to-length ratio different from the first channel width-to-length ratio.

20. The device according to claim 19, characterized in that The difference between the first channel width-to-length ratio and the second channel width-to-length ratio is a function of a quotient of a resistance of the second diffusion resistor and a resistance of the first diffusion resistor.

21. A sensor, characterized in that: The sensor include: According to the device of claim 15, the sensor is configured so that a measured value of the sensor depends on a resistance value of one of the first diffused resistor and the second diffused resistor.

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