LDO (Low Dropout Regulator) integrated with programmable soft start circuit

Abstract

The utility model discloses a low dropout regulator (LDO) integrated with a programmable soft start circuit, which belongs to the technical field of low dropout regulators and comprises a bias circuit connected with an unbalanced comparator component, a main operational amplifier circuit and a switch tube component. The unbalanced comparator assembly is connected with the main operational amplifier circuit and the switch tube assembly, the main operational amplifier circuit is connected with a power tube assembly, the power tube assembly is connected with a feedback circuit, and the unbalanced comparator assembly, the main operational amplifier circuit and the power tube assembly are all connected with the switch tube assembly. By means of the mode, compared with a traditional soft start circuit, the LDO soft start circuit is beneficial to being integrated in the LDO; and secondly, the soft start time is programmable, so that the method can be applied to complex use scenes.

Description

Technical Field

[0001] The utility model relates to the technical field of low voltage dropout regulators, in particular to an LDO with an integrated programmable soft start circuit. Background Art

[0002] Since the reference voltage is powered on very quickly when the actual chip is powered on, the module using this reference voltage is prone to trigger an ampere-level startup peak current; secondly, the output end of the low-voltage difference linear voltage regulator is generally designed with a microfarad-level output capacitor, which requires a large current to charge it, so it will also trigger an ampere-level capacitor charging current; excessive current can easily burn the circuit, so it is necessary to design a soft-start circuit. Traditional soft-start circuits often require the design of complex startup timing or the use of large inductance and large capacitance devices, which has a large layout area overhead and is not conducive to integration into the LDO; secondly, traditional soft-start circuits have a fixed soft-start time and a single usage scenario, which is not conducive to the requirements of different soft-start times in complex application scenarios.

[0003] For example, Chinese patent CN209327893U discloses a low voltage dropout regulator with a soft start circuit, the low voltage dropout regulator comprising: a differential amplifier; a channel transistor, the channel transistor is coupled to the output portion of the differential amplifier, wherein the channel transistor is configured to provide the output voltage of the LDO regulator; and a soft start circuit, the soft start circuit is coupled to the differential amplifier.

[0004] However, this technology has the following problems, which is not conducive to integration into the LDO; secondly, the soft start time is not programmable, which is not conducive to application in complex usage scenarios.

[0005] Based on this, the utility model designs an LDO with an integrated programmable soft start circuit to solve the above problems. Utility Model Content

[0006] In view of the above-mentioned shortcomings of the prior art, the utility model provides an LDO with an integrated programmable soft-start circuit.

[0007] In order to achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] An LDO with an integrated programmable soft-start circuit comprises a bias circuit, wherein an unbalanced comparator component, a main operational amplifier circuit and a switch tube component are connected to the bias circuit; the unbalanced comparator component is connected to the main operational amplifier circuit and the switch tube component, the main operational amplifier circuit is connected to a power tube component, the power tube component is connected to a feedback circuit, and the unbalanced comparator component, the main operational amplifier circuit and the power tube component are all connected to the switch tube component.

[0009] Furthermore, the bias circuit includes P1, P3, P8, P9, N0, N1, N2, N3, N19 and IDC; the gate of P1, the drain of P1, the gate of P3, the gate of P8, and the gate of P9 are short-circuited, the gate of P9 is connected to the main operational amplifier circuit, the gate of N0 and the drain of N0 are electrically connected to the gate of N1, the drain of P1 is electrically connected to the drain of N1, the source of N1 is electrically connected to the drain of N3, the gate of N3 is electrically connected to the drain of N2 and the drain-gate of N2, the drain of P8 is electrically connected to the drain of N19, the gate of N19 is connected to the main operational amplifier circuit, the IDC, the gate of P1, and the gate of P3 are all connected to the switch tube component, the drain of P3 is connected to the unbalanced comparator component, the drain of P9 is electrically connected to the main operational amplifier circuit, and the IDC is a connector.

[0010] Furthermore, the unbalanced comparator component includes P4, P5, P6, P7, N6, N7, N8, N9, N11, N12, N13, N14, N15, N16, N17 and N18; the source of P4, the source of P5, the source of P6 and the source of P7 are electrically connected, the gate of P4, the gate of P5 and the gate of P7 are electrically connected to the drain of P3, the gate of P4 and the gate of P6 are electrically connected to the main operational amplifier circuit, the drain of P4, the drain of P5 and the drain of P7 are electrically connected to the drain of N6, the gate of N7 and the gate of N9, the source of N6 is electrically connected to the drain of N7, the source of N8 is electrically connected to the drain of N9, and the gate of N6 is electrically connected to the drain of N7. The gate is electrically connected to the gate of N8 and the gate of N19, the gate of N7 is electrically connected to the gate of N9, the gate of N7 and the gate of N9 are both connected to the switch tube assembly, the drain of P6 is electrically connected to the drain of N8, the drain of N11, the gate of N11, the drain of N13, the gate of N13, the drain of N15, the gate of N15, the gate of N16, the drain of N17, the gate of N17, and the gate of N18, the source of N8 is electrically connected to the drain of N9, the source of N11 is electrically connected to the drain of N12, the source of N13 is electrically connected to the drain of N14, the source of N15 is electrically connected to the drain of N16, and the source of N17 is electrically connected to the drain of N18.

[0011] Furthermore, the main operational amplifier circuit includes P10, P11, P12, N22, N23, N21, N24, N26, N28, N29, N30, N31 and R0; the gate of P10 is electrically connected to P6, the source of P10 is electrically connected to the drain of P9 and the source of P11, the drain of P9 is electrically connected to the source of P11, the gate of P11 is electrically connected to the gate of P4, the drain of P10 is electrically connected to the drain of N22, the gate of N21, and the gate of N24, the gate of N22 is electrically connected to the gate of N23, the drain of N23 is electrically connected to the drain of P11 and the gate of N29, The drain of N23 is connected to the switch tube assembly, the source of N23 is electrically connected to the drain of N24, the gate of N24 is electrically connected to the gate of N21, the gate of N24 and the gate of N21 are both connected to the switch tube assembly, the gate of N26 is electrically connected to the gate of N17, the drain of N26 is electrically connected to the gate of P12, the drain of P12 is electrically connected to the drain of N28 and R0, the drain of P12 is connected to the switch tube assembly, R0 is electrically connected to the drain of N30, the source of N28 is electrically connected to the drain of N29, the source of N30 is electrically connected to the drain of N31, and the gate of N31 is electrically connected to the source of N0 and the drain of N2.

[0012] Furthermore, the power tube assembly includes P15, and the P15 is connected to both the feedback circuit and the switch tube assembly.

[0013] Furthermore, the feedback circuit includes R1 and R2, and the drain of P15, the gate of P4, the gate of P5, the gate of P7, the gate of P11, the negative end of R1, and the positive end of R2 are short-circuited.

[0014] Furthermore, the switch tube assembly includes P0, P2, P13, P14, N4, N5, N10, N20 and N27, the source of P0 is electrically connected to IDC, the gate of P0 is electrically connected to the drain of N0, the gate of N0, the source of N5, the gate of N28, and the gate of N30, the gate of N2 is electrically connected to the gate of N3 and the drain of N4, the source of N4 is electrically connected to the gate of N5, the gate of N10, the gate of N20, the gate of N25, the gate of N27, the gate of P0 The drain of P2 is electrically connected to the gate of P1 and the gate of P3, the drain of P13 is electrically connected to the drain of P12 and the gate of P14, the drain of P14 is electrically connected to the gate of P5 and the drain of N30, the drain of N10 is electrically connected to the gates of N7 and N9, the drain of N20 is electrically connected to the gate of N19, the drain of N25 is electrically connected to the gate of N21 and the gate of N24, and the drain of N27 is electrically connected to the gate of N29.

[0015] Furthermore, the gate of P1, the drain of P1, the gate of P3, the gate of P8, the gate of P9, and the gate of P12 are short-circuited to form a first current mirror bias circuit; the gate of N0, the drain of N0, the gate of N1, the gate of N28, and the gate of N30 are short-circuited to form a second current mirror bias circuit; the gate of N2, the drain of N2, the gate of N3, and the gate of N31 are short-circuited to form a third current mirror bias circuit.

[0016] Furthermore, the IDC, the source of P1, the source of P2, the source of P3, the source of P8, the source of P9, the source of P12, the source of P13, the source of P14, and the source of P15 are all connected to a high level.

[0017] Furthermore, the source of N2, the drain of N4, the source of N3, the drain of N5, the source of N7, the drain of N10, the source of N9, the source of N12, the source of N14, the source of N16, the source of N18, the source of N19, the source of N20, the source of N21, the source of N25, the source of N24, the source of N27, the source of N26, the source of N29, the source of N31, and R2 are all grounded.

[0018] The utility model has the following technical effects:

[0019] 1. When the utility model is in the initial state, when the power supply and the enable signal EN are at a high level, the gate of the switch tube P0 is at a high level; the gate of P2 and the gate of P13 are both at a low level; the gate of N4, the gate of N5, the gate of N10, the gate of N20, and the gate of N27 are all at a high level; the LDO output is at zero potential relative to the ground.

[0020] 2. When the utility model is in the on state, when the power supply and the enable signal jump from high level to low level, the gate of the switch tube P0 is low level; the gate of P2 and the gate of P13 are both high level; the gate of N4, the gate of N5, the gate of N10, the gate of N20, and the gate of N27 are all low level; the potential of the LDO output to the ground gradually rises, and when the LDO is truly transiently powered on, the branches P14, R0, N30, and N31 in the main loop generate current, and the drain potential of P14 is determined; the drain potential of P14 gives the gate potential of the power tube P15; therefore, the drain-source voltage of the power tube P15 is determined, so the initial transient startup current is preliminarily determined; in the unbalanced comparator loop, the positive input terminals are P4, P5, and P7; the negative input terminal is P6; when the LDO is truly transiently powered on, V REF The voltage value is higher than V FB , so the output is high level; as the power supply voltage is powered on V FBIt gradually builds up and rises, so the output of the unbalanced differential op amp gradually decreases; the output of the unbalanced comparator gives the gate bias of N26, and the current generated by N26 gradually decreases as the power supply voltage is powered on; the current generated by N26 gradually decreases as the power supply voltage is powered on; then the gate potential of P12 is pulled down; the gate potential of P12 is pulled down, then the gate bias of P14 and P15 is raised, and finally, the gate bias of P15 of the power tube gradually builds up slowly from high to low, so the startup current of LDO is limited by the soft-start circuit to achieve slow start; among them, the soft-start time can be programmable by turning on or off the gate bias K0 and K1 of N12 and N14. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 This is an overall circuit diagram of an LDO with an integrated programmable soft-start circuit of the utility model;

[0023] Figure 2 A circuit diagram of a bias circuit of the utility model;

[0024] Figure 3 It is a circuit connection diagram of the unbalanced comparator component of the utility model;

[0025] Figure 4 A circuit diagram of the main operational amplifier circuit of the utility model;

[0026] Figure 5 A circuit diagram of a power tube assembly and a feedback circuit of the utility model;

[0027] Figure 6 This is a circuit connection diagram of the switch tube assembly of the utility model;

[0028] Figure 7 It is a transient power-on simulation curve diagram of the utility model;

[0029] Figure 8 It is a programmable simulation curve diagram of the soft start of the utility model;

[0030] Fig. 9 It is a simulation curve diagram of the input voltage fillable range of the utility model;

[0031] Fig.10 It is a load modulation simulation curve diagram of the utility model;

[0032] Fig.11 It is a simulation curve diagram of the amplitude-frequency characteristic of the utility model;

[0033] Fig.12 It is a transient response simulation curve diagram of the utility model;

[0034] Fig.13 This is a simulation curve diagram of the power supply rejection ratio of the utility model.

[0035] The numbers in the figure represent:

[0036] 1. Bias circuit; 2. Unbalanced comparator assembly; 3. Main op amp circuit; 4. Power tube assembly; 5. Feedback circuit; 6. Switch tube assembly. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0038] The utility model is further described below in conjunction with embodiments.

[0039] Example 1

[0040] Please refer to the instruction manual Figure 1-13 , an LDO with an integrated programmable soft-start circuit, comprising a bias circuit 1, to which an unbalanced comparator component 2, a main operational amplifier circuit 3 and a switch tube component 6 are connected; the unbalanced comparator component 2 is connected to the main operational amplifier circuit 3 and the switch tube component 6, the main operational amplifier circuit 3 is connected to a power tube component 4, the power tube component 4 is connected to a feedback circuit 5, and the unbalanced comparator component 2, the main operational amplifier circuit 3, and the power tube component 4 are all connected to the switch tube component 6.

[0041] Compared with the traditional soft start circuit, the utility model is advantageous for integration into the LDO; secondly, the soft start time is programmable, which is advantageous for application in complex usage scenarios.

[0042] Example 2

[0043] like Figure 1-13As shown, as a preferred embodiment of the utility model, the bias circuit 1 includes P1, P3, P8, P9, N0, N1, N2, N3, N19 and IDC; the gate of P1, the drain of P1, the gate of P3, the gate of P8 and the gate of P9 are short-circuited, the gate of P9 is connected to the main operational amplifier circuit 3, the gate of N0 and the drain of N0 are electrically connected to the gate of N1, the drain of P1 is electrically connected to the drain of N1, the source of N1 is electrically connected to the drain of N3, the gate of N3 is electrically connected to the drain of N2 and the drain-gate of N2, the drain of P8 is electrically connected to the drain of N19, the gate of N19 is connected to the main operational amplifier circuit 3, the IDC, the gate of P1 and the gate of P3 are all connected to the switch tube component 6, the drain of P3 is connected to the unbalanced comparator component 2, the drain of P9 is electrically connected to the main operational amplifier circuit 3, and the IDC is a connector.

[0044] The unbalanced comparator component 2 includes P4, P5, P6, P7, N6, N7, N8, N9, N11, N12, N13, N14, N15, N16, N17 and N18; the source of P4, the source of P5, the source of P6 and the source of P7 are electrically connected, the gate of P4, the gate of P5 and the gate of P7 are all electrically connected to the drain of P3, the gate of P4 and the gate of P6 are all connected to the main operational amplifier circuit 3, the drain of P4, the drain of P5 and the drain of P7 are all electrically connected to the drain of N6, the gate of N7 and the gate of N9, the source of N6 is electrically connected to the drain of N7, the source of N8 is electrically connected to the drain of N9, the gate of N6 is electrically connected to the drain of N7, the gate ... The gate of N8 and the gate of N19 are both electrically connected, the gate of N7 and the gate of N9 are both electrically connected, the gate of N7 and the gate of N9 are both connected to the switch tube component 6, the drain of P6 and the drain of N8, the drain of N11, the gate of N11, the drain of N13, the gate of N13, the drain of N15, the gate of N15, the gate of N16, the drain of N17, the gate of N17, and the gate of N18 are all electrically connected, the source of N8 is electrically connected to the drain of N9, the source of N11 is electrically connected to the drain of N12, the source of N13 is electrically connected to the drain of N14, the source of N15 is electrically connected to the drain of N16, and the source of N17 is electrically connected to the drain of N18.

[0045] The main operational amplifier circuit 3 includes P10, P11, P12, N22, N23, N21, N24, N26, N28, N29, N30, N31 and R0; the gate of P10 is electrically connected to P6, the source of P10 is electrically connected to the drain of P9 and the source of P11, the drain of P9 is electrically connected to the source of P11, the gate of P11 is electrically connected to the gate of P4, the drain of P10 is electrically connected to the drain of N22, the gate of N21 and the gate of N24, the gate of N22 is electrically connected to the gate of N23, the drain of N23 is electrically connected to the drain of P11 and the gate of N29, and the gate of N23 is electrically connected to the drain of P11 and the gate of N29. The drain is connected to the switch tube component 6, the source of N23 is electrically connected to the drain of N24, the gate of N24 is electrically connected to the gate of N21, the gate of N24 and the gate of N21 are both connected to the switch tube component 6, the gate of N26 is electrically connected to the gate of N17, the drain of N26 is electrically connected to the gate of P12, the drain of P12 is electrically connected to the drain of N28 and R0, the drain of P12 is connected to the switch tube component 6, R0 is electrically connected to the drain of N30, the source of N28 is electrically connected to the drain of N29, the source of N30 is electrically connected to the drain of N31, and the gate of N31 is electrically connected to the source of N0 and the drain of N2.

[0046] The power tube assembly 4 includes P15, and the P15 is connected to both the feedback circuit 5 and the switch tube assembly 6.

[0047] The feedback circuit 5 includes R1 and R2, and the drain of P15, the gate of P4, the gate of P5, the gate of P7, the gate of P11, the negative end of R1, and the positive end of R2 are short-circuited.

[0048] The switch tube assembly 6 includes P0, P2, P13, P14, N4, N5, N10, N20 and N27, the source of P0 is electrically connected to IDC, the gate of P0 is electrically connected to the drain of N0, the gate of N0, the source of N5, the gate of N28 and the gate of N30, the gate of N2 is electrically connected to the gate of N3 and the drain of N4, the source of N4 is electrically connected to the gate of N5, the gate of N10, the gate of N20, the gate of N25, the gate of N27, the gate of P0, The gate of P2 and the gate of P13 are electrically connected, the drain of P2 is electrically connected to the gate of P1 and the gate of P3, the drain of P13 is electrically connected to the drain of P12 and the gate of P14, the drain of P14 is electrically connected to the gate of P5 and the drain of N30, the drain of N10 is electrically connected to the gates of N7 and N9, the drain of N20 is electrically connected to the gate of N19, the drain of N25 is electrically connected to the gate of N21 and the gate of N24, and the drain of N27 is electrically connected to the gate of N29.

[0049] When the power supply and enable signal EN are at high levels, the gate of the switch tube P0 is at a high level; the gates of P2 and P13 are both at a low level; the gates of N4, N5, N10, N20, and N27 are all at a high level, and the LDO output is at zero potential relative to ground.

[0050] like Figure 7 The figure shows the transient power-on simulation curve of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. In the figure, solid line 1 is the output voltage of LDO, dotted line 2 is the output current of power tube, and dotted horizontal line 3 is the output current of soft start tube. According to the simulation waveform, when the transient time is 94uS, the output voltage of LDO is 4.00V. When LDO is powered on with no load, the maximum transient current of power tube is 1.341A. When LDO is powered on with no load, the output current of soft start tube gradually decreases linearly from 47uA to 11pA.

[0051] like Figure 8 The figure shows the soft-start programmable simulation curve of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. In the figure above, solid line 2 is the output voltage VOUT0 of LDO, dotted line 3 is the output voltage VOUT1 of LDO, and dotted horizontal line 1 is the output voltage VOUT2 of LDO. According to the simulation waveform, when the soft-start time is 36uS, LDO successfully outputs an output voltage VOUT0 of 4V; when the soft-start time is 60uS, LDO successfully outputs an output voltage VOUT1 of 4V; when the soft-start time is 87uS, LDO successfully outputs an output voltage VOUT2 of 4V.

[0052] like Fig. 9 The figure shows the simulation curve of the adjustable input voltage range of the LDO. The simulation settings are tt process angle, 25°C, power supply voltage range of 0-5.5V, and output current of 0mA. The solid line in the figure above is the output voltage of the LDO. According to the simulation curve, when the power supply voltage is 4.07V, the output voltage of the LDO is 4.00952V; when the power supply voltage is 5.50V, the output voltage of the LDO is 4.00955V. Therefore, the adjustable input voltage range of the LDO is 4.07-5.50V, and the output voltage error is 32.44uV.

[0053] like Fig.10 The figure shows the load modulation simulation curve of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. The curve in the figure is the output voltage waveform of the low-dropout linear regulator. According to the simulation waveform, when the output current is 0mA, the output voltage is 4.00712V; when the output current is 200mA, the output voltage is 4.00604V. Therefore, when the output current of the low-dropout linear regulator is within 200mA, the output voltage fluctuation range is only 1.08mV.

[0054] like Fig.11 The figure shows the simulation curve of the amplitude-frequency characteristics of LDO. The simulation settings are tt process angle, 25°C, power supply voltage of 5V, and output current range of 0mA. The solid line 1 in the figure above is the loop gain, and the dotted line 2 is the phase margin. According to the simulation waveform, the low-frequency loop gain of the bandgap reference is 79.11dB, the unit gain bandwidth is 10.55KHz, and the phase margin is 90°.

[0055] like Fig.12 The figure shows the transient response simulation curve of LDO. The simulation environment is set to tt process angle, 25℃, and power supply voltage of 5V. Curve 1 in the upper figure is the output current change waveform of the low voltage difference linear regulator, and curve 2 in the lower figure is the output voltage waveform of the low voltage difference linear regulator. According to the simulation waveform, when the output current jumps from 0mA to 200mA within 1us, the minimum undershoot voltage of the output voltage is 3.984V; when the output current jumps from 200mA to 0mA within 1us, the minimum overshoot voltage of the output voltage is 4.030V; during the output current jump process, the minimum output voltage of LDO is 3.984V, the maximum output voltage is 4.030V, and the standard output voltage is 4.000V.

[0056] like Fig.13 Shown is a simulation curve of the power supply rejection ratio of LDO. The simulation settings are tt process angle, 25°C, power supply voltage of 5V, and output current range of 0mA. The solid line in the figure above is the power supply rejection ratio of LDO. According to the simulation waveform, when the frequencies are 100Hz, 1KHz, 100KHz, and 1.0mHz, the power supply rejection ratios of LDO are 112.0dB, 112.0dB, 115.5dB, and 94.7dB respectively.

[0057] Example 3

[0058] like Figure 1-13 As shown, as a preferred embodiment of the utility model, the gate of P1, the drain of P1, the gate of P3, the gate of P8, the gate of P9, and the gate of P12 are short-circuited to form a first current mirror bias circuit; the gate of N0, the drain of N0, the gate of N1, the gate of N28, and the gate of N30 are short-circuited to form a second current mirror bias circuit; the gate of N2, the drain of N2, the gate of N3, and the gate of N31 are short-circuited to form a third current mirror bias circuit.

[0059] The IDC, the source of P1, the source of P2, the source of P3, the source of P8, the source of P9, the source of P12, the source of P13, the source of P14, and the source of P15 are all connected to a high level.

[0060] The source of N2, the drain of N4, the source of N3, the drain of N5, the source of N7, the drain of N10, the source of N9, the source of N12, the source of N14, the source of N16, the source of N18, the source of N19, the source of N20, the source of N21, the source of N25, the source of N24, the source of N27, the source of N26, the source of N29, the source of N31, and R2 are all grounded.

[0061] When the power supply and enable signal jump from high level to low level, the gate of the switch tube P0 is low level; the gate of P2 and the gate of P13 are both high level; the gate of N4, the gate of N5, the gate of N10, the gate of N20, and the gate of N27 are all low level; the LDO output ground potential gradually rises. When the LDO is truly transiently powered on, the P14, R0, N30, and N31 branches in the main loop generate current, the drain potential of P14 is determined, and the drain potential of P14 gives the gate potential of the power tube P15; therefore, the drain-source voltage of the power tube P15 is determined, so the initial transient startup current is preliminarily determined; in the unbalanced comparator loop, the non-inverting input terminal is P4, P5, and P7; the inverting input terminal is P6; when the LDO is truly transiently powered on, V REF The voltage value is higher than V FB , so the output is high level; as the power supply voltage is powered on V FB It gradually builds up and rises, so the output of the unbalanced differential op amp gradually decreases; the output of the unbalanced comparator gives the gate bias of N26, and the current generated by N26 gradually decreases as the power supply voltage is powered on; the current generated by N26 gradually decreases as the power supply voltage is powered on; then the gate potential of P12 is pulled down; the gate potential of P12 is pulled down, so the gate bias of P14 and P15 is raised; finally, the gate bias of P15 of the power tube gradually builds up slowly from high to low, so the startup current of the LDO is limited by the soft-start circuit to achieve slow start; among them, the soft-start time can be programmable by turning on or off the gate bias K0 and K1 of N12 and N14.

[0062] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An LDO with an integrated programmable soft-start circuit, comprising a bias circuit (1), characterized in that: The bias circuit (1) is connected to an unbalanced comparator component (2), a main operational amplifier circuit (3) and a switch tube component (6); the unbalanced comparator component (2) is connected to the main operational amplifier circuit (3) and the switch tube component (6); the main operational amplifier circuit (3) is connected to a power tube component (4); the power tube component (4) is connected to a feedback circuit (5); and the unbalanced comparator component (2), the main operational amplifier circuit (3) and the power tube component (4) are all connected to the switch tube component (6).

2. The LDO with integrated programmable soft start circuit according to claim 1, characterized in that: The bias circuit (1) comprises P1, P3, P8, P9, N0, N1, N2, N3, N19 and an IDC; the gate of P1, the drain of P1, the gate of P3, the gate of P8 and the gate of P9 are short-circuited, the gate of P9 is connected to the main operational amplifier circuit (3), the gate of N0 and the drain of N0 are both electrically connected to the gate of N1, the drain of P1 is electrically connected to the drain of N1, the source of N1 is electrically connected to the drain of N3, the gate of N3 is electrically connected to the drain of N2 and the drain-gate of N2, the drain of P8 is electrically connected to the drain of N19, the gate of N19 is connected to the main operational amplifier circuit (3), the IDC, the gate of P1 and the gate of P3 are all connected to the switch tube component (6), the drain of P3 is connected to the unbalanced comparator component (2), the drain of P9 is electrically connected to the main operational amplifier circuit (3), and the IDC is a connector.

3. The LDO with integrated programmable soft start circuit according to claim 2, characterized in that: The unbalanced comparator component (2) comprises P4, P5, P6, P7, N6, N7, N8, N9, N11, N12, N13, N14, N15, N16, N17 and N18; the source of P4, the source of P5, the source of P6 and the source of P7 are electrically connected, the gate of P4, the gate of P5 and the gate of P7 are electrically connected to the drain of P3, the gate of P4 and the gate of P6 are electrically connected to the main operational amplifier circuit (3), the drain of P4, the drain of P5 and the drain of P7 are electrically connected to the drain of N6, the gate of N7 and the gate of N9, the source of N6 is electrically connected to the drain of N7, the source of N8 is electrically connected to the drain of N9. The gate of N6 is electrically connected to the gate of N8 and the gate of N19, the gate of N7 is electrically connected to the gate of N9, the gate of N7 and the gate of N9 are both connected to the switch tube component (6), the drain of P6 is electrically connected to the drain of N8, the drain of N11, the gate of N11, the drain of N13, the gate of N13, the drain of N15, the gate of N15, the gate of N16, the drain of N17, the gate of N17, and the gate of N18, the source of N11 is electrically connected to the drain of N12, the source of N13 is electrically connected to the drain of N14, the source of N15 is electrically connected to the drain of N16, and the source of N17 is electrically connected to the drain of N18.

4. The LDO with integrated programmable soft start circuit according to claim 3, characterized in that: The main operational amplifier circuit (3) comprises P10, P11, P12, N22, N23, N21, N24, N26, N28, N29, N30, N31 and R0; the gate of P10 is electrically connected to P6, the source of P10 is electrically connected to the drain of P9 and the source of P11, the drain of P9 is electrically connected to the source of P11, the gate of P11 is electrically connected to the gate of P4, the drain of P10 is electrically connected to the drain of N22, the gate of N21 and the gate of N24, the gate of N22 is electrically connected to the gate of N23, the drain of N23 is electrically connected to the drain of P11 and the gate of N29, the drain of N23 is electrically connected to the drain of The switch tube assembly (6) is connected to the source of N23 and the drain of N24. The gate of N24 and the gate of N21 are electrically connected to the switch tube assembly (6). The gate of N26 and the gate of N17 are electrically connected. The drain of N26 and the gate of P12 are electrically connected. The drain of P12 and the drain of N28 and R0 are electrically connected. The drain of P12 and the switch tube assembly (6) are connected. R0 and the drain of N30 are electrically connected. The source of N28 and the drain of N29 are electrically connected. The source of N30 and the drain of N31 are electrically connected. The gate of N31 and the source of N0 and the drain of N2 are electrically connected.

5. The LDO with integrated programmable soft start circuit according to claim 4, characterized in that: The power tube assembly (4) comprises P15, and the P15 is connected to both the feedback circuit (5) and the switch tube assembly (6).

6. The LDO with integrated programmable soft start circuit according to claim 5, characterized in that: The feedback circuit (5) comprises R1 and R2, and the drain of P15, the gate of P4, the gate of P5, the gate of P7, the gate of P11, the negative end of R1, and the positive end of R2 are short-circuited.

7. The LDO with integrated programmable soft start circuit according to claim 6, characterized in that: The switch tube assembly (6) comprises P0, P2, P13, P14, N4, N5, N10, N20 and N27, wherein the source of P0 is electrically connected to the IDC, the gate of P0 is electrically connected to the drain of N0, the gate of N0, the source of N5, the gate of N28 and the gate of N30, the gate of N2 is electrically connected to the gate of N3 and the drain of N4, the source of N4 is electrically connected to the gate of N5, the gate of N10, the gate of N20, the gate of N25, the gate of N27 and the gate of P0. , the gate of P2 and the gate of P13 are all electrically connected, the drain of P2 is electrically connected to the gate of P1 and the gate of P3, the drain of P13 is electrically connected to the drain of P12 and the gate of P14, the drain of P14 is electrically connected to the gate of P5 and the drain of N30, the drain of N10 is electrically connected to the gates of N7 and N9, the drain of N20 is electrically connected to the gate of N19, the drain of N25 is electrically connected to the gate of N21 and the gate of N24, and the drain of N27 is electrically connected to the gate of N29.

8. The LDO with integrated programmable soft start circuit according to claim 7, characterized in that: The gate of P1, the drain of P1, the gate of P3, the gate of P8, the gate of P9, and the gate of P12 are short-circuited to form a first current mirror bias circuit; the gate of N0, the drain of N0, the gate of N1, the gate of N28, and the gate of N30 are short-circuited to form a second current mirror bias circuit; the gate of N2, the drain of N2, the gate of N3, and the gate of N31 are short-circuited to form a third current mirror bias circuit.

9. The LDO with integrated programmable soft start circuit according to claim 8, characterized in that: The IDC, the source of P1, the source of P2, the source of P3, the source of P8, the source of P9, the source of P12, the source of P13, the source of P14, and the source of P15 are all connected to a high level.

10. The LDO with integrated programmable soft start circuit according to claim 9, characterized in that: The source of N2, the drain of N4, the source of N3, the drain of N5, the source of N7, the drain of N10, the source of N9, the source of N12, the source of N14, the source of N16, the source of N18, the source of N19, the source of N20, the source of N21, the source of N25, the source of N24, the source of N27, the source of N26, the source of N29, the source of N31, and R2 are all grounded.

Images