Power failure protection circuit

Abstract

The utility model discloses a power failure protection circuit. The circuit comprises a power supply module, a power failure detection module, a power supply delay module and a target chip, the power supply delay module comprises a capacitor; the power supply module comprises a power supply and a voltage stabilizing unit; the power failure detection module comprises a PNP triode, a first resistor and a voltage stabilizing diode, and the voltage of the power supply is greater than the breakdown voltage of the voltage stabilizing diode; the first pin of the target chip is connected with the output end of the power supply delay module; the output end of the power supply is connected with the input end of the voltage stabilizing unit and the cathode of the voltage stabilizing diode, and the output end of the voltage stabilizing unit is connected with one end of the power delay module; the anode of the voltage stabilizing diode is connected with the base electrode of the PNP triode, the emitting electrode of the PNP triode is connected with the output end of the power supply delay module through the first resistor, and the emitting electrode is further directly connected with a second pin of the target chip; an interrupt function used for storing data is stored in the target chip, and the second pin of the target chip is set as a falling edge to trigger the interrupt function. It can be seen that data storage does not need to be completed regularly, CPU occupation during normal operation is reduced, and operation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and more specifically, to a power-off protection circuit. Background Art

[0002] With the development of information technology, the functions of various electronic systems and circuits have become increasingly complex. In order to improve the reliability of various electronic systems and circuits, more and more electronic systems and circuits have added timed storage functions to save important data to avoid data loss caused by sudden power outages, so as to facilitate the electronic systems and circuits to maintain normal operation after power is restored.

[0003] However, saving data regularly requires the use of the CPU, which can easily cause the CPU to be occupied for too long, reducing the operating speed of electronic systems and circuits. Utility Model Content

[0004] In view of this, the present application provides a power-off protection circuit for solving the shortcomings of the prior art that the CPU is occupied for too long in data storage, thereby reducing the operating speed of the electronic system and circuit.

[0005] In order to achieve the above objectives, the proposed solution is as follows:

[0006] A power-off protection circuit comprises a power supply module, a power-off detection module, a power supply delay module and a target chip;

[0007] The power delay module includes a capacitor;

[0008] The power module includes a power supply and a voltage stabilizing unit;

[0009] The power failure detection module includes a PNP transistor, a first resistor and a voltage regulator diode, and the voltage of the power supply is greater than the breakdown voltage of the voltage regulator diode;

[0010] The first pin of the target chip is connected to the output end of the power delay module;

[0011] The output end of the power supply is connected to the input end of the voltage stabilizing unit and the cathode of the voltage stabilizing diode, and the output end of the voltage stabilizing unit is connected to one end of the power delay module;

[0012] The anode of the voltage stabilizing diode is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the output end of the power delay module through the first resistor, and the emitter is also directly connected to the second pin of the target chip;

[0013] An interrupt function for saving data is stored in the target chip, and the second pin of the target chip is set to trigger the interrupt function on a falling edge.

[0014] Optionally, the power delay module further includes a plurality of voltage drop diodes;

[0015] The voltage-drop diodes are connected in series.

[0016] Optionally, the power delay module includes a first voltage drop diode and a second voltage drop diode;

[0017] One end of the capacitor is connected to the cathode of the first voltage drop diode and the anode of the second voltage drop diode, and the other end is grounded.

[0018] Optionally, the power-off detection module further includes a second resistor;

[0019] The anode of the voltage stabilizing diode is connected to the base of the PNP transistor through the second resistor.

[0020] Optionally, the power-off detection module further includes a third resistor;

[0021] One end of the third resistor is connected to the second resistor and the base of the PNP transistor, and the other end is grounded.

[0022] Optionally, a memory chip is also included;

[0023] The storage chip is connected to the target chip, and is used for receiving and storing data transmitted by the interrupt function.

[0024] Optionally, the storage chip is an EEPROM chip.

[0025] Optionally, the storage chip is connected to the target chip via an I2 bus.

[0026] Optionally, the voltage stabilizing unit includes a voltage stabilizing integrated device, a first voltage stabilizing capacitor and a second voltage stabilizing capacitor;

[0027] The input end of the voltage stabilizing integrated device is connected to one end of a first voltage stabilizing capacitor and an output end of a power supply;

[0028] The output end of the voltage stabilizing integrated device is connected to one end of a second voltage stabilizing capacitor and a power supply delay module;

[0029] The other end of the first stabilizing capacitor and the other end of the second stabilizing capacitor are grounded.

[0030] Optionally, the voltage stabilizing integrated device is a three-terminal voltage stabilizing integrated device.

[0031] It can be seen from the above technical solutions that the power-off data preservation circuit provided by the present application includes a power supply module, a power-off detection module, a power delay module and a target chip. Under normal operating conditions, the power supply can provide energy for the entire power-off data preservation circuit. Since the output end of the voltage stabilizing unit is connected to one end of the power delay module and the first pin of the target chip is connected to the output end of the power delay module, the target chip is connected to the voltage stabilizing unit through the power delay module, and the voltage stability of the entire target chip can be maintained through the voltage stabilizing unit; at the same time, since the voltage of the power supply is greater than the breakdown voltage of the voltage stabilizing diode in the power-off detection module and the output end of the power supply is connected to the cathode of the voltage stabilizing diode, the voltage across the voltage stabilizing diode is greater than its breakdown voltage, and the voltage stabilizing diode is in a reverse conduction state; subsequently, since the anode of the voltage stabilizing diode is connected to the base of the PNP transistor, the current flows from the voltage stabilizing diode to the PNP transistor, and at this time, the PNP transistor is in a cut-off state; then, since the emitter of the PNP transistor is connected to the other end of the power delay module through the first resistor, the emitter is also directly connected to the second pin of the target chip; therefore, the voltage of the second pin of the target chip is affected by the first resistor and is at a high level; at the same time, since the power delay module contains a capacitor, and the capacitor is an energy storage element, therefore, when the power supply is operating normally, the capacitor can store electrical energy; since the output end of the power supply is connected to the cathode of the voltage-stabilizing diode, therefore, when the power supply is turned off, the voltage-stabilizing diode is in a reverse cut-off state, the PNP transistor is turned on, and the voltage of the second pin is pulled down, at this time, the second pin is in a low level state; and the second pin of the target chip is set to a falling edge trigger for saving data interrupt function, on this basis, the target chip enters the interrupt program, and the data can be saved; since the output end of the power delay module is connected to the first pin of the target chip, therefore, when the power supply is powered off, the capacitor in the power delay module can extend the operating time of the target chip and ensure that the target chip can complete data storage; it can be seen that the present application can identify power outages through the power-off detection module and execute data storage in time when the power is off. At the same time, the power delay module in the present application can extend the operating time of the target chip and avoid data omission. In addition, this application does not need to save data regularly, which reduces CPU usage during normal operation and improves operating efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of a power-off protection circuit provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of another power-off protection circuit provided in an embodiment of the present application;

[0035] Figure 1-Figure 2 The corresponding relationship between the reference numerals and component names in the figure is:

[0036] Power supply module 1, power-off detection module 2, power delay module 3, target chip 4, storage chip 5, power supply 10, voltage stabilizing unit 11, PNP transistor 20, first resistor 21, voltage stabilizing diode 22, second resistor 23, third resistor 24, capacitor 30, first voltage drop diode 31, second voltage drop diode 32, first pin 40, second pin 41, voltage stabilizing integrated device 110, first voltage stabilizing capacitor 111, second voltage stabilizing capacitor 112. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] It should be noted that the directions of the components shown in the drawings of the present application are set for ease of understanding of the description and do not impose any restrictions on the directions of the embodiments of the present disclosure during actual implementation. Furthermore, the shapes and sizes of the components shown in the drawings as a whole or in part do not limit the actual shapes and sizes.

[0039] Next, we will combine Figure 1 The power-off protection circuit provided in this application is introduced in detail.

[0040] See also Figure 1 It can be found that the power-off protection circuit may include a power supply module 1 , a power-off detection module 2 , a power supply delay module 3 and a target chip 4 .

[0041] The power module 1 may include a power supply 10 and a voltage stabilizing unit 11 .

[0042] The power failure detection module 2 may include a PNP transistor 20 , a first resistor 21 and a voltage regulator diode 22 .

[0043] The power delay module 3 may include a capacitor 30 .

[0044] The capacitor 30 may be any type of energy storage element with delayed discharge characteristics, such as a farad capacitor.

[0045] Farad capacitors can be charged to any potential within their rated voltage range and can be fully discharged. Farad capacitors can store more energy than conventional capacitors of comparable size and can transmit energy pulses repeatedly without any adverse effects. Farad capacitors can be cycled hundreds of thousands of times.

[0046] The target chip 4 may include a plurality of pins, for example, a first pin 40 and a second pin 41 .

[0047] The target chip 4 stores an interrupt program inside, and the interrupt program is used to save important data related to the operation in the target chip.

[0048] The falling edge triggered interrupt function means that when the signal changes from high (1 signal) to low (0 signal), an interrupt will be generated and the interrupt function will be entered. Interrupts are usually used to handle emergencies. Power failure can be regarded as an emergency.

[0049] Meanwhile, the second pin 41 in the target chip 4 is used to trigger an interrupt function after identifying a falling edge.

[0050] The target chip may be a central processing unit (CPU) such as a single-chip microcomputer.

[0051] See also Figure 1 It can be found that the output end of the power supply 10 can be connected to the input end of the voltage stabilizing unit 11 , and at the same time, the output end of the power supply 10 is also connected to the cathode of the voltage stabilizing diode 22 in the power failure detection module 2 .

[0052] In order to more conveniently control the power supply situation, the power module 1 may further include a switch.

[0053] The voltage stabilizing unit 11 may also be connected to the power supply 10 via a switch.

[0054] The output end of the voltage stabilizing unit 11 is connected to the input end of the power delay module 3 and other circuits that need power supply.

[0055] The output end of the power delay module 3 is connected to the first pin 40 of the target chip 4 .

[0056] The anode of the voltage stabilizing diode 22 is connected to the base of the PNP transistor 20 in the power failure detection module 2;

[0057] The emitter of the PNP transistor 20 is connected to the first resistor 21 and the second pin 41 of the target chip 4 at the same time.

[0058] One end of the first resistor 21 is connected to the emitter of the PNP transistor 20 , and the other end is also connected to the output end of the power delay module 3 .

[0059] It can be seen from the above technical solutions that the power-off data preservation circuit provided by the present application includes a power supply module, a power-off detection module, a power delay module and a target chip. Under normal operating conditions, the power supply can provide energy for the entire power-off data preservation circuit. Since the output end of the voltage stabilizing unit is connected to one end of the power delay module and the first pin of the target chip is connected to the output end of the power delay module, the target chip is connected to the voltage stabilizing unit through the power delay module, and the voltage stability of the entire target chip can be maintained through the voltage stabilizing unit; at the same time, since the voltage of the power supply is greater than the breakdown voltage of the voltage stabilizing diode in the power-off detection module and the output end of the power supply is connected to the cathode of the voltage stabilizing diode, the voltage across the voltage stabilizing diode is greater than its breakdown voltage, and the voltage stabilizing diode is in a reverse conduction state; subsequently, since the anode of the voltage stabilizing diode is connected to the base of the PNP transistor, the current flows from the voltage stabilizing diode to the PNP transistor, and at this time, the PNP transistor is in a cut-off state; then, since the emitter of the PNP transistor is connected to the other end of the power delay module through the first resistor, the emitter is also directly connected to the second pin of the target chip; therefore, the voltage of the second pin of the target chip is affected by the first resistor and is at a high level; at the same time, since the power delay module contains a capacitor, and the capacitor is an energy storage element, therefore, when the power supply is operating normally, the capacitor can store electrical energy; since the output end of the power supply is connected to the cathode of the voltage-stabilizing diode, therefore, when the power supply is turned off, the voltage-stabilizing diode is in a reverse cut-off state, the PNP transistor is turned on, and the voltage of the second pin is pulled down, at this time, the second pin is in a low level state; and the second pin of the target chip is set to a falling edge trigger for saving data interrupt function, on this basis, the target chip enters the interrupt program, and the data can be saved; since the output end of the power delay module is connected to the first pin of the target chip, therefore, when the power supply is powered off, the capacitor in the power delay module can extend the operating time of the target chip and ensure that the target chip can complete data storage; it can be seen that the present application can identify power outages through the power-off detection module and execute data storage in time when the power is off. At the same time, the power delay module in the present application can extend the operating time of the target chip and avoid data omission. In addition, this application does not need to save data regularly, which reduces CPU usage during normal operation and improves operating efficiency.

[0060] In some embodiments of the present application, considering that the rated voltage of the target chip 4 may be lower than the supply voltage of the power supply 1, in order to ensure the safe operation of the target chip 4, a plurality of voltage drop diodes may be provided in the power delay module 3;

[0061] The voltage-drop diodes can be connected in series to achieve a voltage of the target chip 4 equal to its rated voltage.

[0062] It can be seen from the above technical solution that a plurality of voltage-dropping diodes connected in series can also be provided in the power delay module 3 in this embodiment, so that the voltage of the target chip 4 is its rated voltage, thereby improving the operational reliability of the present application and avoiding the adverse effects of the power supply voltage on the target chip 4.

[0063] In some embodiments of the present application, considering that too many voltage drop diodes may make the circuit too complicated, the present application may only set two voltage drop diodes, namely a first voltage drop diode 31 and a second voltage drop diode 32 .

[0064] The first voltage drop diode 31 and the second voltage drop diode 32 are connected in series, and one end of the capacitor 30 is connected to the cathode of the first voltage drop diode 31 and the anode of the second voltage drop diode 32, and the other end is grounded. Figure 2 shown.

[0065] When the power supply 10 supplies power normally, the current passes through the first voltage drop diode 31 to reach the capacitor 30 to charge the capacitor 30 , and then passes through the second voltage drop diode 32 to supply power to the target chip 4 .

[0066] The total voltage drop of the first voltage drop diode 31 and the second voltage drop diode 32 can be set according to the rated voltage of the power supply 10 and the target chip 4. For example, when the power supply 10 is 5V and the rated voltage of the target chip 4 is 3.6V, the total voltage drop of the first voltage drop diode 31 and the second voltage drop diode 32 can be 1.4V.

[0067] When the power supply 10 is powered off, since the first voltage drop diode 31 has a unidirectional conductive characteristic, the electric energy of the capacitor 30 can only flow to the target chip 4, thereby achieving the purpose of power delay.

[0068] The capacity of the capacitor 30 can be set according to the power consumption of the target chip 4 .

[0069] It can be seen from the above technical solutions that in this embodiment, the target chip 4 can operate better through the capacitor 30, the first voltage drop diode 31 and the second voltage drop diode 32.

[0070] In some embodiments of the present application, the power-off detection module 2 may further include a second resistor 23 .

[0071] The anode of the voltage stabilizing diode 22 is connected to the base of the PNP transistor 20 via the second resistor 23 .

[0072] It can be seen from the above technical solution that the second resistor 23 can be used for voltage division through the above technical solution, which is more convenient for the operation of the power failure detection module 2 and better for power failure identification.

[0073] In some embodiments of the present application, the power-off detection module 2 may further include a third resistor 24 .

[0074] One end of the third resistor 24 is connected to the second resistor 23 and the base of the PNP transistor 20 , and the other end is grounded.

[0075] It can be seen from the above technical solution that the third resistor 24 is newly added in this embodiment. When the PNP transistor 20 is normally turned on, it is grounded through the third resistor 24, so that the second pin becomes a low level, thereby better completing the falling edge trigger of the second pin.

[0076] In some embodiments of the present application, the power-off protection circuit may further include a storage chip 5 .

[0077] The storage chip 5 can be connected to the target chip 5, and the storage chip 5 can be used to receive and save important data related to the transmission and operation of the interrupt function.

[0078] Furthermore, the storage chip 5 may be an EEPROM chip.

[0079] The memory chip 5 can be connected to the target chip 4 via an I2 bus.

[0080] It can be seen from the above technical solution that the present application can combine the interrupt function and the storage chip 5 to complete data storage and better ensure data reliability.

[0081] In some embodiments of the present application, the voltage stabilizing unit 11 may include a voltage stabilizing integrated device 110 , a first voltage stabilizing capacitor 111 and a second voltage stabilizing capacitor 112 .

[0082] The input end of the voltage stabilizing integrated device 110 is connected to one end of the first voltage stabilizing capacitor 111 and the output end of the power supply 10;

[0083] The output end of the voltage stabilizing integrated device 110 is connected to one end of the second voltage stabilizing capacitor 112 and the power delay module 3 .

[0084] The other end of the first stabilizing capacitor 111 and the other end of the second stabilizing capacitor 112 are grounded.

[0085] Furthermore, the voltage stabilizing integrated device 110 may be various types of three-terminal voltage stabilizing integrated devices, for example, the model may be LM7805.

[0086] The first voltage stabilizing capacitor 111 may be 22UF.

[0087] When the power supply 10 is supplying power normally, the power supply 10 can charge the first voltage stabilizing capacitor 111. When the voltage of the voltage stabilizing diode 22 gradually rises to exceed its voltage stabilizing value, the voltage stabilizing diode 22 conducts in the reverse direction, and the current flows from the cathode of the voltage stabilizing diode 22 to the anode, and flows to the PNP transistor 20, causing the PNP transistor 20 to be in the cut-off state. Since the first resistor 21 is connected to the output end of the power delay circuit and the PNP transistor 20 is in the cut-off state, the voltage of the second pin 41 is a high level.

[0088] The second pin 41 may be the pin 18 of the single chip microcomputer. The pin 18 is the PB0 port interrupt trigger signal source in the software.

[0089] When the power supply 10 is powered off, the supply voltage of the first voltage stabilizing capacitor 111 is less than the voltage stabilizing value of the voltage stabilizing diode 22, the voltage stabilizing diode 22 is reversely cut off, and the current cannot control the PNP transistor 20, and the PNP transistor 20 is in a conducting state. The PNP transistor 20 is connected to the third resistor 24, and the third resistor 24 is grounded, so at this time, the voltage of the second pin 41 is pulled down to the ground line, and the second pin 41 is at a low level.

[0090] When the supply voltage is greater than the voltage regulation value of the voltage regulator diode 22, the second pin 41 is at a high level (signal 1), and when the supply voltage is less than the voltage regulation value of the voltage regulator diode 22, the second pin 41 is at a low level (signal 0). At this time, since the second pin (PB0 port) is set to trigger an interrupt on a falling edge, the target chip 4 runs the interrupt function, writes the data into the EEPROM chip AT24C02 through the IIC bus, and completes the data preservation when the power is off.

[0091] It can be seen from the above technical solution that this embodiment provides an optional composition method of the voltage stabilizing unit 11, which makes it easy to identify power failure and facilitate power failure protection.

[0092] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0093] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0094] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. The various embodiments of the present application can be combined with each other. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power-off protection circuit, It is characterized in that It includes a power module, a power failure detection module, a power delay module and a target chip; The power delay module includes a capacitor; The power module includes a power supply and a voltage stabilizing unit; The power failure detection module includes a PNP transistor, a first resistor and a voltage regulator diode, and the voltage of the power supply is greater than the breakdown voltage of the voltage regulator diode; The first pin of the target chip is connected to the output end of the power delay module; The output end of the power supply is connected to the input end of the voltage stabilizing unit and the cathode of the voltage stabilizing diode, and the output end of the voltage stabilizing unit is connected to one end of the power delay module; The anode of the voltage stabilizing diode is connected to the base of the PNP transistor, the emitter of the PNP transistor is connected to the output end of the power delay module through the first resistor, and the emitter is also directly connected to the second pin of the target chip; An interrupt function for saving data is stored in the target chip, and the second pin of the target chip is set to trigger the interrupt function on a falling edge.

2. The power-off protection circuit according to claim 1, It is characterized in that The power delay module also includes a plurality of voltage drop diodes; The voltage-drop diodes are connected in series.

3. The power-off protection circuit according to claim 2, It is characterized in that The power delay module includes a first voltage drop diode and a second voltage drop diode; One end of the capacitor is connected to the cathode of the first voltage drop diode and the anode of the second voltage drop diode, and the other end is grounded.

4. The power-off protection circuit according to claim 1, It is characterized in that The power failure detection module also includes a second resistor; The anode of the voltage stabilizing diode is connected to the base of the PNP transistor through the second resistor.

5. The power-off protection circuit according to claim 4, It is characterized in that The power failure detection module further includes a third resistor; One end of the third resistor is connected to the second resistor and the base of the PNP transistor, and the other end is grounded.

6. The power-off protection circuit according to claim 1, It is characterized in that Also includes memory chips; The storage chip is connected to the target chip, and is used for receiving and storing data transmitted by the interrupt function.

7. The power-off protection circuit according to claim 6, It is characterized in that The storage chip is an EEPROM chip.

8. The power-off protection circuit according to claim 6, It is characterized in that The storage chip is connected to the target chip via an I2 bus.

9. The power-off protection circuit according to claim 1, It is characterized in that The voltage stabilizing unit includes a voltage stabilizing integrated device, a first voltage stabilizing capacitor and a second voltage stabilizing capacitor; The input end of the voltage stabilizing integrated device is connected to one end of a first voltage stabilizing capacitor and an output end of a power supply; The output end of the voltage stabilizing integrated device is connected to one end of a second voltage stabilizing capacitor and a power supply delay module; The other end of the first stabilizing capacitor and the other end of the second stabilizing capacitor are grounded.

10. The power-off protection circuit according to claim 9, It is characterized in that The voltage stabilizing integrated device is a three-terminal voltage stabilizing integrated device.

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