Non-TSV HBM chip packaging structure
By adopting a non-TSV structure in HBM chip package and using the combination of copper columns and plastic sealing layers, the problems of complex processes and high cost in the prior art are solved, low-cost and high-efficiency chip package is achieved, and multi-layering is supported. Install to meet different application needs.
Patent Information
- Application Number
- CN202323660179.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2033-12-29
AI Technical Summary
The existing HBM chip packaging structure uses TSV connection, which has a complex process and high cost, and is not suitable for promotion and use.
Using a non-TSV chip packaging structure, the chip stacking package is achieved by connecting the copper column between the logic chip unit and the memory chip unit, combining the plastic sealing layer and the solder bump, thereby reducing process costs and improving operating efficiency.
By using wafer-level fan-out process, the solder joints are transferred to the side of the chip, and the copper column connection is connected by the side of the chip, which reduces the process cost and supports the stacking of multi-layer memory chip units to meet the needs of different application scenarios.
Smart Images
Figure CN222214165U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, in particular to a non-TSV HBM chip packaging structure. Background Art
[0002] HBM (High Bandwidth Memory) is a new type of CPU / GPU memory chip (i.e. "RAM"), which is actually a number of DDR chips stacked together and packaged together with the GPU to achieve a large-capacity, high-bit-width DDR combination array.
[0003] The conventional HBM DRAM 3D chip packaging structure is as follows:
[0004] ●DRAM is stacked together, and the dies are connected by TVS.
[0005] ● Below the DRAM is the DRAM logic control unit, which controls the DRAM;
[0006] GPU and DRAM are connected via uBump and Interposer (a silicon chip that performs interconnection functions);
[0007] ●Interposer is then connected to BALL through Bump and Substrate (package substrate);
[0008] ●Finally, the BGA BALL is connected to the PCB.
[0009] The TVS method is used to connect each chip, which has a complex process and high cost, and is not suitable for popularization. Utility Model Content
[0010] In order to solve the above problems, the utility model provides a non-TSV HBM chip packaging structure with low cost, simple process and high operation efficiency.
[0011] To this end, the technical solution of the utility model is: a non-TSV HBM chip packaging structure, including a logic chip unit and a plurality of storage chip units;
[0012] The logic chip unit includes a logic chip body, a first plastic sealing layer and a first copper pillar, wherein the first copper pillar is located outside the logic chip body and is electrically connected to the logic chip body, and the first plastic sealing layer covers the logic chip body and the first copper pillar;
[0013] The memory chip unit comprises a memory chip body, a second plastic sealing layer and a second copper pillar, wherein the second copper pillar is located outside the memory chip body and is electrically connected to the memory chip body, and the second plastic sealing layer covers the memory chip body and the second copper pillar;
[0014] The memory chip unit is stacked on the logic chip unit, and the first copper pillar and the second copper pillar are connected to each other.
[0015] On the basis of the above scheme and as a preferred scheme of the above scheme: the logic chip body in the logic chip unit is a front-mounted structure, and the storage chip unit is stacked on the front side of the logic chip body.
[0016] On the basis of the above scheme and as a preferred scheme of the above scheme: the logic chip body in the logic chip unit is a flip-chip structure, and the storage chip unit is stacked on the back side of the logic chip body.
[0017] On the basis of the above solution and as a preferred solution of the above solution: the front side of the logic chip body is electrically connected to the first copper pillar.
[0018] On the basis of the above scheme and as a preferred scheme of the above scheme: the storage chip body in the storage chip unit is a flip-chip structure, and the front side of the storage chip body is conductively connected to the second copper pillar.
[0019] On the basis of the above solution and as a preferred solution of the above solution: a first solder bump is provided under the second copper column of the storage chip unit and is welded and fixed to the first copper column or the second copper column below.
[0020] On the basis of the above solution and as a preferred solution of the above solution: a filling layer is provided between the memory chip unit and the logic chip unit, and between adjacent memory chip units.
[0021] On the basis of the above scheme and as a preferred scheme of the above scheme: a storage chip unit is installed on one side of the logic chip unit, and a second solder bump is provided on the other side, and the second solder bump is conductively connected to the first copper column.
[0022] Compared with the prior art, the beneficial effects of the utility model are: the solder joints are transferred to the side of the chip by using the wafer-level fan-out process, and the original TSV connection is replaced by the copper column connection on the side of the chip, which greatly reduces the process cost; multiple storage chip units can be stacked according to usage needs to meet the requirements of different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings.
[0024] Figure 1 It is a structural schematic diagram of Example 1;
[0025] Figure 2 This is a schematic diagram of the structure of the storage chip unit of Example 1;
[0026] Figure 3This is a process flow chart of a memory chip unit in Example 1;
[0027] Figure 4 This is a process flow chart of the logic chip unit of Example 1;
[0028] Figures 5 to 9 It is the process flow chart of Example 1;
[0029] Fig.10 It is a structural schematic diagram of Example 2;
[0030] Fig.11 This is a process flow chart of the logic chip unit of Example 2;
[0031] Figures 12 to 16 This is the process flow chart of Example 2.
[0032] Marked in the figure are: first logic chip unit 1, logic chip body 11, first plastic sealing layer 12, first copper pillar 13, fourth copper pillar 14, solder bump 15, memory chip unit 2, memory chip body 21, second plastic sealing layer 22, second copper pillar 23, first solder bump 24, third copper pillar 25, DAF film 26, second solder bump 3, filling layer 4, first silicon substrate 51, second silicon substrate 52, third silicon substrate 53, second logic chip unit 6, and third plastic sealing layer 7. DETAILED DESCRIPTION
[0033] In the description of the present invention, it should be noted that directional words, such as the terms "center", "lateral (X)", "longitudinal (Y)", "vertical (Z)", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating directions and positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of narrating the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific protection scope of the present invention.
[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. Therefore, the definition of "first" and "second" features can explicitly or implicitly include one or more of the features. In the description of the utility model, the meaning of "several" and "a number" is two or more, unless otherwise clearly and specifically defined.
[0035] Example 1
[0036] The non-TSV HBM chip packaging structure described in this embodiment includes a first logic chip unit 1 and a plurality of memory chip units 2 .
[0037] The first logic chip unit 1 includes a logic chip body 11, a first plastic layer 12 and a first copper pillar 13. The first copper pillar 13 is located outside the logic chip body 11 and is electrically connected to the logic chip body 11. The first plastic layer 12 covers the logic chip body 11 and the first copper pillar 13. The logic chip body 11 in the first logic chip unit 1 is a positive structure, and the memory chip unit 2 is stacked on the front side of the logic chip body 11. The front side of the logic chip body 11 is connected to the first copper pillar 13 through the wiring layer. The memory chip unit 2 is installed on one side of the first logic chip unit 1, and a second solder bump 3 is provided on the other side. The second solder bump 3 is connected to the first copper pillar 13.
[0038] The memory chip unit 2 includes a memory chip body 21, a second plastic sealing layer 22 and a second copper pillar 23. The second copper pillar 23 is located outside the memory chip body 21 and is electrically connected to the memory chip body 21. The second plastic sealing layer 22 covers the memory chip body 21 and the second copper pillar 23. The memory chip body 21 in the memory chip unit 2 is a flip-chip structure, and the front side of the memory chip body 21 is conductively connected to the second copper pillar 23.
[0039] The memory chip unit 2 is stacked on the first logic chip unit 1, and a first solder bump 24 is provided below the second copper pillar 23 of the memory chip unit 2, which is soldered and fixed to the first copper pillar 13 or the second copper pillar 23 below. A filling layer 4 is provided between the memory chip unit 2 and the first logic chip unit 1, and between adjacent memory chip units 2.
[0040] The preparation process of this embodiment is as follows:
[0041] 1. The packaging process of the memory chip unit, such as Figure 3 As shown:
[0042] 1.1) preparing a first silicon substrate 51, and growing a second copper pillar 23 on the first silicon substrate 51;
[0043] 1.2) preparing a memory chip body 21 and growing a third copper pillar 25 on the front side of the memory chip body 21;
[0044] 1.3) Grinding the back of the memory chip body 21 and cutting out a single wafer, and then covering it with a DAF film 26 (centrifugal air flotation concentration membrane);
[0045] 1.4) Mount the memory chip body 21 on the first silicon substrate 51, with the front side of the memory chip body 21 facing upwards;
[0046] 1.5) Filling a second plastic encapsulation layer 22 on the first silicon substrate 51, the second plastic encapsulation layer 22 covers the memory chip body 21, the third copper pillar 25 and the second copper pillar 23;
[0047] 1.6) Grinding the second plastic sealing layer 22 to expose the third copper pillar 25 and the second copper pillar 23;
[0048] 1.7) Laying a PI layer and a wiring layer on the exposed front side of the chip, the second copper pillar 23 is electrically connected to the third copper pillar 25 through the wiring layer, wherein the number of layers of the PI layer and the wiring layer is determined by the actual routing of the chip; at the same time, making a first solder bump 24 on the front side of the chip, the first solder bump 24 can be realized by ball planting or electroplating process;
[0049] 1.8) Grind the back side of the chip, remove the first silicon substrate 51 and the DAF film 26, expose the back side of the memory chip body 21 and the bottom of the second copper pillar 23, and then scribing and cutting out individual memory chips.
[0050] 2. The packaging process of the first logic chip unit, such as Figure 4 As shown:
[0051] 2.1) preparing a second silicon substrate 52, and growing a first copper pillar 13 on the second silicon substrate 52;
[0052] 2.2) preparing a logic chip body 11, and growing a fourth copper pillar 14 on the front surface of the logic chip body 11;
[0053] 2.3) Grinding the back of the logic chip body 11 and cutting out a single wafer, and then covering it with a DAF membrane (centrifugal air flotation concentration membrane);
[0054] 2.4) Mount the logic chip body 11 on the second silicon substrate 52, with the front side of the logic chip body 11 facing upwards;
[0055] 2.5) Filling a first plastic encapsulation layer 12 on the second silicon substrate 52, the first plastic encapsulation layer 12 covers the logic chip body 11, the fourth copper pillar 14 and the first copper pillar 13;
[0056] 2.6) Grinding the first plastic sealing layer 12 to expose the fourth copper pillar 14 and the first copper pillar 13;
[0057] 2.7) Lay the PI layer and the wiring layer on the exposed front side of the chip, and the first copper pillar 13 is electrically connected to the fourth copper pillar 14 through the wiring layer, wherein the number of the PI layer and the wiring layer is determined by the actual routing of the chip; at the same time, make solder bumps 15 on the front side of the chip.
[0058] 3. The packaging process of HBM chip, such as Figures 5 to 9 As shown:
[0059] 3.1) The fabricated memory chip unit 2 is flipped onto the first logic chip unit 1, the first copper pillar 13 and the second copper pillar 23 are connected to each other, and the bottom filling glue or NCF is used to fill the space between them to form a filling layer 4;
[0060] 3.2) Continue to stack the remaining memory chip units 2 on the memory chip units 2 in sequence, the second copper pillars 23 between adjacent memory chip units 2 are connected to each other, and the middle of each layer is filled with bottom filling glue or NCF to form a filling layer 4;
[0061] 3.3) Plastic encapsulation is performed on the front side of the package body to cover all the stacked memory chip units 2 as a whole, forming a third plastic encapsulation layer 7;
[0062] 3.4) Grinding the back of the package to remove the second silicon substrate 52 and the DAF film, exposing the back of the logic chip body 11 and the bottom of the first copper pillar 13;
[0063] 3.5) Flipping the package, laying a PI layer and a wiring layer on the back of the exposed logic chip body 11, making a second solder bump 3 on the back, the second solder bump is electrically connected to the first copper column through the wiring layer, wherein the number of PI layers and wiring layers depends on the actual routing of the chip; meanwhile, the second solder bump can be realized by ball planting or electroplating process;
[0064] 3.6) The back side of the package (i.e., the side without the second solder bump) is subjected to grinding, printing, back gluing, dicing, and then testing to obtain qualified chips.
[0065] Example 2
[0066] The structure of this embodiment is similar to that of the embodiment 1, except that: the memory chip unit 2 is flipped on the second logic chip unit 6, the logic chip body 11 in the second logic chip unit 6 is a flipped structure, and the memory chip unit 2 is stacked on the back side of the logic chip body 11. The front side of the logic chip body 11 is conductive with the first copper pillar 12.
[0067] 4. The packaging process of the second logic chip unit, such as Fig.11 As shown:
[0068] 4.1) Prepare a logic chip body 11, and grow a fourth copper pillar 14 on the front side of the logic chip body;
[0069] 4.2) preparing a third silicon substrate 53, and coating a temporary bonding adhesive on the surface of the third silicon substrate 53;
[0070] 4.3) Laying a PI layer and a wiring layer on the third silicon substrate 53, and generating a first copper pillar 13, wherein the number of layers of the PI layer and the wiring layer is determined according to the actual routing of the chip;
[0071] 4.4) The logic chip body 11 is flipped onto the third silicon substrate 53, with the front side of the logic chip body 11 facing downwards, and is connected to the first copper pillar 13 through the wiring layer;
[0072] 4.5) Filling a first plastic encapsulation layer 12 on the third silicon substrate 53, the first plastic encapsulation layer 12 covers the logic chip body 11 and the first copper pillar 13;
[0073] 4.6) Grind the first plastic packaging layer 12 to expose the logic chip body 11 and the first copper pillar 13, thus completing the packaging of the second logic chip unit 6.
[0074] 5. The second packaging process of HBM chip, such as Figure 12 to Figure 16 As shown:
[0075] 5.1) The fabricated memory chip unit 2 is flipped onto the second logic chip unit 6, the first copper pillar 13 and the second copper pillar 23 are connected to each other, and the space between the two is filled with bottom filling glue or NCF to form a filling layer 4;
[0076] 5.2) Continue to stack the remaining memory chip units 2 on the memory chip unit 2 in sequence, the second copper pillars between adjacent memory chip units are connected to each other, and the middle of each layer is filled with bottom filling glue or NCF to form a filling layer 4;
[0077] 5.3) Plastic sealing is performed on the front side of the package body to cover all the stacked memory chip units 2 as a whole;
[0078] 5.4) Debonding the package body and the third silicon substrate 53, and removing the third silicon substrate 53;
[0079] 5.5) turning over the package body to make a second solder bump 3, the second solder bump is electrically connected to the first copper column through the wiring layer, and the second solder bump can be realized by ball planting or electroplating process;
[0080] 5.6) The back side of the package (i.e., the side without the second solder bump) is subjected to grinding, printing, back gluing, dicing, and then testing to obtain qualified chips.
[0081] The above is only a preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.
Claims
1. A non-TSV HBM chip packaging structure, including a logic chip unit and a plurality of memory chip units; Features: The logic chip unit includes a logic chip body, a first plastic sealing layer and a first copper pillar, wherein the first copper pillar is located outside the logic chip body and is electrically connected to the logic chip body, and the first plastic sealing layer covers the logic chip body and the first copper pillar; The memory chip unit comprises a memory chip body, a second plastic sealing layer and a second copper pillar, wherein the second copper pillar is located outside the memory chip body and is electrically connected to the memory chip body, and the second plastic sealing layer covers the memory chip body and the second copper pillar; The memory chip unit is stacked on the logic chip unit, and the first copper pillar and the second copper pillar are connected to each other.
2. A non-TSV HBM chip packaging structure as claimed in claim 1, Features: The logic chip body in the logic chip unit is a front-mounted structure, and the storage chip unit is stacked on the front side of the logic chip body.
3. The non-TSV HBM chip packaging structure according to claim 1, Features: The logic chip body in the logic chip unit is a flip-chip structure, and the storage chip unit is stacked on the back side of the logic chip body.
4. A non-TSV HBM chip packaging structure as claimed in claim 2 or 3, Features: The front side of the logic chip body is electrically connected to the first copper column.
5. The non-TSV HBM chip packaging structure according to claim 1, Features: The storage chip body in the storage chip unit is a flip-chip structure, and the front side of the storage chip body is conductively connected to the second copper column.
6. The non-TSV HBM chip packaging structure according to claim 1, Features: A first solder bump is provided below the second copper column of the memory chip unit and is welded and fixed to the first copper column or the second copper column below.
7. The non-TSV HBM chip packaging structure according to claim 1, Features: A filling layer is provided between the memory chip unit and the logic chip unit, and between adjacent memory chip units.
8. The non-TSV HBM chip packaging structure according to claim 1, Features: A storage chip unit is installed on one side of the logic chip unit, and a second solder bump is provided on the other side, and the second solder bump is conductively connected to the first copper column.