Trench gate silicon carbide MOSFET capable of inhibiting gate breakdown

Abstract

The utility model provides a trench gate silicon carbide MOSFET inhibiting gate breakdown, comprising a silicon carbide substrate and a drift layer, the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate; the lower side surface of the low-resistance structure layer is connected to the upper side surface of the drift layer; the lower side surface of the well region is connected to the low-resistance structure layer; the source region is connected to the well region; the gate dielectric layer penetrates through the source region, and the lower side surface of the gate dielectric layer is connected to the well region; the side surface of the gate dielectric layer is connected to the source region, and a groove is formed in the gate dielectric layer; the source electrode metal layer is respectively connected with the low-resistance structure layer, the well region and the source region; a gate metal layer, wherein the gate metal layer is arranged in the groove; and the drain electrode metal layer is connected to the lower side surface of the silicon carbide substrate, so that the driving voltage is reduced, and the driving loss is further reduced.

Description

Technical Field

[0001] The utility model relates to the field of semiconductors, in particular to a trench gate silicon carbide MOSFET capable of suppressing gate breakdown. Background Art

[0002] As a representative device among SiC power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. The on-resistance of the trench gate of this device is low, but the electric field concentration at its corners will reduce its gate reliability. Therefore, solving the gate reliability of the trench gate is a problem that academia and industry have always needed to solve. At the same time, continuously reducing the on-resistance of the device is the eternal pursuit of improving the efficiency of the power system. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a trench gate silicon carbide MOSFET which suppresses gate breakdown, reduces the driving voltage, and further reduces the driving loss.

[0004] The utility model is implemented as follows: a trench gate silicon carbide MOSFET for suppressing gate breakdown, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;

[0007] A low-resistance structural layer, wherein the lower side of the low-resistance structural layer is connected to the upper side of the drift layer;

[0008] A well region, wherein the lower side of the well region is connected to the low-resistance structure layer;

[0009] a source region connected to the well region;

[0010] A gate dielectric layer, the gate dielectric layer passes through the source region, the lower side of the gate dielectric layer is connected to the well region; the side of the gate dielectric layer is connected to the source region, and a groove is provided in the gate dielectric layer;

[0011] A source metal layer, the source metal layer is respectively connected to the low resistance structure layer, the well region and the source region;

[0012] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0013] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0014] The advantages of the utility model are:

[0015] 1. The device constructs a direct contact between the source metal layer and the low-resistance structure layer, forming a Schottky diode, which reduces the body diode conduction voltage of the device and reduces the device's freewheeling power consumption;

[0016] Second, the device constructs a low-resistance structure layer with the same doping concentration as the source region under the well region. The low-resistance structure layer can provide carriers for the well region inversion during the device conduction process, thereby reducing the driving voltage of the device during low-resistance conduction, thereby reducing the driving voltage and driving loss;

[0017] 3. In addition to reducing the driving voltage, the low-resistance structure layer can also reduce the on-resistance of the device and improve the device performance due to its high doping concentration;

[0018] Fourth, the device adopts a trench gate structure. In order to avoid breakdown caused by electric field concentration at the corners of the gate insulating dielectric, the well region surrounds the corners of the gate dielectric layer, suppressing the gate breakdown characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0020] Figure 1 The utility model is a schematic diagram of a trench gate silicon carbide MOSFET for suppressing gate breakdown.

[0021] Figure 2 The utility model is a flow chart of a method for preparing a trench gate silicon carbide MOSFET capable of suppressing gate breakdown.

[0022] Figure 3 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 1 .

[0023] Figure 4 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 2 .

[0024] Figure 5 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 3 .

[0025] Figure 6 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 4 .

[0026] Figure 7 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 5 .

[0027] Figure 8 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 6 .

[0028] Fig. 9 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 7 .

[0029] Fig.10 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 8 .

[0030] Fig.11 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 9 .

[0031] Fig.12 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 10 .

[0032] Fig.13 This is a cross-sectional view of the process of a trench gate silicon carbide MOSFET that suppresses gate breakdown in the utility model. Figure 10 one. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] like Figure 1 As shown, the embodiment of the present application provides a trench gate silicon carbide MOSFET that suppresses gate breakdown, including:

[0039] Silicon carbide substrate 1,

[0040] A drift layer 2, wherein the lower side of the drift layer 1 is connected to the upper side of the silicon carbide substrate 2;

[0041] A low-resistance structure layer 3, wherein the lower side of the low-resistance structure layer 3 is connected to the upper side of the drift layer 2;

[0042] A well region 4, wherein the lower side of the well region 4 is connected to the low-resistance structure layer 3;

[0043] a source region 5, wherein the source region 5 is connected to the well region 4;

[0044] A gate dielectric layer 6, the gate dielectric layer 6 passes through the source region 5, the lower side of the gate dielectric layer 6 is connected to the well region 4; the side of the gate dielectric layer 6 is connected to the source region 5, a groove 61 is provided in the gate dielectric layer 6, the distance L between the bottom of the gate dielectric layer 6 and the bottom of the well region 4 is 500-800 nanometers, and the gate dielectric layer 6 is silicon dioxide or a high-K dielectric;

[0045] A source metal layer 7, wherein the source metal layer 7 is respectively connected to the low resistance structure layer 3, the well region 4 and the source region 5;

[0046] A gate metal layer 8, wherein the gate metal layer 8 is disposed in the groove 61;

[0047] and a drain metal layer 9 , wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0048] The silicon carbide substrate 1 , the drift layer 2 , the low-resistance structure layer 3 and the source region 5 are all N-type, and the well region 4 is P-type.

[0049] The direct contact between the device source metal layer 7 and the low-resistance structure layer 3 constructs a Schottky diode, and the on-state voltage drop of the Schottky diode is smaller than the on-state voltage drop of the parasitic pn junction, thereby effectively reducing the device loss when the device body diode is freewheeling, and improving the efficiency of the power supply system; a low-resistance structure layer 3 with the same doping concentration as the source region 5 is constructed below the well region 4, and the low-resistance structure layer 3 can provide carriers for the well region 4 in the process of device conduction, thereby reducing the driving voltage when the device is fully turned on, thereby reducing the driving loss; in addition to reducing the driving voltage, the low-resistance structure layer 3 has a very low contact resistance because its doping concentration is the same as that of the source region 5, so it can reduce the on-resistance of the device and improve the performance of the device.

[0050] The device adopts a trench gate structure. The trench gate itself has the characteristic of reducing on-resistance, but it is easy to generate electric field concentration at the corners of the gate dielectric layer 6 and cause breakdown. Therefore, the well region surrounds the corners of the gate dielectric layer 6, effectively suppressing the unreliable corners of the gate insulating dielectric layer 6.

[0051] like Figures 1 to 13 As shown, the method for preparing the above MOSFET comprises the following steps:

[0052] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9, and depositing and growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0053] Step 2, forming a low-resistance structure layer 3 by ion implantation into the drift layer 2, the ion implantation energy is 500-1200kev, the implantation depth is about 1500nm-3600nm, the implantation depth is 1500nm-3600nm, and the thickness of the low-resistance structure layer 3 is 2100nm;

[0054] Step 3, depositing a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 through the through hole to form a well region 4, wherein the ion implantation energy is 100-500kev, the implantation depth is 300nm-1500nm, and the thickness of the well region 4 is 1200nm;

[0055] Step 4, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing ion implantation into the drift layer 2 through the through hole to form a source region 5, wherein the thickness of the source region 5 is 300 nm;

[0056] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch to form a trench gate region b, the distance between the bottom of the trench gate region b and the bottom of the well region 4 is 500-800nm, and deposit and grow a gate dielectric layer 6 in the trench gate region b, wherein the gate dielectric layer 6 is silicon dioxide or a high-K dielectric;

[0057] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a and the gate dielectric layer 6 respectively to form a through hole and a groove 61, and depositing metal in the groove 61 through the through hole to form a gate metal layer 8;

[0058] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a and the drift layer 2, depositing metal, and forming a first source metal region 71;

[0059] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, deposit metal, form the second source metal region 72, the source metal layer 7 includes the first source metal region 71 and the second source metal region 72, remove the barrier layer a, and complete the manufacturing.

[0060] The silicon carbide substrate 1, drift layer 2, low resistance structure layer 3 and source region 5 are all N-type, the well region 4 is P-type, and the doping concentration of the silicon carbide substrate is 2e18cm -3 , the doping concentration of the drift layer is 3e16cm -3 The doping concentration of the low-resistance structure layer is 5e19cm-3 The doping concentration of the well region is 6e16 cm -3 , the doping concentration of the source region is 5e19cm -3 The doping concentration of the low-resistance structure layer 3 is equal to the doping concentration of the source region, which can effectively reduce the on-resistance of this part. At the same time, when the device is turned on, the device current flows to the low-resistance area, making the current more evenly distributed inside the device, avoiding current concentration and heat concentration.

[0061] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A trench gate silicon carbide MOSFET with gate breakdown suppression, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A low-resistance structural layer, wherein the lower side of the low-resistance structural layer is connected to the upper side of the drift layer; A well region, wherein the lower side of the well region is connected to the low-resistance structure layer; a source region connected to the well region; A gate dielectric layer, the gate dielectric layer passes through the source region, the lower side of the gate dielectric layer is connected to the well region; the side of the gate dielectric layer is connected to the source region, and a groove is provided in the gate dielectric layer; A source metal layer, the source metal layer is respectively connected to the low resistance structure layer, the well region and the source region; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. A trench gate silicon carbide MOSFET with gate breakdown suppression according to claim 1, characterized in that: The doping concentration of the low resistance structure layer is equal to the doping concentration of the source region.

3. A trench gate silicon carbide MOSFET with gate breakdown suppression according to claim 1, characterized in that: The distance between the bottom of the gate dielectric layer and the bottom of the well region is 500-800 nanometers.

4. A trench gate silicon carbide MOSFET with gate breakdown suppression according to claim 1, characterized in that: The thickness of the source region is 300 nm; the thickness of the well region is 1200 nm; and the thickness of the low-resistance structural layer is 2100 nm.

5. A trench gate silicon carbide MOSFET with gate breakdown suppression according to claim 1, characterized in that: The silicon carbide substrate, drift layer, low-resistance structure layer and source region are all N-type, and the well region is P-type.

6. A trench gate silicon carbide MOSFET with gate breakdown suppression according to claim 1, characterized in that: The gate dielectric layer is silicon dioxide or high-K dielectric.

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