Silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) capable of inhibiting drain voltage overshoot

Abstract

The utility model provides a silicon carbide VDMOS capable of suppressing drain voltage overshoot. The silicon carbide VDMOS comprises a silicon carbide substrate; the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate; an overshoot suppression structure layer is arranged in the drift layer, and a lug boss is arranged on the drift layer; the lower side surface of the well region is connected to the upper side surface of the drift layer, and the side surface of the well region is connected to the side surface of the lug boss; a source region is arranged in the well region; the gate dielectric layer is connected to the lug boss and the well region; the gate metal layer is connected to the gate dielectric layer; the source electrode metal layer is connected to the source region and the well region; and the drain electrode metal layer is connected to the lower side surface of the silicon carbide substrate, and is used for buffering the impact of the grid electrode when the voltage overshoot of the drain electrode occurs, so that the voltage endurance capability of the drain electrode of the device is improved.

Description

Technical Field

[0001] The utility model relates to a silicon carbide VDMOS capable of suppressing drain voltage overshoot. Background Art

[0002] As a representative device among SiC power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. In some harsh environments, the power supply fluctuates widely, and a very small amount of drain voltage overshoot can easily cause irreversible damage to silicon carbide VDMOS, resulting in device reliability problems. In this special case, a device that suppresses drain overshoot is needed to suppress drain fluctuation overshoot and improve the device's ability to withstand harsh conditions. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS which can suppress drain voltage overshoot, buffer the gate impact when drain voltage overshoot occurs, and improve the drain voltage resistance of the device.

[0004] The utility model is implemented as follows: a silicon carbide VDMOS for suppressing drain voltage overshoot, comprising:

[0005] Silicon carbide substrate;

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; an overshoot suppression structure layer is provided in the drift layer, and a protrusion is provided on the drift layer;

[0007] A well region, wherein the lower side of the well region is connected to the upper side of the drift layer, and the side of the well region is connected to the side of the protruding portion; a source region is provided in the well region;

[0008] a gate dielectric layer connected to the protrusion and the well region;

[0009] a gate metal layer, the gate metal layer being connected to the gate dielectric layer;

[0010] A source metal layer connected to the source region and the well region;

[0011] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0012] The advantages of the utility model are:

[0013] 1. An overshoot suppression structure layer is constructed under the gate metal layer of the device to buffer the gate impact when the drain voltage overshoots, thereby improving the drain voltage withstand capability of the device;

[0014] Second, the device adopts a planar gate structure, with a protrusion on the gate dielectric layer. In the conductive part of the control channel area, the gate dielectric thickness is still kept low to achieve good gate control capability. A thick dielectric layer is established in the JFET area to improve the device gate's impact resistance when the device's drain overshoots;

[0015] 3. The overshoot suppression structure layer is constructed inside the drift layer, and its lateral width accounts for one tenth to one sixth of the width of the drift layer, which has little effect on the conductive characteristics of the device;

[0016] 4. The distance from the overshoot suppression structure layer to the silicon carbide substrate is 500nm, which can achieve drain voltage overshoot suppression at the device drain, with minimal impact on the conductive characteristics of the JFET region of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0018] Figure 1 The utility model is a schematic diagram of a silicon carbide VDMOS for suppressing drain voltage overshoot.

[0019] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide VDMOS for suppressing drain voltage overshoot.

[0020] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 1 .

[0021] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 2 .

[0022] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 3 .

[0023] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 4 .

[0024] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 5 .

[0025] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 6 .

[0026] Fig. 9 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 7 .

[0027] Fig.10 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 8 . DETAILED DESCRIPTION

[0028] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0031] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0032] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide VDMOS for suppressing drain voltage overshoot, including:

[0034] Silicon carbide substrate 1;

[0035] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; an overshoot suppression structure layer 21 is provided in the drift layer 2, and a protrusion 22 is provided on the drift layer 2;

[0036] A well region 3, wherein the bottom side of the well region 3 is connected to the top side of the drift layer 2, and the side of the well region 3 is connected to the side of the protrusion 22; a source region 31 is provided in the well region 3;

[0037] A gate dielectric layer 4, the gate dielectric layer 4 is connected to the protrusion 22 and the well region 3, and a protrusion 41 is provided on the gate dielectric layer 4;

[0038] A gate metal layer 5 connected to the gate dielectric layer 4 and the protrusion 41;

[0039] A source metal layer 6, wherein the source metal layer 6 is connected to the source region 31 and the well region 3;

[0040] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0041] The width L1 of the overshoot suppression structure layer 21 is equal to the width L2 of the protrusion 22 , and the width of the overshoot suppression structure layer 21 is one tenth to one sixth of the width of the drift layer 2 . The distance L3 from the bottom of the overshoot suppression structure layer 21 to the silicon carbide substrate 1 is 500 nm.

[0042] The silicon carbide substrate 1 , the drift layer 2 and the source region 31 are all of N type; the overshoot suppression structure layer 21 and the well region 3 are all of P type.

[0043] An overshoot suppression structure layer 21 is constructed under the gate metal layer 5 of the device to buffer the gate impact when the drain voltage overshoots, thereby improving the drain voltage resistance of the device; the device adopts a planar gate structure, and a protrusion is provided on the gate dielectric layer. In the conductive part of the control channel region, the gate dielectric thickness is still maintained low to achieve good gate control capability, and a thick dielectric layer is established in the JFET region to improve the impact resistance of the device gate when the drain of the device overshoots; the overshoot suppression structure layer is constructed inside the drift layer, and its lateral width accounts for one-tenth to one-sixth of the width of the drift layer, which has little effect on the conductive characteristics of the device; the distance from the overshoot suppression structure layer to the silicon carbide substrate is 500nm, and the drain voltage overshoot is suppressed at the drain of the device, which has little effect on the conductive characteristics of the JFET region of the device.

[0044] like Figures 1 to 10 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0045] Step 1: depositing metal on one side of the silicon carbide substrate 1 to form a drain metal layer 7, and depositing and growing a drift layer 2 on the other side of the silicon carbide substrate 1, wherein the thickness of the drift layer is 6 microns;

[0046] Step 2, depositing a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and implanting ions into the drift layer 2 through the through hole to form an overshoot suppression structure layer 21, wherein the ion implantation energy for forming the overshoot suppression structure layer 21 is 1200-1500kev, and the depth that can be reached is 3.6-4.5 microns, and the thickness of the overshoot structure layer 21 is 900nm;

[0047] Step 3, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 through the through hole to form a well region 31, so that a convex portion 22 is formed on the drift layer 2; the ion implantation energy for forming the well region 31 is 100-500kev, the thickness of the well region is 1200nm, and the width of the overshoot suppression structure layer 21 is equal to the width of the convex portion 22;

[0048] Step 4, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing ion implantation into the well region 3 through the through hole to form a source region 31, wherein the thickness of the source region 31 is 300 nm;

[0049] Step 5, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing metal deposition through the through hole to form a source metal layer 6;

[0050] Step 6: remove the original barrier layer a, reform the barrier layer a, etch to form a through hole, deposit through the through hole to form a gate insulating layer 4, remove the original barrier layer a, reform the barrier layer a, etch to form a through hole, deposit through the through hole to form a protrusion 41;

[0051] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, deposit metal through the through hole to form a gate metal layer 5; remove the barrier layer a, and complete the manufacturing;

[0052] The width of the overshoot suppression structure layer 21 is one tenth to one sixth of the width of the drift layer 2 , and the distance L3 from the bottom of the overshoot suppression structure layer 21 to the silicon carbide substrate 1 is 500 nm.

[0053] The silicon carbide substrate 1, the drift layer 2 and the source region 31 are all N-type; the overshoot suppression structure layer 21 and the well region 3 are all P-type, and the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 3e16 cm -3 The doping concentration of the overshoot suppression structure layer 21 is 5e17cm -3 The doping concentration of the well region 3 is 6e16 cm -3 The doping concentration of the source region 31 is 5e19cm -3 ; The doping of the silicon carbide substrate 1 is to form an ohmic contact with the drain metal layer 7 and reduce the on-resistance. The doping concentration of the drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device. The doping of the overshoot suppression structure layer 21 is related to its thickness, forming the size of the internal space charge region and ensuring the ability to suppress drain voltage overshoot. The doping concentration of the well region 3 is to achieve a compromise between the device gate control and the device on-resistance. The doping concentration of the source region 31 is to ensure that the source region 31 forms an ohmic contact with the source metal layer 6 and reduces the on-resistance of the device.

[0054] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide VDMOS for suppressing drain voltage overshoot, characterized in that: include: Silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; An overshoot suppression structure layer is provided in the drift layer, and a protrusion is provided on the drift layer; A well region, wherein the lower side of the well region is connected to the upper side of the drift layer, and the side of the well region is connected to the side of the protruding portion; a source region is provided in the well region; a gate dielectric layer connected to the protrusion and the well region; a gate metal layer, the gate metal layer being connected to the gate dielectric layer; A source metal layer connected to the source region and the well region; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. A silicon carbide VDMOS for suppressing drain voltage overshoot as claimed in claim 1, characterized in that: A protrusion is provided on the gate dielectric layer.

3. The silicon carbide VDMOS for suppressing drain voltage overshoot according to claim 1, characterized in that: The width of the overshoot suppression structure layer is equal to the width of the protrusion.

4. A silicon carbide VDMOS for suppressing drain voltage overshoot as claimed in claim 1 or 3, characterized in that: The width of the overshoot suppression structure layer is one tenth to one sixth of the width of the drift layer.

5. The silicon carbide VDMOS for suppressing drain voltage overshoot according to claim 1, characterized in that: The distance from the bottom of the overshoot suppression structure layer to the silicon carbide substrate is 500 nm.

6. The silicon carbide VDMOS for suppressing drain voltage overshoot according to claim 1, characterized in that: The silicon carbide substrate, drift layer and source region are all N-type; the overshoot suppression structure layer and well region are all P-type.

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