Signal latch circuit and watchdog circuit system

Abstract

The utility model relates to the technical field of signal processing, and provides a signal latch circuit and a watchdog circuit system. The signal latch circuit includes: a first switching transistor; the latch circuit module is connected with the control end of the first switch transistor; the selection circuit module is connected with a state signal end capable of outputting a variable state signal and a shielding signal end capable of outputting a shielding signal, and the output end of the selection circuit module is connected with the input end of the first switching transistor; the signal latch circuit has a latch state, in the latch state, the latch circuit module conducts the first switch transistor, and the selection circuit module can respond to a first state signal output by the state signal end to output a shielding signal. According to the utility model, the latch circuit module is used for controlling the signal latch circuit to enter a latch state, and the selection circuit module is used for accurately identifying the time required to be shielded, so that the shielding of a specific signal generated in a circuit system in association with a first state signal is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of signal processing, in particular to a signal latch circuit and a watchdog circuit system. Background Art

[0002] In the field of signal processing, there is often a need to shield certain signals to achieve specific circuit design.

[0003] For example, in a circuit system configured with an external watchdog function, in order to realize the self-check of the watchdog function during the initialization phase, it is necessary to shield the reset signal of the watchdog core function. Specifically, in order to detect the effectiveness of the watchdog function and ensure that the watchdog function plays a monitoring role during the operation of the circuit system, it is necessary to self-check the watchdog function during the initialization phase. However, due to the strong coupling between the external watchdog function and the reset function, a reset signal will inevitably be issued during the watchdog self-check process, causing the monitored target chip to reset, thereby affecting the initialization time of the circuit system. If the reset signal issued during the watchdog self-check process can be shielded, the self-check of the watchdog function during the initialization phase can be successfully realized.

[0004] However, the current problems with signal shielding are: on the one hand, it is difficult to accurately identify the moment when shielding is required, and it usually requires the help of complex circuit design or complex control logic to implement; on the other hand, the circuit module used to shield specific signals of a specific circuit system relies on the implementation of the specific circuit system and cannot be flexibly applied to different circuit systems as an independent module.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Utility Model Content

[0006] In view of this, the utility model provides a signal latch circuit and a watchdog circuit system, which can accurately identify the moment when shielding is required, without the need for complex circuit design and complex control logic, and does not rely on a specific circuit system for implementation. It can be flexibly applied to different circuit systems as an independent module.

[0007] According to one aspect of the utility model, a signal latch circuit is provided, comprising: a first switching transistor; a latch circuit module connected to a control end of the first switching transistor; a selection circuit module connected to a state signal end capable of outputting a variable state signal and a shielding signal end capable of outputting a shielding signal, wherein the output end of the selection circuit module is connected to the input end of the first switching transistor; the signal latch circuit has a latching state, in which the latch circuit module turns on the first switching transistor, and the selection circuit module can output the shielding signal in response to a first state signal output by the state signal end.

[0008] In some embodiments, the output end of the first switch transistor is connected to a release signal end capable of outputting a release signal; the signal latch circuit also has an unlatched state, in which the first switch transistor is turned off, and the signal latch circuit outputs the release signal.

[0009] In some embodiments, the latch circuit module includes an energy storage element, which is connected to the connection node between the selection circuit module and the first switching transistor; in the latched state, the energy storage element is discharged; when the state signal terminal outputs a second state signal after the Nth first state signal, the signal latch circuit enters the unlatched state, where N is a positive integer.

[0010] In some embodiments, the shielding signal terminal is connected to a power supply; in the latched state, when the power supply is powered off, the signal latch circuit enters the unlocked state.

[0011] In some embodiments, the selection circuit module includes: a second switch transistor, the control end of the second switch transistor is connected to the state signal end, the input end of the second switch transistor is connected to the shielding signal end, and the output end of the second switch transistor is connected to the input end of the first switch transistor.

[0012] In some embodiments, the selection circuit module further includes any of the following electronic components: a second voltage-dividing resistor connected in series between the state signal terminal and the control terminal of the second switch transistor; a third voltage-dividing resistor connected in series between the shielding signal terminal and the input terminal of the second switch transistor.

[0013] In some embodiments, the latch circuit module includes: two latch transistors, wherein the control end of the first latch transistor is connected to the trigger signal end and the output end of the second latch transistor, and the control end of the second latch transistor is connected to the input end of the first latch transistor; two latch capacitors, wherein the first latch capacitor is connected between the input ends of the two latch transistors, one end of the second latch capacitor is connected to the input end of the second latch transistor and the control end of the first switch transistor, and the other end is connected to the input end of the first switch transistor; wherein the latch transistor can be turned on in response to the trigger signal of the trigger signal end to charge the latch capacitor, and when the latch capacitor is fully charged, the latch transistor remains turned on under the action of the latch capacitor to cause the signal latch circuit to enter the latch state.

[0014] In some embodiments, the trigger signal is a pulse signal, and the latch capacitor is fully charged after at least two pulse waves of the pulse signal.

[0015] In some embodiments, the latch circuit module also includes any of the following electronic components: a DC blocking capacitor connected in series between the trigger signal terminal and the control terminal of the first latch transistor; an anti-false touch capacitor, one end of which is connected to the control terminal of the first latch transistor and the other end is grounded.

[0016] In some embodiments, the latch circuit module also includes any of the following electronic components: a fourth voltage-dividing resistor, one end of which is connected to the trigger signal end and the control end of the first latch transistor and the other end is grounded; a diode, which is reverse-connected between the trigger signal end and the control end of the first latch transistor; a fifth voltage-dividing resistor, which is connected in series between the trigger signal end and the control end of the first latch transistor; a sixth voltage-dividing resistor, one end of which is connected to the control end of the first latch transistor and the other end is grounded; a seventh voltage-dividing resistor, which is connected in parallel at both ends of the first latch capacitor; an eighth voltage-dividing resistor, which is connected in series between the first latch capacitor and the second latch capacitor; and a ninth voltage-dividing resistor, which is connected in parallel at both ends of the second latch capacitor.

[0017] According to another aspect of the utility model, a watchdog circuit system is provided, comprising: a signal latch circuit as described in any of the above embodiments; a signal selection circuit, wherein the output end of the signal latch circuit and the reset pin of the watchdog chip are connected to a target chip through the signal selection circuit; wherein the safety shutdown path pin of the watchdog chip is connected to the status signal end, when the safety shutdown path pin outputs a first status signal representing a fault of the target chip, the reset pin outputs a reset signal for resetting the target chip; the watchdog circuit system has a watchdog self-test phase, in which the signal latch circuit is in a latched state, and the signal selection circuit can shield the reset signal in response to a shielding signal output by the signal latch circuit.

[0018] In some embodiments, when the safety shutdown path pin outputs a second state signal indicating that the target chip fault has been resolved, the signal latch circuit outputs a release signal, and the signal selection circuit can release the signal output by the reset pin in response to the release signal.

[0019] In some embodiments, the signal selection circuit is an OR gate circuit, the reset signal is a low level signal, the shielding signal is a high level signal, and the release signal is a low level signal.

[0020] In some embodiments, the target chip is provided with a trigger signal terminal, and the trigger signal terminal is connected to the signal latch circuit and is used to output a trigger signal that causes the signal latch circuit to enter the latch state.

[0021] Compared with the prior art, the beneficial effects of the present invention include at least:

[0022] The utility model controls the signal latch circuit to enter the latch state through the latch circuit module, so as to change the output of the signal latch circuit according to the change of the state signal; by selecting the circuit module to accurately identify the moment when shielding is required, there is no need for complex circuit design and complex control logic, and the variable state signal already existing in the circuit system is used to identify whether to shield or not; and the signal latch circuit of the utility model does not rely on a specific circuit system for implementation, and can be flexibly applied to different circuit systems as an independent module to achieve shielding of specific signals associated with the first state signal in the circuit system. The signal latch circuit of the utility model is particularly suitable for circuit systems in which a specific signal and a first state signal have a strong coupling relationship, and can shield the unexpected changes caused by the strong coupling relationship between the specific signal and the first state signal, thereby achieving a specific circuit design.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present utility model, and together with the specification, are used to explain the principles of the present utility model. Obviously, the accompanying drawings described below are only some embodiments of the present utility model, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0025] Figure 1 A schematic diagram of a module of a signal latch circuit in an embodiment of the utility model is shown;

[0026] Figure 2 A module schematic diagram showing another signal latch circuit in an embodiment of the utility model is shown;

[0027] Figure 3 A module schematic diagram showing another signal latch circuit in an embodiment of the utility model is shown;

[0028] Figure 4 A schematic diagram showing the structure of a signal latch circuit in an embodiment of the utility model is shown;

[0029] Figure 5 A schematic diagram showing the architecture of a watchdog circuit system in an embodiment of the present utility model is shown;

[0030] Figure 6 The signal timing diagram of the watchdog self-test system in the embodiment of the utility model is shown. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to make the present invention comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art.

[0032] The accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted.

[0033] The words "first", "second" and similar words used in the specific description do not indicate any order, quantity or importance, but are only used to distinguish different components. The term "plurality" means two or more, unless otherwise clearly and specifically defined. The term "any" means one or more, unless otherwise clearly and specifically defined. In addition, in the description of the present utility model, when it is said that a device is "connected" to another device, this includes not only the case of direct connection, but also the case of indirect connection through other elements.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in different embodiments may be combined with each other.

[0035] Figure 1 The main components of a signal latch circuit in the embodiment of the utility model are shown, and the transmission principle of the signal in the signal latch circuit in the latch state is shown; Figure 1 As shown, the signal latch circuit provided in this embodiment includes:

[0036] A first switching transistor Q1;

[0037] The latch circuit module 110 is connected to the control end of the first switch transistor Q1;

[0038] A selection circuit module 120 is connected to a state signal terminal IN1 capable of outputting a variable state signal and a shielding signal terminal IN2 capable of outputting a shielding signal, and an output terminal of the selection circuit module 120 is connected to an input terminal of the first switch transistor Q1;

[0039] The signal latch circuit has a latch state. In the latch state, the latch circuit module 110 turns on the first switch transistor Q1, and the selection circuit module 120 can output a shielding signal in response to the first state signal outputted from the state signal terminal IN1.

[0040] The first switch transistor Q1 is used to act as a switch, and a suitable transistor such as a bipolar transistor (BJT), a field effect transistor (FET) or the like may be used as the first switch transistor Q1. The bipolar transistor may be an NPN transistor or a PNP transistor, and the field effect transistor may be a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0041] The latch circuit module 110 is connected to the control end of the first switch transistor Q1, and is used to turn on the first switch transistor Q1 when needed, so that the signal latch circuit enters a latch state; in the latch state, the signal output by the output end OUT of the signal latch circuit (i.e., the output end of the first switch transistor Q1) changes with the change of the state signal output by the state signal end IN1. The latch circuit module 110 can realize latching through a transistor or a gate circuit.

[0042] The main electronic component of the selection circuit module 120 may be a transistor, which is turned on / off according to the state signal output by the state signal terminal IN1, so as to output a shielding signal at a specific moment. The main electronic component of the selection circuit module 120 may be a gate circuit, which outputs / does not output a shielding signal according to the state signal output by the state signal terminal IN1, so as to output a shielding signal at a specific moment. The selection circuit module 120 may also be composed of other electronic components, as long as it can output a shielding signal in response to the first state signal output by the state signal terminal IN1, so that the circuit system used by the signal latch circuit can shield the specific signal generated in association with the first state signal by the shielding signal, thereby realizing a specific circuit design.

[0043] Thus, the utility model controls the signal latch circuit to enter the latch state through the latch circuit module 110, so as to change the circuit output according to the change of the state signal; by selecting the circuit module 120, the moment when shielding is required is accurately identified, without the need for complex circuit design and complex control logic, and the variable state signal already existing in the circuit system is used to identify whether to shield or not; and the signal latch circuit of the utility model does not rely on a specific circuit system for implementation, and can be flexibly applied to different circuit systems as an independent module to achieve shielding of specific signals associated with the first state signal in the circuit system. The signal latch circuit of the utility model is particularly suitable for circuit systems in which a specific signal and a first state signal have a strong coupling relationship, and can shield the unexpected changes caused by the strong coupling relationship between the specific signal and the first state signal, thereby achieving a specific circuit design.

[0044] For example, the signal latch circuit of the utility model can be applied to a watchdog circuit system. The watchdog circuit system includes a watchdog chip configured with an external watchdog function and a monitored target chip; the reset pin of the watchdog chip is strongly coupled with the safety shutdown path pin, and the safety shutdown path pin is strongly coupled with the counter. When the count of the counter reaches the set value, the output of the safety shutdown path pin jumps to indicate a failure of the monitored target chip, and synchronously, the reset pin outputs a reset signal for resetting the target chip. When the signal latch circuit of this embodiment is applied to a watchdog circuit system, the safety shutdown path pin of the watchdog chip can be connected to the status signal terminal IN1, and a signal selection circuit (such as a transistor, a gate circuit, etc.) is used to receive the output of the signal latch circuit and the output of the reset pin of the watchdog chip, and then output it to the target chip to achieve "takeover" of the reset pin during the watchdog self-test phase. Specifically, during the initialization phase of the circuit system, when there is a need for watchdog self-test, the signal latch circuit can be controlled to enter a latched state so as to accurately identify the moment when shielding is required based on the output of the safety shutdown path pin of the watchdog chip; at the moment when the safety shutdown path pin outputs the first state signal representing the failure of the target chip (at this moment the reset pin will output a reset signal in response to the first state signal), the signal latch circuit outputs a shielding signal to enable the signal selection circuit to shield the signal output by the reset pin, thereby preventing the target chip from being reset during the watchdog self-test phase, and further avoiding affecting the initialization time of the circuit system, thereby resolving the contradiction between initialization and self-test caused by the inherent characteristics of the external watchdog, realizing self-test of the watchdog chip during the initialization phase, and ensuring the effectiveness of the watchdog safety mechanism during subsequent circuit system operation.

[0045] Figure 2 The main components of another signal latch circuit in the embodiment of the utility model are illustrated, and the transmission principle of the signal in the signal latch circuit in the unlocked state is illustrated; combined with Figure 1 and Figure 2 As shown, in some embodiments, the output end of the first switch transistor Q1 is connected to a release signal end RELEASE that can output a release signal; the signal latch circuit also has an unlatched state. In the unlatched state, the first switch transistor Q1 is turned off, and the signal latch circuit outputs a release signal.

[0046] The function of the release signal is opposite to that of the shielding signal. When it is necessary to release the specific signal generated in response to the first state signal so that the circuit system undergoes the expected change, that is, the need to shield the circuit system has ended, the signal latch circuit can enter the unlocked state. In the unlocked state, the first switch transistor Q1 is turned off, and the signal latch circuit constantly outputs a release signal that does not affect the specific signal, thereby releasing the specific signal generated in response to the first state signal in the circuit system, so that the circuit system can achieve normal circuit function.

[0047] For example, in a watchdog circuit system, when the watchdog self-check is completed, it is necessary to release the "takeover" of the reset pin of the watchdog chip, otherwise it will affect the normal implementation of the watchdog safety mechanism. When the signal latch circuit of this embodiment is applied to the watchdog circuit system, after the watchdog self-check phase is completed, the first switch transistor Q1 can be turned off in time and a release signal can be output, so that the signal output by the reset pin of the watchdog chip is output through the signal selection circuit, so as to ensure the integrity and effectiveness of the watchdog safety mechanism.

[0048] The voltage states of the shielding signal and the release signal are determined according to the specific signal to be shielded / released. For example, when the specific signal is a low-level signal, the shielding signal is designed to be a high-level signal and the release signal is designed to be a low-level signal with a voltage value lower than that of the specific signal. The output end of the first switch transistor Q1 can be connected to the first voltage divider resistor (R1, shown in FIG. Figure 4 The RELEASE signal terminal is grounded in the middle.

[0049] By connecting the output end of the first switch transistor Q1 to the release signal end RELEASE, it is also possible to achieve that in the latched state, when the state signal end IN1 does not output the first state signal (at this time the circuit system will not generate a specific signal that causes unexpected changes, so the circuit system does not need to be shielded), the first switch transistor Q1 outputs a release signal to avoid redundant shielding design, thereby facilitating precise shielding and enabling the selection circuit module 120 to accurately output a shielding signal in response to the first state signal.

[0050] For example, when the signal latch circuit of this embodiment is applied to a watchdog circuit system, when the counter count of the watchdog chip does not reach the set value, the safety shutdown path pin does not output the first state signal, and the reset pin does not output the reset signal; at this time, the output of the reset pin can be released, and the initialization time of the circuit system will not be affected. After the counter counts to the set value, the counter is cleared to start a new round of counting, and the output of the safety shutdown path pin will also jump with the clearing of the counter to indicate that the target chip fault has been cleared; if multiple self-tests of the watchdog chip are to be implemented, the signal latch circuit can be designed to keep the latch circuit module 110 turned on during the multiple rounds of counting of the counter.

[0051] Figure 3 The main components of another signal latch circuit in the embodiment of the utility model are shown, and the discharge principle of the latch circuit module is shown; combined with Figures 1 to 3As shown, in some embodiments, the latch circuit module 110 includes an energy storage element 111, which is connected to the connection node between the selection circuit module 120 and the first switch transistor Q1; in the latched state, the energy storage element 111 is discharged; when the state signal terminal IN1 outputs the second state signal after the Nth first state signal, the signal latch circuit enters the unlocked state, where N is a positive integer.

[0052] Before the signal latch circuit enters the latch state, the energy storage element 111 of the latch circuit module 110 can be charged through the relevant trigger signal; when the energy storage element 111 is fully charged, the latch circuit module 110 turns on the first switch transistor Q1 under the action of the energy storage element 111, so that the signal latch circuit enters the latch state. In the latch state, the energy storage element 111 can be discharged through the first switch transistor Q1; and when the selection circuit module 120 outputs a shielding signal, it has a certain reverse charging effect on the energy storage element 111. Through the design of the energy storage element 111 and the selection circuit module 120, it can be achieved that when the state signal terminal IN1 outputs the second state signal after one or more first state signals, the energy storage element 111 is discharged until the selection circuit module 120 ends the conduction effect on the first switch transistor Q1, so that the signal latch circuit enters the unlocked state.

[0053] The voltage states of the first state signal and the second state signal are determined according to the circuit system used by the signal latch circuit, for example, the first state signal is a low level signal and the second state signal is a high level signal, but not limited thereto. The output timing of the first state signal and the second state signal is also determined according to the circuit system used by the signal latch circuit, for example, the state signal terminal IN1 can output the first state signal in a specific case and output the second state signal in other cases, but not limited thereto.

[0054] In the watchdog circuit system, when the counter count of the watchdog chip reaches the set value, the safety shutdown path pin outputs the first state signal representing the target chip fault; then, the counter is cleared to start a new round of counting, and the safety shutdown path pin outputs the second state signal representing the target chip fault removal as the counter is cleared; until the counter count reaches the set value again, the safety shutdown path pin outputs the first state signal again. When the signal latch circuit of this embodiment is applied to the watchdog circuit system, according to the watchdog self-test requirements, the energy storage element 111 can be discharged in response to the Nth second state signal output by the safety shutdown path pin to end the conduction effect on the first switch transistor Q1, so that the signal latch circuit enters the unlocked state and outputs the release signal; under the action of the release signal, the signal output by the reset pin of the watchdog chip can be output through the signal selection circuit, so that the watchdog chip can reset the target chip through the reset signal when monitoring the target chip fault, to ensure the integrity and effectiveness of the watchdog safety mechanism.

[0055] Continue to combine Figures 1 to 3 As shown, in some embodiments, the shielding signal terminal IN2 is connected to the power supply; in the latched state, when the power supply is powered off, the signal latch circuit enters the unlocked state.

[0056] In the latched state, especially when the selection circuit module 120 outputs a shielding signal (i.e., the power supply signal of the power supply), if the power supply is powered off, the energy storage element 111 can be quickly discharged through the selection circuit module 120, so that the latch circuit enters the unlocked state. In this way, the signal latch circuit outputs a release signal in the case of power failure, and releases a specific signal in response to the first state signal to generate an expected change in the circuit system, so as to detect the abnormality of the signal latch circuit power failure. In addition, by actively powering off the power supply, the circuit design that uses the shielding signal for shielding can be interrupted.

[0057] For example, when the signal latch circuit of the present embodiment is applied to a watchdog circuit system, during the watchdog self-test stage, especially when the selection circuit module 120 outputs a shielding signal, if the power supply is powered off, the signal latch circuit enters an unlocked state. At this time, the signal output by the reset pin of the watchdog chip can be output through the signal selection circuit. When the reset pin outputs the reset signal, the abnormality of the power failure of the signal latch circuit can be detected. In addition, by actively powering off the power supply, the watchdog self-test stage can be interrupted, so that the circuit system can enter the normal operation stage or realize other circuit designs.

[0058] Figure 4 The circuit structure of the signal latch circuit in the embodiment of the utility model is shown; Figures 1 to 4 As shown, in some embodiments, the selection circuit module 120 includes: a second switch transistor Q2, the control end of the second switch transistor Q2 is connected to the state signal end IN1, the input end of the second switch transistor Q2 is connected to the shielding signal end IN2, and the output end of the second switch transistor Q2 is connected to the input end of the first switch transistor Q1.

[0059] The second switch transistor Q2 plays a switch role, and can be a suitable transistor such as an NPN transistor, a PNP transistor, a MOSFET, an IGBT, etc. Through the second switch transistor Q2, the design of the selection circuit module 120 can be realized with a simple circuit structure.

[0060] In a specific implementation, the second switching transistor Q2 is a PNP transistor, which can be turned on when triggered by a low-level first state signal, so that a high-level shielding signal is outputted through it; and the reset signal generated in the circuit system in response to the low-level first state signal is also a low-level signal, thereby realizing the use of a high-level shielding signal to shield a low-level reset signal.

[0061] Furthermore, in some embodiments, the selection circuit module 120 also includes any of the following electronic components: a second voltage-dividing resistor R2, connected in series between the state signal terminal IN1 and the control terminal of the second switch transistor Q2; a third voltage-dividing resistor R3, connected in series between the shielding signal terminal IN2 and the input terminal of the second switch transistor Q2.

[0062] The second voltage-dividing resistor R2 and / or the third voltage-dividing resistor R3 can be used to divide the voltage and protect the circuit where the second switch transistor Q2 is located.

[0063] Continue to combine Figures 1 to 4 As shown, in some embodiments, the latch circuit module 110 includes: two latch transistors, wherein the control end of the first latch transistor Q3 is connected to the trigger signal end IN3 and the output end of the second latch transistor Q4, and the control end of the second latch transistor Q4 is connected to the input end of the first latch transistor Q3; two latch capacitors, wherein the first latch capacitor C1 is connected between the input ends of the two latch transistors, and one end of the second latch capacitor C2 is connected to the input end of the second latch transistor Q4 and the control end of the first switch transistor Q1, and the other end is connected to the input end of the first switch transistor Q1;

[0064] Among them, the latch transistor can respond to the trigger signal of the trigger signal terminal IN3 to be turned on to charge the latch capacitor. When the latch capacitor is charged, the latch transistor remains turned on under the action of the latch capacitor, so that the signal latch circuit enters the latch state.

[0065] The latch transistor is used for latching, and suitable transistors such as NPN transistors, PNP transistors, MOSFETs, and IGBTs can be used as latch transistors. When the trigger signal terminal IN3 inputs a trigger signal, the latch transistor can be turned on to charge the latch capacitor; when the latch capacitor is fully charged, the latch transistor remains turned on for a long period of time under the action of the latch capacitor, so that the signal latch circuit enters a latched state, so that the signal output by the signal latch circuit changes with the change of the state signal output by the state signal terminal IN1. When the latch capacitor is discharged until the latch transistor is cut off, the trigger signal needs to be input again to activate the latch circuit module 110.

[0066] In a specific implementation, the first latch transistor Q3 is an NPN transistor, and the second latch transistor Q4 is a PNP transistor. When the first latch capacitor C1 and the second latch capacitor C2 are fully charged, a low-level voltage signal can be provided to the first switch transistor Q1; thus, the first switch transistor Q1 is set to a PNP transistor so that it can remain turned on under the action of a low-level voltage signal, so that the latch signal circuit enters a latched state.

[0067] In some embodiments, the trigger signal is a pulse signal, and the latch capacitor is fully charged after at least two pulse waves of the pulse signal.

[0068] The pulse signal is, for example, a pulse width modulation (PWM) signal. When the trigger signal terminal IN3 inputs a pulse signal, the first latch transistor Q3 and the second latch transistor Q4 are periodically turned on, so that the first latch capacitor C1 and the second latch capacitor C2 are charged (for example, when the pulse signal is at a high level, the first latch transistor Q3 and the second latch transistor Q4 are turned on at the same time, and the first latch capacitor C1 and the second latch capacitor C2 are charged; when the pulse signal is at a low level, the first latch transistor Q3 and the second latch transistor Q4 are turned off); when the first latch capacitor C1 and the second latch capacitor C2 are charged, the voltage of the latch circuit module 110 is stable, the first latch transistor Q3 and the second latch transistor Q4 are interlocked, and the on state is maintained, that is, the working state of the signal latch circuit is maintained, so that the first switch transistor Q1 is kept on, so that the signal latch circuit enters the latched state.

[0069] By designing the parameters of the latch transistor and the latch capacitor, the latch capacitor is fully charged after at least two pulse waves of the pulse signal, thus preventing false triggering. When the signal latch circuit is initially powered on and after power failure, the latch circuit module 110 does not work, and a trigger signal needs to be input to activate the latch circuit module 110. When the trigger signal terminal IN3 fails and cannot send a pulse signal containing at least two pulse waves, the latch circuit module 110 cannot be activated. In addition, after the signal latch circuit enters the latch state, the pulse signal of the trigger signal terminal IN3 no longer affects the latch circuit module 110, and the latch transistor is supported by the latch capacitor to be turned on for a long time. At this time, the pulse signal can stop being provided or continue to be provided.

[0070] Furthermore, in some embodiments, the latch circuit module 110 also includes any of the following electronic components: a DC blocking capacitor C3, which is connected in series between the trigger signal terminal IN3 and the control terminal of the first latch transistor Q3; an anti-false touch capacitor C4, one end of which is connected to the control terminal of the first latch transistor Q3 and the other end is grounded.

[0071] The DC blocking capacitor C3 is used to filter and isolate DC. The capacitor C4 is used to prevent false triggering to ensure that the latch circuit module 110 is activated only when a pulse signal is input to the trigger signal terminal IN3, thereby avoiding false triggering.

[0072] Further, in some embodiments, the latch circuit module 110 also includes any of the following electronic components: a fourth voltage-dividing resistor R4, one end of which is connected to the trigger signal terminal IN3 and the control end of the first latch transistor Q3, and the other end is grounded; a diode D, which is reversely connected between the trigger signal terminal IN3 and the control end of the first latch transistor Q3; a fifth voltage-dividing resistor R5, which is connected in series between the trigger signal terminal IN3 and the control end of the first latch transistor Q3; a sixth voltage-dividing resistor R6, one end of which is connected to the control end of the first latch transistor Q3, and the other end is grounded; a seventh voltage-dividing resistor R7, which is connected in parallel at both ends of the first latch capacitor C1; an eighth voltage-dividing resistor R8, which is connected in series between the first latch capacitor C1 and the second latch capacitor C2; and a ninth voltage-dividing resistor R9, which is connected in parallel at both ends of the second latch capacitor C2.

[0073] The latch circuit module 110 is provided with a voltage dividing and protection function by means of the fourth voltage dividing resistor R4 and / or the fifth voltage dividing resistor R5 and / or the sixth voltage dividing resistor R6 and / or the seventh voltage dividing resistor R7 and / or the eighth voltage dividing resistor R8 and / or the ninth voltage dividing resistor R9; the diode D is used to filter out the reverse voltage to avoid affecting the trigger signal terminal IN3.

[0074] Based on the description of the above embodiments, in a specific implementation, the signal latch circuit can be designed using the following parameters:

[0075] The capacity of the DC blocking capacitor C3 is 10nF, the resistance of the fourth voltage-dividing resistor R4 is 1kΩ, the resistance of the fifth voltage-dividing resistor R5 is 10kΩ, the capacity of the anti-false touch capacitor C4 is 100nF, the resistance of the sixth voltage-dividing resistor R6 is 47kΩ, the resistance of the seventh voltage-dividing resistor R7 is 47kΩ, the resistance of the eighth voltage-dividing resistor R8 is 22kΩ, and the resistance of the ninth voltage-dividing resistor R9 is 10kΩ; the first latch transistor Q3 adopts an NPN transistor, the second latch transistor Q4 adopts a PNP transistor, the capacity of the first latch capacitor C1 is 50nF, and the capacity of the second latch capacitor C2 is 100nF;

[0076] The first switch transistor Q1 is a PNP transistor, and the resistance of the first voltage-dividing resistor R1 is 10 kΩ;

[0077] The second switch transistor Q2 is a PNP transistor, the resistance of the second voltage-dividing resistor R2 is 10 kΩ, and the resistance of the third voltage-dividing resistor R3 is 100 kΩ;

[0078] The shielding signal terminal IN2 is connected to the power supply, which can be the power supply of the circuit system used by the signal latch circuit or the power supply of the signal latch circuit, and the power supply voltage is 5V; the trigger signal terminal IN3, the state signal terminal IN1 and the output terminal OUT of the signal latch circuit are all connected to the circuit system used by the signal latch circuit.

[0079] It should be noted that the above-mentioned specific implementation method is only an exemplary description. According to different circuit design requirements, within the technical concept framework of the present utility model, the signal latch circuit may have other designs, all of which are within the protection scope of the present utility model.

[0080] The present utility model also provides a watchdog circuit system, which uses the signal latch circuit described in any of the above embodiments to shield the reset signal during the watchdog self-test phase. The features and principles of the signal latch circuit described in any of the above embodiments can be applied to the following watchdog circuit system embodiments. In the following watchdog circuit system embodiments, the features and principles of the signal latch that have been explained will not be repeated.

[0081] Figure 5 The main structure of the watchdog circuit system in the embodiment of the utility model is shown; Figures 1 to 5 As shown, the watchdog circuit system provided in this embodiment includes:

[0082] Signal latch circuit 100;

[0083] The signal selection circuit 200, the output terminal OUT of the signal latch circuit 100 and the reset pin ROT of the watchdog chip 300 are connected to the target chip 400 through the signal selection circuit 200;

[0084] The safety shutdown path pin SS1 of the watchdog chip 300 is connected to the state signal terminal IN1, when the safety shutdown path pin SS1 outputs a first state signal representing a fault of the target chip 400, and the reset pin ROT outputs a reset signal for resetting the target chip 400;

[0085] The watchdog circuit system has a watchdog self-checking stage. In the watchdog self-checking stage, the signal latch circuit 100 is in a latching state, and the signal selection circuit 200 can respond to the shielding signal output by the signal latch circuit 100 to shield the reset signal.

[0086] The watchdog chip 300 is equipped with a watchdog function (watchdog: WDG, mainly refers to an external watchdog in the utility model, and the external watchdog has the characteristics of strong coupling of a counter, a safety shutdown path pin SS1, and a reset pin ROT), and the target chip 400 refers to the chip monitored by the watchdog chip 300; in some specific implementations, the watchdog chip 300 is a system basic chip (SBC), and the target chip 400 is a main control chip (MCU), but it is not limited to this. During the normal operation of the watchdog circuit system, the target chip 400 periodically sends a dog feeding signal to the watchdog chip 300 (the target chip 400 and the watchdog chip 300 can communicate through the MISO / MOSI pin), and the watchdog chip 300 receives the dog feeding signal, which means that the target chip 400 is normal; if the watchdog chip 300 does not receive the dog feeding signal for several consecutive cycles (the judgment condition is that the counter count of the watchdog chip 300 reaches the set value), the watchdog chip 300 will send a reset signal to reset the target chip 400. In order to ensure that the watchdog safety mechanism can function effectively when the circuit system operates normally, the watchdog chip 300 needs to be self-checked during the initialization phase of the circuit system to avoid the subsequent monitoring of the target chip 400 being affected by a fault in the watchdog chip 300.

[0087] The signal selection function of the signal selection circuit 200 can be realized by a gate circuit, which shields the reset signal when receiving a shielding signal, and releases the signal output by the reset pin ROT when not receiving the shielding signal. The signal selection circuit 200 can also be composed of transistors or other electronic components to realize the following signal selection function: when the signal latch circuit 100 responds to the first state signal output by the safety shutdown path pin SS1 and outputs a shielding signal, the reset signal output by the reset pin ROT is shielded to prevent the target chip 400 from being reset and affecting the initialization time of the watchdog circuit system; the signal output by the reset pin ROT can be released when the shielding signal is not received. Among them, the signal selection circuit 200 can be connected to the PORST pin of the target chip 400.

[0088] The watchdog circuit system of the present invention connects the safety shutdown path pin SS1 of the watchdog chip 300 to the status signal terminal IN1 of the output signal of the signal latch circuit 100, and uses the signal selection circuit 200 to receive the output of the signal latch circuit 100 and the output of the reset pin ROT of the watchdog chip 300, and outputs the signal to the target chip 400 after signal selection processing, thereby realizing the "takeover" of the reset pin ROT during the watchdog self-test stage. Specifically, during the initialization phase of the circuit system, when there is a need for watchdog self-test, the signal latch circuit 100 can be controlled to enter a latched state so as to accurately identify the moment when shielding is required based on the output of the safety shutdown path pin SS1 of the watchdog chip 300; at the moment when the safety shutdown path pin SS1 outputs the first state signal representing the failure of the target chip 400 (at this moment the reset pin ROT will output a reset signal in response to the first state signal), the signal latch circuit 100 outputs a shielding signal to enable the signal selection circuit 200 to shield the signal output by the reset pin ROT, thereby preventing the target chip 400 from being reset during the watchdog self-test phase, ensuring that the initialization time of the circuit system is not affected, thereby resolving the contradiction between initialization and self-test caused by the inherent characteristics of the external watchdog, and realizing self-test of the watchdog chip 300 during the initialization phase, so that the watchdog safety mechanism can effectively function during the subsequent operation of the circuit system.

[0089] In some embodiments, when the safety shutdown path pin SS1 outputs a second state signal indicating that the target chip 400 has been fault-free, the signal latch circuit 100 outputs a release signal, and the signal selection circuit 200 can respond to the release signal and release the signal output by the reset pin ROT.

[0090] When the watchdog self-test is completed, it is necessary to release the signal output by the reset pin ROT, so that when the watchdog chip 300 monitors the target chip 400 to fail, the reset pin ROT outputs a reset signal to reset the target chip 400, ensuring the normal implementation of the watchdog safety mechanism. In specific implementation, the signal output by the safety shutdown path pin SS1 changes with the count of the counter of the watchdog chip 300 and triggers the reset pin ROT to output the corresponding signal, so as to automatically shield and release the signal output by the reset pin ROT. After the watchdog chip 300 is awakened (for example, after power-on), the counter performs periodic counting. When the counter count reaches the set value, the safety shutdown path pin SS1 outputs a first state signal representing the failure of the target chip 400, and triggers the reset pin ROT to output a reset signal; at this time, the signal latch circuit 100 in the latched state outputs a shielding signal in response to the first state signal, so that the signal selection circuit 200 shields the reset signal in response to the shielding signal, so as to avoid the target chip 400 being reset during the watchdog self-test phase and affecting the initialization time of the watchdog circuit system. After the counter reaches the set value, the counter is cleared to start a new round of counting. The safety shutdown path pin SS1 outputs the second state signal indicating that the target chip 400 has been cleared as the counter is cleared, and the reset pin ROT outputs a non-reset signal at this time; until the counter reaches the set value again, the safety shutdown path pin SS1 outputs the first state signal again. According to the circuit design of the signal latch circuit 100, the signal latch circuit 100 can respond to the second state signal output by the safety shutdown path pin SS1 after the Nth first state signal, enter the unlocked state, and output a release signal. The release signal allows the signal output by the reset pin ROT of the watchdog chip 300 to be output through the signal selection circuit 200.

[0091] Therefore, the watchdog circuit system of this embodiment utilizes the signal latch circuit 100 and the signal selection circuit 200 to accurately identify the entry and completion times of the watchdog function in the watchdog self-test phase, timely shield the reset signal triggered by the watchdog function, prevent the target chip 400 from being reset and affecting the initialization time of the circuit system, and immediately release the reset pin ROT of the watchdog chip 300 after the watchdog self-test is completed, so that the watchdog chip 300 can promptly detect the target chip 400 fault and reset the target chip 400 during the normal operation of the circuit system, thereby ensuring the integrity and effectiveness of the watchdog safety mechanism and enabling the circuit system to have self-recovery capabilities.

[0092] The circuit design principle of the signal latch circuit 100 and the conditions for entering the latch state and releasing the latch state can be found in the description of the above-mentioned signal latch circuit embodiments, which will not be repeated here.

[0093] In some embodiments, the signal selection circuit 200 is an OR gate circuit, the reset signal is a low level signal, the shielding signal is a high level signal, and the release signal is a low level signal.

[0094] Usually, according to the configuration of the watchdog chip 300, when the target chip 400 is monitored to have a fault, the reset pin ROT outputs a low-level reset signal, and in other cases, the signal output by the reset pin ROT is a high-level signal. Therefore, by using an OR gate circuit as the signal selection circuit 200, and making the shielding signal output by the signal latch circuit 100 a high-level signal and the release signal a low-level signal, it is possible to shield the reset signal by using the shielding signal and avoid affecting the output of the reset pin ROT by using the release signal.

[0095] Furthermore, in some embodiments, the target chip 400 is provided with a trigger signal terminal IN3 , which is connected to the signal latch circuit 100 and is used to output a trigger signal that causes the signal latch circuit 100 to enter a latched state.

[0096] In the watchdog self-test stage, the target chip 400 can be deliberately not fed, and a trigger signal for simulating a fault signal can be sent to check whether the watchdog chip 300 can work normally. Under the action of the trigger signal, the signal latch circuit 100 enters the latch state, so that it can be shielded when the reset pin ROT of the watchdog chip 300 outputs the reset signal, so as to realize the self-test of the watchdog chip 300, and at the same time, it does not affect the initialization time of the circuit system.

[0097] The target chip 400 may send a trigger signal when the watchdog circuit system is powered on, that is, the target chip 400 sends a trigger signal in response to the power-on signal of the watchdog circuit system; the target chip 400 may also send a trigger signal when receiving a watchdog self-test request.

[0098] The trigger signal may be a PWM signal; using the PWM signal to latch the signal latch circuit 100 can avoid false latching caused by other signals. In addition, the signal latch circuit 100 can enter the latch state after more than two pulse waves of the PWM signal, thus avoiding false triggering.

[0099] Based on the signal latch circuit and the watchdog circuit system described in the above embodiment, the process of initializing the self-test of the watchdog chip may include:

[0100] In response to the wake-up signal, the target chip 400 outputs a trigger signal, so that the signal latch circuit 100 responds to the trigger signal and enters a latch state;

[0101] In response to the first state signal indicating a failure of the target chip 400, a shielding signal is output through the signal latch circuit 100;

[0102] The first state signal is outputted by the safety shutdown path pin SS1 of the watchdog chip 300, and the first state signal can trigger the reset pin ROT of the watchdog chip 300 to output a reset signal for resetting the target chip 400;

[0103] In response to the mask signal, the reset signal is masked by the signal selection circuit 200 .

[0104] According to the working mechanism of the watchdog chip 300, in response to the wake-up signal, the counter of the watchdog chip 300 starts counting; when the counter counts to the set value, it will trigger the safety shutdown path pin SS1 of the watchdog chip 300 to send a first state signal representing the failure of the target chip 400. Synchronously, the safety shutdown path pin SS1 will trigger the reset pin ROT of the watchdog chip 300 to send a reset signal for resetting the target chip 400.

[0105] The wake-up signal can be set according to the needs of the circuit design to perform a self-test of the watchdog chip 300 at an appropriate time. For example, if the wake-up signal is a power-on signal, a power-on self-test of the watchdog chip 300 can be implemented when the circuit system is powered on. After identifying the wake-up signal, the target chip 400 outputs a trigger signal; under the action of the trigger signal, the latch circuit module 110 of the signal latch circuit 100 turns on the first switching transistor Q1, so that the signal latch circuit 100 enters a latched state. In the latched state, the selection circuit module 120 of the signal latch circuit 100 can be turned on under the action of the first state signal and output a shielding signal; under the action of the shielding signal, the signal selection circuit 200 shields the reset signal triggered by the first state signal, thereby preventing the target chip 400 from being reset during the watchdog self-test phase, ensuring that the initialization time of the circuit system is not affected.

[0106] Therefore, the utility model utilizes the circuit design of the signal latch circuit 100 and the signal selection circuit 200 and the functions of the trigger signal and the shielding signal to effectively resolve the contradiction between initialization and self-test caused by the inherent characteristics of the external watchdog, and realizes the self-test of the watchdog chip 300 in the initialization stage, so that the watchdog safety mechanism can effectively play a role when the subsequent circuit system is running.

[0107] Furthermore, the process of initializing the self-test of the watchdog chip may also include:

[0108] In response to the second state signal indicating that the target chip 400 has been fault-free, a release signal is outputted through the signal latch circuit 100 ;

[0109] In response to the release signal, the signal output by the reset pin ROT is released through the signal selection circuit 200;

[0110] The second state signal is outputted by the safety shutdown path pin SS1 at a preset time after the first state signal is outputted, and the signal outputted by the reset pin ROT changes with the change of the signal outputted by the safety shutdown path pin SS1.

[0111] According to the working mechanism of the watchdog chip 300, after the counter counts to the set value, the counter is cleared to start a new round of counting; then, the output of the safety shutdown path pin SS1 jumps accordingly, and sends out a second state signal indicating that the fault of the target chip 400 is relieved, and synchronously, the output of the reset pin ROT also jumps. According to the circuit design of the signal latch circuit 100, when the safety shutdown path pin SS1 outputs the second state signal for several times, the circuit latch module of the signal latch circuit 100 cuts off the first switch transistor Q1, and the signal latch circuit 100 outputs a release signal. As a result, the signal selection circuit 200 releases the signal output by the reset pin ROT, and the watchdog circuit system ends the watchdog self-check stage and enters the normal operation stage; in the normal operation stage of the watchdog circuit system, if the watchdog chip 300 detects that the target chip 400 is abnormal, the reset signal can be output to the target chip 400 through the signal selection circuit 200 to ensure the integrity and effectiveness of the watchdog safety mechanism, so that the circuit system has self-recovery capability.

[0112] In some embodiments, the trigger signal ends at any time after the signal latch circuit 100 enters the latch state; or, the trigger signal is continuously output to the safety shutdown path pin SS1 to output the second state signal.

[0113] When the signal latch circuit 100 enters the latch state, the trigger signal no longer works, so the output can be stopped; in specific implementation, the output time of the trigger signal can be determined according to the parameter design of the latch circuit module 110, and the time required for the first switch transistor Q1 to turn on under the action of the trigger signal. Alternatively, the trigger signal can be continuously output until the completion time of the watchdog self-test phase (the completion time of the watchdog self-test phase is identified by outputting the second state signal through the safety shutdown path pin SS1).

[0114] Figure 6 The signal timing of the watchdog self-test system in the embodiment of the utility model during the watchdog chip self-test process is illustrated; combined with Figures 1 to 6 As shown, in a specific implementation, the watchdog self-test phase includes:

[0115] In response to the wake-up signal, the target chip 400 outputs a trigger signal in the form of a pulse wave to the signal latch circuit 100; after three pulse waves of the trigger signal (time T1), the signal latch circuit 100 enters the latch state, and the watchdog circuit system also enters the watchdog self-test stage.

[0116] In response to the wake-up signal, the counter of the watchdog chip 300 also starts counting periodically, and the counting rule is 0→2→4→6→0... The length of two consecutive counting times depends on the configuration of the watchdog chip 300, for example, 3ms.

[0117] During the counter counting period, the safety shutdown path pin SS1 outputs a high-level signal, and the reset pin ROT outputs a high-level signal. At this time, the signal latch circuit 100 outputs a low-level release signal. When the counter counts to the set value 6 (time T2), the output signal of the safety shutdown path pin SS1 is triggered to jump to a low-level signal (at time T2, the signal output by the safety shutdown path pin SS1 is the first state signal), and synchronously, the signal output by the reset pin ROT jumps to a low-level reset signal. At this time, the signal latch circuit 100 responds to the jump of the output signal of the safety shutdown path pin SS1 at time T2 (that is, responding to the first state signal) and outputs a high-level shielding signal, so that the signal selection circuit 200 shields the reset signal and outputs a high-level shielding signal, thereby preventing the target chip 400 from being reset.

[0118] Then, the counter is reset (time T3), and the output of the safety shutdown path pin SS1 jumps to a high level signal following the reset of the counter (at time T3, the signal output by the safety shutdown path pin SS1 is the second state signal). By capturing the signal output by the safety shutdown path pin SS1 at time T3, which jumps from a low level to a high level, it is determined that the watchdog self-test phase is completed. At this time, the trigger signal has stopped, and the signal latch circuit 100 responds to the jump of the signal output by the safety shutdown path pin SS1 at time T3 (that is, in response to the second state signal) and enters the unlocked state and outputs a low-level release signal; the voltage of the release signal is lower than the voltage output by the reset pin ROT, so the signal output by the signal selection circuit 200 is determined by the signal output by the reset pin ROT, so that the signal output by the reset pin ROT can act on the target chip 400. Specifically, when the reset pin ROT outputs a high-level non-reset signal, the signal selection circuit 200 outputs a high-level non-reset signal to the target chip 400; when the reset pin ROT outputs a low-level reset signal, the signal selection circuit 200 outputs a low-level reset signal to the target chip 400 to reset the target chip 400, thereby achieving effective operation of the watchdog safety mechanism.

[0119] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A signal latch circuit, characterized in that: include: a first switching transistor; A latch circuit module connected to the control end of the first switch transistor; A selection circuit module connected to a state signal terminal capable of outputting a variable state signal and a shielding signal terminal capable of outputting a shielding signal, wherein an output terminal of the selection circuit module is connected to an input terminal of the first switch transistor; The signal latch circuit has a latch state. In the latch state, the latch circuit module turns on the first switch transistor, and the selection circuit module can output the shielding signal in response to the first state signal output by the state signal terminal.

2. The signal latch circuit according to claim 1, wherein: The output end of the first switch transistor is connected to a release signal end capable of outputting a release signal; The signal latch circuit also has an unlocked latch state. In the unlocked latch state, the first switch transistor is turned off and the signal latch circuit outputs the release signal.

3. The signal latch circuit according to claim 2, characterized in that: The latch circuit module includes an energy storage element, and the energy storage element is connected to a connection node between the selection circuit module and the first switch transistor; In the latched state, the energy storage element is discharged; When the state signal terminal outputs the second state signal after the Nth first state signal, the signal latch circuit enters the unlocking state, where N is a positive integer.

4. The signal latch circuit according to claim 3, characterized in that: The shielded signal terminal is connected to a power supply; In the latched state, when the power supply is powered off, the signal latch circuit enters the unlocked state.

5. The signal latch circuit according to any one of claims 1 to 4, characterized in that: The selection circuit module comprises: A second switch transistor, wherein the control end of the second switch transistor is connected to the state signal end, the input end of the second switch transistor is connected to the shielding signal end, and the output end of the second switch transistor is connected to the input end of the first switch transistor.

6. The signal latch circuit according to claim 5, characterized in that: The selection circuit module further includes any of the following electronic components: A second voltage-dividing resistor connected in series between the state signal terminal and the control terminal of the second switch transistor; A third voltage-dividing resistor is connected in series between the shielding signal terminal and the input terminal of the second switch transistor.

7. The signal latch circuit according to any one of claims 1 to 4, characterized in that: The latch circuit module comprises: Two latch transistors, wherein a control terminal of a first latch transistor is connected to a trigger signal terminal and an output terminal of a second latch transistor, and a control terminal of the second latch transistor is connected to an input terminal of the first latch transistor; Two latch capacitors, wherein a first latch capacitor is connected between the input terminals of the two latch transistors, and a second latch capacitor has one end connected to the input terminal of the second latch transistor and the control terminal of the first switch transistor, and the other end connected to the input terminal of the first switch transistor; Among them, the latch transistor can be turned on in response to the trigger signal of the trigger signal end to charge the latch capacitor. When the latch capacitor is charged, the latch transistor remains turned on under the action of the latch capacitor, causing the signal latch circuit to enter the latch state.

8. The signal latch circuit according to claim 7, characterized in that: The trigger signal is a pulse signal, and the latch capacitor is fully charged after at least two pulse waves of the pulse signal.

9. The signal latch circuit according to claim 8, characterized in that: The latch circuit module further includes any of the following electronic components: A DC blocking capacitor connected in series between the trigger signal terminal and the control terminal of the first latch transistor; The anti-false-touch capacitor has one end connected to the control end of the first latch transistor and the other end grounded.

10. The signal latch circuit according to claim 7, characterized in that: The latch circuit module further includes any of the following electronic components: a fourth voltage-dividing resistor, one end of which is connected to the trigger signal terminal and the control terminal of the first latch transistor, and the other end of which is grounded; a diode, reversely connected between the trigger signal terminal and the control terminal of the first latch transistor; A fifth voltage-dividing resistor is connected in series between the trigger signal terminal and the control terminal of the first latch transistor; a sixth voltage-dividing resistor, one end of which is connected to the control end of the first latch transistor and the other end of which is grounded; a seventh voltage-dividing resistor connected in parallel to both ends of the first latch capacitor; an eighth voltage-dividing resistor, connected in series between the first latch capacitor and the second latch capacitor; A ninth voltage-dividing resistor is connected in parallel to both ends of the second latch capacitor.

11. A watchdog circuit system, characterized in that: include: The signal latch circuit according to any one of claims 1 to 10; A signal selection circuit, wherein the output end of the signal latch circuit and the reset pin of the watchdog chip are connected to the target chip through the signal selection circuit; Wherein, the safety shutdown path pin of the watchdog chip is connected to the state signal end, when the safety shutdown path pin outputs a first state signal representing a fault of the target chip, the reset pin outputs a reset signal for resetting the target chip; The watchdog circuit system has a watchdog self-checking stage. In the watchdog self-checking stage, the signal latch circuit is in a latching state, and the signal selection circuit can shield the reset signal in response to the shielding signal output by the signal latch circuit.

12. The watchdog circuit system according to claim 11, characterized in that: When the safety shutdown path pin outputs a second state signal indicating that the target chip fault is released, the signal latch circuit outputs a release signal, and the signal selection circuit can release the signal output by the reset pin in response to the release signal.

13. The watchdog circuit system according to claim 12, characterized in that: The signal selection circuit is an OR gate circuit, the reset signal is a low level signal, the shielding signal is a high level signal, and the release signal is a low level signal.

14. The watchdog circuit system according to claim 11, characterized in that: The target chip is provided with a trigger signal terminal, which is connected to the signal latch circuit and is used to output a trigger signal that causes the signal latch circuit to enter the latch state.

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