Data communication interface, data communication system and electronic equipment
The data communication interface enables multiple processors to share a communication module, reducing hardware complexity and pin count while enhancing electrical and EMC performance through a multi-port design with switch and logic modules.
Patent Information
- Application Number
- CN202420343549.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-23
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-02-23
AI Technical Summary
Existing systems require multiple communication modules for different processors to communicate with the same bus information, increasing hardware complexity, resource usage, and pin count.
A data communication interface with multiple ports and a switch module, logic AND module, and bidirectional switches to enable multiple processors to communicate through a single communication module, reducing the need for separate hardware circuits and pins.
Simplifies hardware design, reduces pin count, and improves electrical and EMC performance by allowing multiple processors to share a communication module, facilitating flexible and efficient data routing.
Smart Images
Figure CN222215751U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of data communication technology, and specifically relates to a data communication interface, a data communication system and an electronic device. Background Art
[0002] When two different processors need to obtain CAN (Controller Area Network) information at the same time, two independent CAN modules are usually designed and connected to different processors to achieve parallel processing and independent control. Each processor can independently receive and send CAN messages through its own CAN module.
[0003] However, each independent CAN module requires a dedicated hardware circuit to connect to the processor, which increases the complexity of hardware design and layout. In addition, each CAN module requires some processor resources and increases the number of pins.
[0004] Therefore, it is necessary to solve the technical problem that different processors need to communicate data with the same communication module through the same communication protocol. Utility Model Content
[0005] A technical purpose of the present application is to solve the technical problem that multiple communication modules are required when different processors need to obtain the same bus information, and to provide a data communication interface.
[0006] Another technical purpose of the present application is to solve the technical problem of the existing data communication system that different processors need to obtain the same bus information when multiple communication modules are required, and to provide a data communication system.
[0007] Another technical purpose of the present application is to solve the technical problem of existing electronic devices that require multiple communication modules when different processors need to obtain the same bus information, and to provide an electronic device.
[0008] This application adopts the following technical solutions.
[0009] In a first aspect, an embodiment of the present application provides a data communication interface, including:
[0010] n first data ports;
[0011] n second data ports, the first data ports corresponding to the second data ports one by one, and n is greater than or equal to 2;
[0012] A switch module, comprising 2n-2 switches, each of the switches having a first terminal and a second terminal, wherein the first terminals of the first n-1 switches are electrically connected to the second first data port to the nth first data port respectively; and the second terminals of the remaining n-1 switches are electrically connected to the second second data port to the nth second data port respectively;
[0013] A logic AND module, having n input terminals and one output terminal, wherein the n input terminals are electrically connected to the first first data port and the second terminals of the first n-1 switches respectively;
[0014] a third data port, electrically connected to the output end;
[0015] The fourth data port is electrically connected to the first terminals of the remaining n-1 switches.
[0016] In a second aspect, an embodiment of the present application provides a data communication system, including:
[0017] A data communication interface as provided in any possible implementation manner of the first aspect;
[0018] A communication module, the communication module includes a first communication port and a second communication port, the first communication port is electrically connected to the third data port, and the second communication port is electrically connected to the fourth data port.
[0019] In a third aspect, an embodiment of the present application provides an electronic device, including a data communication interface provided by any possible implementation of the first aspect;
[0020] Or, including a data communication system provided by any possible implementation of the second aspect.
[0021] Compared with the prior art, the data communication interface provided in the embodiment of the present application is provided with multiple ports, which can be connected to multiple different processors and communication modules, thereby saving communication modules, thereby reducing the complexity of product layout, and also reducing the number of interface pins, facilitating PCB layout, and improving the electrical performance and EMC performance of the product.
[0022] Compared with the prior art, the data communication system provided in the embodiment of the present application, by connecting multiple different processors and a communication module to different ports respectively, can realize that different processors need to communicate data with the same communication module through the same communication protocol, thereby reducing the complexity of product layout, and can also reduce the number of interface pins, facilitate PCB layout, and improve the electrical performance and EMC performance of the product.
[0023] Compared with the prior art, the electronic device provided in the embodiment of the present application reduces the complexity of product layout, can also reduce the number of interface pins, facilitates PCB layout, and improves the electrical performance and EMC performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0025] Figure 1 A schematic diagram of the data communication interface structure provided in Example 1 of the present application;
[0026] Figure 2 A schematic diagram of the structure of a data communication system provided in Example 2 of the present application;
[0027] Figure 3 A schematic diagram of the structure of a data communication system provided in Embodiment 3 of the present application;
[0028] Figure 4 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application;
[0029] Figure 5 A schematic diagram of the structure of an electronic device provided in another embodiment of the present application;
[0030] Reference numerals:
[0031] 10 - data communication interface, 11 - logic and module, 12 - switch module, 20 - communication module, 30 - processor, 40 - data communication system, 50 - electronic equipment. DETAILED DESCRIPTION
[0032] Reference will now be made in detail to implementations, examples of which are shown in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various implementations. However, it will be apparent to one of ordinary skill in the art that the various described implementations may be practiced without these specific details. In other cases, well-known methods, processes, components, circuits, and networks are not described in detail in order to avoid unnecessarily obscuring aspects of the implementations.
[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.
[0034] It should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0035] When two different processors 30 need to obtain CAN information at the same time, two independent CAN modules are usually designed and connected to different processors 30 respectively, so as to realize parallel processing and independent control, and each processor 30 can independently receive and send CAN messages through its own CAN module. However, each independent CAN module requires a dedicated hardware circuit to connect to the processor 30, which increases the complexity of hardware design and layout. In addition, each CAN module needs to occupy some resources of the processor 30, which increases the number of pins.
[0036] The present application provides a data communication interface 10, a data communication system 40 and an electronic device 50 to solve the technical problem that different processors 30 need to perform data communication with the same communication module 20 through the same communication protocol.
[0037] The embodiment of the present application provides a data communication interface 10, comprising: n first data ports, n second data ports, a switch module 12, a logic and module 11, a third data port and a fourth data port. The first data port corresponds to the second data port one by one, and n is an integer greater than or equal to 2.
[0038] The switch module 12 includes 2n-2 switches, each switch has a first terminal and a second terminal, the first terminals of the first n-1 switches are electrically connected to the second first data port to the nth first data port respectively; the second terminals of the remaining n-1 switches are electrically connected to the second second data port to the nth second data port respectively.
[0039] The logic AND module 11 has n input terminals and one output terminal, and the n input terminals are electrically connected to the first first data port and the second terminals of the first n-1 switches respectively.
[0040] The third data port is electrically connected to the output end.
[0041] The fourth data port is electrically connected to the first terminals of the remaining n-1 switches.
[0042] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of the data communication interface 10 provided in the first embodiment of the present application. Figure 1 In the provided embodiment, the first data port can be used as a transmitting port (TX end), and the second data port can be used as a receiving port (RX end). This embodiment includes two first data ports (TX1 and TX2) and two second data ports (RX1 and RX2).
[0043] TX1 and RX1 are a pair of transceiver ports, and TX2 and RX2 are a pair of transceiver ports. TX1 is connected to an input end of the logic AND module 11, and TX2 is connected to another input end of the logic AND module 11 after passing through a switch; the output end of the logic AND module 11 is connected to the third data port (TXD).
[0044] The fourth data port (RXD) is connected to the RX1 port, and the fourth data port (RXD) is also connected to the RX2 through a switch.
[0045] The third data port and the fourth data port can be connected to an external communication signal.
[0046] In this embodiment, when the external communication bus signal is input through the fourth data port RXD, the signal is divided into two paths, one path is input to RX2 through the switch, and the other path is directly input to RX1.
[0047] When a signal needs to be sent, after TX1 and TX2 receive the external communication bus signal, the signal received by TX1 is connected to an input pin of the logic AND gate (i.e., And gate), and the signal of TX2 is also connected to the other input end of the logic AND gate (i.e., And gate) through a bidirectional switch, and then fed back to the communication bus through the third data port TXD.
[0048] The data communication interface 10 provided in the embodiment of the present application can be connected to a communication module 20, so the communication module 20 can be saved, thereby reducing product costs, and the number of interface pins can be reduced, which facilitates PCB layout and improves the electrical performance and EMC performance of the product.
[0049] In a specific embodiment, the logic gate module may use a logic AND gate circuit, such as chip 74LS08. Chip 74LS08 can provide higher integration, smaller size and lower power consumption.
[0050] The chip 74LS08 has four AND gates, each with two inputs, which can realize logical operations.
[0051] In some embodiments, the logic gate module uses a combinational logic gate of a multi-input AND gate, which allows multiple inputs to perform a logical AND operation. For example, four two-input AND gates can be cascaded, and their outputs are connected to the input of the fifth two-input AND gate to form a five-input AND gate.
[0052] In some embodiments, the logic gate module can also be implemented using discrete components. For example, in some embodiments, the logic and module includes a bipolar transistor, all input terminals are connected to the base of the bipolar transistor, and the collector of the bipolar transistor is used as the output terminal. The three input pins are connected to the base of the transistor to control the conduction and cutoff of the transistor. When all input pins are at a high level, the transistor will be turned on and current will flow to the load resistor. The output pin is connected to the output load resistor and the collector of the transistor so that the output signal flows through the circuit normally. Connect the positive power supply (Vcc) and the negative power supply (GND) of the logic gate module to provide the power supply voltage.
[0053] In this embodiment, the switch is a bidirectional switch, which is an electrical switch used to control the direction of current flow in a circuit. It switches between two states of open and closed, and allows current to flow in different directions.
[0054] like Figure 1 As shown, the first terminal of the switch is such as the Z terminal, and the second terminal is such as the Y terminal. The switch may also include a control terminal E terminal. In some embodiments, the bidirectional switch may also be implemented by a relay. The connection between the Z terminal and the Y terminal is operated by controlling the current of the E terminal. When the current of the E terminal meets a certain condition, the relay attracts the coil to connect the Z terminal and the Y terminal. When the current of the E terminal does not meet the condition, the coil relaxes and disconnects the Z terminal and the Y terminal.
[0055] Please refer to Figure 2 This embodiment provides a data communication system 40, including the data communication interface 10 and the communication module 20 as described above; the communication module 20 includes a first communication port and a second communication port, the first communication port is electrically connected to the third data port TXD, and the second communication port is electrically connected to the fourth data port RXD.
[0056] In this embodiment, the data communication interface 10 includes three pairs of transceiver ports, namely TX1\RX1, TX2\RX2 and TX3\RX3. TX2 and TX3 are respectively input to two input ends of the logic and module 11 after passing through switches, TX1 is input to another input end of the logic and module 11, and the output end of the logic and module 11 is electrically connected to the third interface TXD.
[0057] RX2 and RX3 are electrically connected to the fourth data port via switches respectively, and RX1 is directly electrically connected to the fourth data port.
[0058] In this embodiment, the communication module 20 is a CAN transceiver, and the third data port TXD and the fourth data port RXD are respectively electrically connected to the TXD port and the RXD port of the communication module 20. In this embodiment, the three transceiver pairs can be respectively connected to the corresponding communication interfaces of the three processors 30, so that the three processors 30 (such as MCU, SOC1, SOC2) can communicate data with the same communication module 20 through the same communication protocol. The hardware layout of the whole system is simple, the connection pins are few, and the overall cost is saved.
[0059] It is understandable that the data communication interface 10 provided in the embodiment of the present application is applicable to a two-wire communication protocol. In other embodiments, the data communication interface 10 and the communication module 20 may adopt any one of a CAN communication module, an RS485 communication module, a LIN communication module or a FlexRay communication module.
[0060] The CAN communication module uses the CAN bus protocol. The CAN bus uses differential signals for data transmission. Its two signal lines are called CAN_H (high) and CAN_L (low). The differential voltage is transmitted through these two lines for data communication. This makes the CAN bus have strong anti-interference and anti-noise capabilities.
[0061] The RS485 communication module uses the RS485 bus protocol, which is a multi-point, half-duplex serial communication protocol that uses a pair of differential signal lines (A line and B line) for communication. It can support data communication of multiple nodes and is suitable for applications with long-distance transmission and high anti-interference requirements.
[0062] The LIN communication module uses the LIN bus, which is a low-cost, low-speed serial communication protocol used to connect electronic devices inside the vehicle 50. It is mainly used to transmit simple commands and data. Compared with the high-speed CAN bus, the LIN bus has advantages in cost, complexity and power consumption.
[0063] The FlexRay communication module uses the FlexRay bus protocol. FlexRay is a high-speed, real-time serial communication protocol used to connect complex control systems inside vehicles. The FlexRay bus protocol uses two lines for communication at the physical layer, which are the data line and the clock line.
[0064] In some embodiments, each first port is also electrically connected to a corresponding first pin, and each second port is also electrically connected to a corresponding second pin. The first pin and the second pin may be provided on a system-on-a-chip (SOC), a central processing unit (CPU), a programmable logic gate array chip, or a microcontroller unit (MCU).
[0065] SOC (System-on-a-Chip) refers to a system on a chip, which is a chip that integrates the functions of a complete computer system. Unlike traditional microprocessors 30 or microcontrollers, SOC integrates the processor 30, memory, input / output interfaces, peripherals and other related functions on one chip.
[0066] MCU (Microcontroller Unit) refers to a microcontroller unit, which is an integrated circuit chip that integrates a central processing unit 30 (CPU), memory (RAM and ROM), input / output interface (I / O), timer / counter (Timer / Counter) and other functional modules.
[0067] CPU (Central Processing Unit) is the core component in the computer system responsible for executing instructions, processing data and controlling the internal operations of the computer.
[0068] FPGA (Field-Programmable Gate Array) is a programmable gate array chip, which is a flexible and reconfigurable integrated circuit. Compared with fixed-function ASIC (Application-Specific Integrated Circuit) chips, FPGA allows users to configure the functions and connections of its internal circuits as needed.
[0069] Figure 3 In the illustrated embodiment, the data communication system 40 further includes n processors 30 , and a first pin of each processor 30 is electrically connected to a corresponding first data port; a second pin of each processor 30 is electrically connected to a corresponding second data port.
[0070] The first data port and the second data port of the data communication interface 10 can be connected to corresponding pins of the processor 30 respectively, so as to realize data communication between the processor 30 and the communication module 20 .
[0071] like Figure 3As shown, when the external communication bus signal is input to the communication module 20, it is converted to the COMS level by the communication module 20, and then connected to the fourth data port RXD, the signal will be divided into two outputs, one is output to the second data port RX1 of the data communication interface 10, and is output to the second pin MCU_RX of the processor 30 (such as MCU) through the second data port RX1, and the other output is sent to another second data interface RX2 of the data communication interface 10 through the bidirectional switch, and is sent to the second pin SOC_RX of the second processor 30 (such as SOC) through the second data interface RX2. Therefore, the processor 30 and the second processor 30 can receive the external communication bus signal at the same time. In other embodiments, if more processors 30 need to receive the communication bus signal at the same time, the number of switching channels can be increased.
[0072] After receiving the external communication bus signal respectively, the MCU and SOC analyze and process the corresponding signal. The first pin MCU_TX of the MCU is connected to an input pin of the logic AND gate (i.e., And gate) through the first data port TX1, and the first pin SOC_TX of the SOC is connected to the other input end of the logic AND gate through the first data port TX2 and the bidirectional switch, and then the output signal of the logic AND gate is fed back to the communication bus through the third data port TXD. The signals sent by the first data port TX1 and the first data port TX2 cannot be sent at the same time. Therefore, in a specific embodiment, there may be a priority mechanism between the MCU and the SOC to determine which has a higher priority. Then send it in time-sharing. When one sends a signal, the other must maintain a high level. For example, when TX1 sends a signal, the switch connected to TX2 is closed and TX2 maintains a high level, TX2 can remain permanently closed, and in some embodiments, priority diagnosis can be provided, and only those with a high priority can send data first, and other channels maintain a high level. The switch can also be disconnected when there is no signal sent in any channel. This design increases the flexibility and practicality of the data communication interface. The switch connected to the second data port can be kept closed continuously, and data sent by the communication module 20 can be received at the same time. The external input signal is input irregularly, so each second data port channel needs to be kept closed.
[0073] In a specific embodiment, the processor 30 may be an MCU or SOC as described above, or may be an FPGA, etc., and no setting is required for this.
[0074] The pins on the processor 30 (which may be general input / output pins or communication pins on the processor 30 ) are connected to the first data port and the second data port of the data communication interface 10 to achieve data transmission with the communication module 20 .
[0075] See also Figure 4The embodiment of the present application further provides an electronic device 50, comprising the above data communication interface 10.
[0076] See also Figure 5 , an embodiment of the present application further provides an electronic device 50, comprising the above data communication system 40.
[0077] The electronic device 50 provided in the embodiment of the present application has a simple layout and flexible scalability, can meet the needs of different application scenarios, can realize flexible data routing and switching, enables fast data transmission between different ports, and provides more data transmission paths and options.
[0078] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
Claims
1. A data communication interface, characterized in that: include: n first data ports, where n is an integer greater than or equal to 2; n second data ports, the first data ports corresponding to the second data ports one by one; A switch module, the switch module comprising 2n-2 switches, each of the switches having a first terminal and a second terminal, wherein the first terminals of the first n-1 switches are electrically connected to the second first data port to the nth first data port respectively; and the second terminals of the remaining n-1 switches are electrically connected to the second second data port to the nth second data port respectively; A logic AND module, having n input terminals and one output terminal, wherein the n input terminals are electrically connected to the first first data port and the second terminals of the first n-1 switches respectively; a third data port, the third data port being electrically connected to the output end; A fourth data port, wherein the fourth data port is electrically connected to the first terminals of the remaining n-1 switches.
2. The data communication interface according to claim 1, characterized in that: The logic AND module includes a bipolar transistor, all the input terminals are connected to the base of the bipolar transistor, and the collector of the bipolar transistor serves as the output terminal.
3. The data communication interface according to claim 2, characterized in that: All the input terminals are connected to the power supply terminal through resistors.
4. The data communication interface according to claim 1, characterized in that: The logic and module is chip 74LS08.
5. The data communication interface according to claim 1, characterized in that: The switch is a bidirectional switch.
6. The data communication interface according to claim 5, characterized in that: The bidirectional switch is a relay.
7. A data communication system, characterized in that: include: The data communication interface as claimed in any one of claims 1 to 6; A communication module, the communication module includes a first communication port and a second communication port, the first communication port is electrically connected to the third data port, and the second communication port is electrically connected to the fourth data port.
8. The data communication system according to claim 7, characterized in that: The communication module adopts any one of a CAN communication module, an RS485 communication module, a LIN communication module or a FlexRay communication module.
9. The data communication system according to claim 7, characterized in that: Each of the first data ports is also electrically connected to a corresponding first pin, and each of the second data ports is also electrically connected to a corresponding second pin.
10. An electronic device, characterized in that: It comprises the data communication interface as claimed in any one of claims 1 to 6, or the data communication system as claimed in any one of claims 7 to 9.