Capacitor device and integrated circuit

Abstract

The utility model provides a capacitor device and an integrated circuit, in the capacitor device, a side edge of a capacitor unit is provided with an isolation ring, an upper pole plate and / or a lower pole plate of the capacitor unit is provided with an isolation plate, and fixed potential is applied to the isolation ring and the isolation plate so that the isolation ring and the isolation plate can serve as a charge shielding layer of the capacitor unit. The parasitic effect of the voltage jump process on the capacitor unit on other devices of the circuit is effectively reduced, and the interference influence of the capacitor unit on a peripheral circuit is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of capacitor design, and in particular to a capacitor device and an integrated circuit. Background Art

[0002] MOM capacitor (Metal-Oxide-Metal Capacitor) is a common capacitor device structure, widely used in integrated circuits. It consists of two metal electrodes and an oxide layer between them. It has high capacitance density and good electrical properties, and can carry ultra-high voltage in the circuit.

[0003] Due to the inherent charging and discharging properties of capacitors, coupling will occur in other nearby circuits, causing circuit signal disorder and thus causing circuit function abnormality. Therefore, how to avoid the influence of ultra-high voltage capacitors on circuit function in circuit layout is an issue that urgently needs to be improved. Utility Model Content

[0004] In order to solve the above technical problems, the present application provides a capacitor device and an integrated circuit, which can effectively solve the parasitic effects of the voltage mutation process on the capacitor on other components of the circuit and avoid the interference of the capacitor on the peripheral circuit.

[0005] According to a first aspect of the present application, a capacitive device is provided, comprising:

[0006] A capacitor unit, comprising a first plate, a second plate, and a first dielectric layer between the first plate and the second plate;

[0007] An isolation ring surrounding the capacitor unit;

[0008] a first isolation plate, which is arranged on a side of the first electrode plate away from the second electrode plate and covers the first electrode plate and a gap between the capacitor unit and the isolation ring;

[0009] A fixed potential is applied to the isolation ring and the first isolation plate, so that the isolation ring and the first isolation plate can shield the charge of the capacitor unit.

[0010] Optionally, the isolation ring includes: a plurality of metal layers, a second dielectric layer located between any two adjacent metal layers, and a plurality of vias penetrating the second dielectric layer.

[0011] The multiple vias are disposed around the capacitor unit and arranged in an array, each via is filled with a metal column, and two adjacent metal layers are connected via the multiple metal columns in the multiple vias.

[0012] Optionally, among the plurality of via holes, via holes located in adjacent rows or adjacent columns are staggered with each other.

[0013] Optionally, the first electrode plate and the first metal layer of the isolation ring are located at the same layer, and the second electrode plate and the second metal layer of the isolation ring are located at the same layer.

[0014] Optionally, the first isolation plate is a polysilicon layer, and the first isolation plate is connected to the first metal layer of the isolation ring via a plurality of metal columns.

[0015] Optionally, the first isolation plate and the third metal layer in the isolation ring are the same metal plate, and the third metal layer is located on a side of the first metal layer away from the second metal layer.

[0016] Optionally, the capacitive device further includes:

[0017] The second isolation plate is arranged on a side of the second electrode plate away from the first electrode plate, a fixed potential is applied to the second isolation plate, and a through hole is arranged on the second isolation plate, and the first electrode plate and the second electrode plate are externally connected through the through hole.

[0018] Optionally, the second isolation plate and the fourth metal layer in the isolation ring are the same metal plate, and the fourth metal layer is located on a side of the second metal layer away from the first metal layer.

[0019] Optionally, the fixed potential is a ground potential.

[0020] Optionally, when the metal layer in the isolation ring and the upper electrode plate and the lower electrode plate in the capacitor unit have corners, a chamfer is formed at each corner.

[0021] According to a second aspect of the present application, an integrated circuit is provided, which includes a capacitive device as described in any embodiment of the present application.

[0022] The beneficial effects of this application include at least:

[0023] In the embodiment of the present application, an isolation ring is provided on the side of the capacitor unit (hereinafter referred to as the capacitor), and a first isolation plate is provided at the first electrode plate of the capacitor (corresponding to either the upper electrode plate or the lower electrode plate of the capacitor). By applying a fixed potential on the isolation ring and the first isolation plate so that they can act as a charge shielding layer of the capacitor, the parasitic effects of the voltage mutation process on the capacitor on other devices in the circuit are effectively reduced, thereby avoiding the interference of the capacitor on the peripheral circuit.

[0024] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A top view of a capacitive device provided according to a first embodiment of the present application is shown;

[0026] Figure 2 Show Figure 1 A cross-sectional view of the capacitor device at line AA;

[0027] Figure 3 Show Figure 1 Schematic diagram of the arrangement of vias of the capacitor device in area P;

[0028] Figure 4 A top view of a capacitive device provided according to a second embodiment of the present application is shown;

[0029] Figure 5 Show Figure 4 Cross-sectional view of the capacitor device at line BB. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0031] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0032] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "And / or" herein is a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" refers to two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0033] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0034] Various types of passive devices, such as integrated capacitor devices, are commonly used in analog integrated circuits. These integrated capacitor devices may include metal-oxide-semiconductor (MOS) capacitor devices, pn junction capacitor devices, metal-insulator-metal (MIM), polysilicon to polysilicon capacitor devices (poly-to-poly capacitor), metal-oxide-metal (MOM) capacitor devices, and other similar capacitor device structures. Capacitor devices are typically passive components used to store charge in integrated circuits.

[0035] Taking MOM capacitor devices as an example, they usually use two layers of metal plates as flat capacitor devices. In analog circuits such as AC-DC conversion circuits, MOM capacitor devices are also often used to carry ultra-high voltage. Due to the charging and discharging properties of MOM capacitor devices, coupling phenomena will occur in other nearby circuits, causing circuit signals to become disordered, and then the functions become abnormal. Conventional avoidance methods generally avoid placing sensitive circuits near such ultra-high voltage capacitor devices during layout, or leaving a certain blank area; or the designer avoids setting overly sensitive points in the adjacent circuits of the capacitor device in circuit design. No matter which of the above methods is used, the design complexity and layout difficulty of the relevant personnel will be increased, and the risk is not controllable.

[0036] In view of the above situation, the present application provides a new capacitor device structure.

[0037] Figure 1FIG. 4 shows a top view of a capacitive device provided in the first embodiment of the present application, Figure 2 Shows Figure 1 The cross-sectional view of the capacitor device at line AA in the figure, Figure 3 Shows Figure 1 Schematic diagram of the via arrangement of the capacitor device in area P, combined with Figure 1 , Figure 2 and Figure 3 In this embodiment, the capacitor device 100 includes: a capacitor unit 120, an isolation ring 130, a dielectric layer 140 and a first isolation plate 150 arranged on a substrate 110. Among them, the capacitor unit 120 includes a first electrode plate, a second electrode plate, and a first dielectric layer between the first electrode plate and the second electrode plate. The isolation ring 130 surrounds the capacitor unit 120. The first isolation plate 150 is arranged on the side of the first electrode plate away from the second electrode plate, and covers the first electrode plate and the gap between the capacitor unit 120 and the isolation ring 130. At the same time, a fixed potential is applied to the isolation ring 130 and the first isolation plate 150, so that the isolation ring 130 and the first isolation plate 150 can achieve charge shielding for the capacitor unit 120.

[0038] In this embodiment, the substrate 110 may be any type of substrate.

[0039] The first electrode of the capacitor unit 120 is one of the upper electrode 121 and the lower electrode 122, and the second electrode of the capacitor unit 120 is the other of the upper electrode 121 and the lower electrode 122. It should be noted that, in this article, the technical solution will only be described by taking the first electrode as the lower electrode 122 and the second electrode as the upper electrode 121 as an example. Figure 2 and Figure 5 , but the technical solution of the present application is also applicable to another opposite scenario.

[0040] exist Figure 2 In the example shown, the upper plate 121 and the lower plate 122 are both metal plates, and the first dielectric layer between the upper plate 121 and the lower plate 122 corresponds to the portion of the dielectric layer 140 located between the upper plate 121 and the lower plate 122. Optionally, the dielectric layer 140 is made of conventional insulating dielectric materials.

[0041] The thickness of the upper electrode plate 121 and the lower electrode plate 122 are the same everywhere, and the distance between the upper electrode plate 121 and the lower electrode plate 122 is the same everywhere.

[0042] Optionally, the shapes of the upper plate 121 and the lower plate 122 of the capacitor unit 120 in the top view can be made into any N-gon (N is an integer greater than or equal to 4), circle, ellipse, etc. Figure 1The example shown only shows a schematic diagram of the structure when they are all rectangular, but this application scenario is not unique and fixed. In this embodiment, when the upper plate 121 and the lower plate 122 of the capacitor unit 120 have corners, such as when the shape in the top view is an N-gon, a chamfer is formed at each corner, so that the formation of a spike electric field can be avoided, which is convenient for improving the quality of the device.

[0043] The isolation ring 130 surrounds the capacitor unit 120, and there is a gap between the isolation ring 130 and the capacitor unit 120, that is, each inner side of the isolation ring 130 is spaced a certain distance from the corresponding outer sides of the upper plate 121 and the lower plate 122 of the capacitor unit 120. In some preferred examples, the distance is equal everywhere.

[0044] In a specific implementation, the isolation ring 130 includes: a plurality of metal layers (such as 1311-131x, where x is an integer greater than or equal to 2), a second dielectric layer located between any two adjacent metal layers, and a plurality of vias 132 penetrating the second dielectric layer, Figure 2 The multiple metal layers of the isolation ring 130 are stacked in a direction perpendicular to the plate of the capacitor unit 120, and each metal layer has a substantially identical structure. The second dielectric layer between any two adjacent metal layers corresponds to, for example, the portion of the dielectric layer 140 located between the two metal layers.

[0045] In some examples, reference Figure 2 , the lower plate 122 of the capacitor unit 120 and the first metal layer 1311 of the isolation ring 130 are located at the same layer, and the upper plate 121 of the capacitor unit 120 and the second metal layer 131x of the isolation ring 130 are located at the same layer. In this way, at least part of the metal layer of the isolation ring 130 can be directly manufactured and formed in the same process step as the upper plate 121 and the lower plate 122 of the capacitor unit 120, so that the capacitor device 100 can be manufactured using the existing process without adding additional process steps and costs. In the case of being able to achieve the required functions, the process flow is simpler.

[0046] Optionally, each metal layer in the isolation ring 130 and the upper plate 121 and the lower plate 122 of the capacitor unit 120 can be made of the same or different metal materials, preferably the same metal material, so as to reduce the process steps and reduce the process manufacturing cost.

[0047] The top view shape of each metal layer of the isolation ring 130 specifically follows the top view shape of the plate of the capacitor unit 120. For example, when the top view shape of the plate of the capacitor unit 120 is rectangular, the top view shape of each metal layer in the isolation ring 130 corresponds to a rectangular ring. For example, when the top view shape of the plate of the capacitor unit 120 is circular, the top view shape of each metal layer in the isolation ring 130 corresponds to a circular ring, and so on. They are not listed one by one here.

[0048] The multiple vias 132 provided on each metal layer and each second dielectric layer are specifically provided around the capacitor unit 120 and arranged in an array, and each via 132 is filled with a metal column, so that two adjacent metal layers of the isolation ring 130 are connected through the multiple metal columns in the multiple vias 132. When a fixed potential is applied, each metal layer can have the same fixed potential through the electrical connection of the multiple metal columns, and the multiple metal columns in the multiple vias 132 provided around the capacitor unit 120 also provide a larger area of ​​side charge shielding layer for the capacitor unit 120, effectively reducing the parasitic effect of the voltage mutation process on the capacitor unit 120 on other devices in the circuit, and reducing the interference effect of the capacitor unit 120 on the peripheral circuit.

[0049] In some preferred examples, among the multiple via holes 132 disposed on each metal layer and each second dielectric layer, the via holes 132 located in adjacent rows or adjacent columns are staggered with each other. Figure 1 For example, the arrangement of multiple vias in a certain area P on the metal layer 131x on the top layer of the isolation ring 130 is shown in FIG. Figure 3 In the partial area P, a plurality of vias 132 are staggeredly arranged in an array, so that there are vias 132 in any lateral and longitudinal directions of the metal layer 131x. Based on the metal pillars filled in each via 132, a metal shielding layer with a fixed potential can be present at any position of the peripheral space of the capacitor unit 120, thereby improving the charge shielding capability of the isolation ring 130 at the dielectric layer between different metal layers, so that the isolation ring can achieve a better isolation effect.

[0050] Furthermore, the above-mentioned isolation ring 130 structure cooperates with the first isolation plate (also referred to as the lower isolation plate in this embodiment) 150 that completely covers the lower plate of the capacitor unit 120 and the gap between the capacitor unit 120 and the isolation ring 130, further reducing the parasitic effects of the voltage mutation process on the capacitor unit 120 on other devices in the circuit, thereby further reducing the interference effect of the capacitor unit 120 on the peripheral circuit. In some examples, the first isolation plate 150 is a polysilicon layer, that is, the first isolation plate 150 is made of polysilicon (poly) material, and the first isolation plate 150 is connected to the first metal layer 1311 of the isolation ring 130 through a plurality of metal pillars. Optionally, the polysilicon layer can be a polysilicon layer formed in an existing back-end process to reduce process steps, or it can be a polysilicon layer made in the process of manufacturing capacitor devices. Of course, other implementations are also possible. For example, the first isolation plate 150 may be the same metal plate as the third metal layer in the isolation ring 130 , wherein the third metal layer is located on the side of the first metal layer 1311 away from the second metal layer 131x.

[0051] In a further preferred embodiment, reference Figure 4 and Figure 5 , the capacitor device 100 further includes: a second isolation plate 160 disposed on the side of the upper plate 121 of the capacitor unit 120 away from the lower plate 122, the second isolation plate 160 is also applied with the same fixed potential as the isolation ring 130 and the first isolation plate 150, and basically covers the upper plate 121 of the capacitor unit 120 and the gap between the capacitor unit 120 and the isolation ring 130, so that the second isolation plate 160 can cooperate with the isolation ring 130 and the first isolation plate 150 to achieve charge shielding of the capacitor unit 120. It can be understood that the isolation ring 130 achieves charge shielding of the space around the capacitor unit 120, the first isolation plate 150 and the second isolation plate 160 achieve charge shielding of the space above and below the capacitor unit 120, and the three cooperate to achieve a more rigorous charge shielding of the substantially entire space around the capacitor unit 120, and the shielding effect is better. Meanwhile, in this embodiment, a through hole 161 is provided on the second isolation plate 160 , and the potentials on the first plate (such as the lower plate 122 ) and the second plate (such as the upper plate 121 ) of the capacitor unit 120 are externally connected through the through hole 161 .

[0052] Optionally, in some examples, the number of through holes 161 provided on the second isolation plate 160 is one, and the potential connection lines 170 and 180 of the first electrode plate and the second electrode plate of the capacitor unit 120 are respectively led out through the same through hole 161; in other examples, the number of through holes 161 provided on the second isolation plate 160 is two, and the potential connection lines 170 and 180 of the first electrode plate and the second electrode plate of the capacitor unit 120 are respectively led out through different through holes 161, such as Figure 4 As shown, of course, Figure 4 Only one through-hole situation is shown, and other conventional designs are also possible.

[0053] In some examples, the second isolation plate 160 and the fourth metal layer in the isolation ring 130 are the same metal plate, wherein the fourth metal layer is located on the side of the second metal layer 131x away from the first metal layer 1311. Of course, other implementations are also possible, and the second isolation plate 160 can also be a polysilicon layer, that is, the second isolation plate 160 is made of polysilicon (poly) material, and in this case, the second isolation plate 160 is connected to the second metal layer 131x of the isolation ring 130 through a plurality of metal pillars.

[0054] In some preferred examples, the above-mentioned fixed potential is a ground potential. When applying a fixed potential to the isolation ring 130, the first isolation plate 150 and the second isolation plate 160, the isolation ring 130, the first isolation plate 150 and the second isolation plate 160 can be grounded to apply the ground potential. It can be understood that since the ground potential has good potential stability, it can provide a good charge shielding effect for the capacitor unit 120, so that the capacitor device provided in the embodiment of the present application will not have any adverse effects on other devices or signals of the circuit in the integrated circuit, and the shielding protection effect is better. Of course, it is also allowed to connect the isolation ring 130, the first isolation plate 150 and the second isolation plate 160 to other potential sources with good stability, so as to apply other potentials with good stability to the isolation ring 130, the first isolation plate 150 and the second isolation plate 160. The specific implementation can be reasonably selected according to the actual situation of the application scenario.

[0055] Furthermore, the present application also provides an integrated circuit, which includes the capacitor device in any embodiment of the present application.

[0056] In summary, the present application sets an isolation ring structure on the side of the capacitor unit of the capacitor device, and sets an isolation plate structure on the top and / or bottom of the capacitor unit, so that the capacitor unit is semi-enclosed or even fully enclosed and isolated by using a conductive structure such as a metal structure. By applying a fixed potential such as a ground potential to these isolation ring and isolation plate structures, the charge shielding of the capacitor unit is well achieved, and the parasitic effects of the voltage mutation process (such as the charging and discharging process) on the capacitor unit on other structures or signals of the circuit are effectively reduced, thereby avoiding the interference of the capacitor unit on the peripheral circuit.

[0057] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A capacitor device, characterized in that: include: A capacitor unit, comprising a first plate, a second plate, and a first dielectric layer between the first plate and the second plate; An isolation ring surrounding the capacitor unit; a first isolation plate, which is arranged on a side of the first electrode plate away from the second electrode plate and covers the first electrode plate and a gap between the capacitor unit and the isolation ring; A fixed potential is applied to the isolation ring and the first isolation plate, so that the isolation ring and the first isolation plate can shield the charge of the capacitor unit.

2. The capacitive device according to claim 1, wherein: The isolation ring includes: a plurality of metal layers, a second dielectric layer located between any two adjacent metal layers, and a plurality of vias penetrating the second dielectric layer. The multiple vias are disposed around the capacitor unit and arranged in an array, each via is filled with a metal column, and two adjacent metal layers are connected via the multiple metal columns in the multiple vias.

3. The capacitive device according to claim 2, wherein: Among the plurality of via holes, the via holes located in adjacent rows or adjacent columns are staggered with each other.

4. The capacitive device according to claim 2, wherein: The first electrode plate and the first metal layer of the isolation ring are located at the same layer, and the second electrode plate and the second metal layer of the isolation ring are located at the same layer.

5. The capacitive device according to claim 4, wherein: The first isolation plate is a polysilicon layer, and the first isolation plate is connected to the first metal layer of the isolation ring through a plurality of metal columns.

6. The capacitive device according to claim 4, wherein: The first isolation plate and the third metal layer in the isolation ring are the same metal plate, and the third metal layer is located on a side of the first metal layer away from the second metal layer.

7. The capacitive device according to claim 4, wherein: The capacitor device further comprises: The second isolation plate is arranged on a side of the second electrode plate away from the first electrode plate, a fixed potential is applied to the second isolation plate, and a through hole is arranged on the second isolation plate, and the first electrode plate and the second electrode plate are externally connected through the through hole.

8. The capacitive device according to any one of claims 1 to 7, wherein: The fixed potential is a ground potential.

9. The capacitive device according to claim 1, wherein: When the metal layer in the isolation ring and the upper plate and the lower plate in the capacitor unit have corners, a chamfer is formed at each corner.

10. An integrated circuit, characterized in that: The invention comprises a capacitive device as claimed in any one of claims 1 to 9.

Images