HBC battery
By designing heterostructure and passivation structures in HBC cells and combining laser process processing, the problem of high surface recombination rate affecting photoelectric conversion efficiency is solved, efficiency improvement and process simplification are achieved, and costs are reduced.
Patent Information
- Application Number
- CN202323415267.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-14
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2033-12-14
AI Technical Summary
The high surface recombination rate of existing HBC batteries affects the photoelectric conversion efficiency, resulting in low battery efficiency.
An HBC cell structure is designed, in which the second surface of the silicon wafer is divided into a first area and a second area, with an isolation area separated by an isolation area, and a heterogeneous structure and a passivation structure are adopted, including a passivation layer and a doping layer, and an isolation groove. For isolating electrodes, the anti-reflection layer is used to reduce light absorption, the electrode structure is located on the doped layer, and the mask is opened and surface treated by laser technology to form a pyramid or polished surface.
It significantly improves the photoelectric conversion efficiency, reduces the surface recombination rate, simplifies process steps, improves product yield and reduces costs.
Smart Images
Figure CN222233655U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of solar energy, and in particular relates to an HBC battery. Background Art
[0002] Heterojunction cells (HJT) have the advantages of high open circuit voltage (Voc) and high fill factor (FF), but low current is an obstacle to further efficiency improvement. The main reasons are: 1. The absorption of light by the transparent conductive film (TCO) on the front side; 2. The absorption of light by the amorphous silicon film on the front side; 3. The shading loss of the front grid line. The future development of heterojunction cells must be towards low current.
[0003] The back contact cell (IBC) is a cell technology that integrates the front and back electrodes on the back of the cell. Its significant advantages are the characteristics of no light blocking on the front side and high current.
[0004] HJT+IBC superposition technology is the key direction of future HJT technology development, which is called HJT-IBC battery, also known as HBC battery. Passivation performance is an important performance of battery photoelectric conversion efficiency. The surface recombination of HBC in the existing technology will affect the passivation performance, thereby reducing the photoelectric conversion efficiency of the battery.
[0005] Therefore, in view of the above technical problems, it is necessary to provide a HBC battery. Utility Model Content
[0006] In view of this, an object of the present invention is to provide a HBC battery to improve the photoelectric conversion efficiency.
[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present utility model is as follows:
[0008] An HBC battery, comprising:
[0009] A silicon wafer, comprising a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a first region, a second region and an isolation region, wherein the isolation region is located between the first region and the second region, and an area of the first region is 70% to 95% of an area of the second surface;
[0010] A heterostructure comprising a first passivation layer and a first doping layer stacked on the first region;
[0011] A first electrode structure is located on the first doped layer in the heterostructure;
[0012] A first passivation structure includes a second passivation layer and a second doping layer stacked on the second region;
[0013] a second electrode structure, located on the second doping layer in the first passivation structure;
[0014] A second passivation structure is located on the first surface of the silicon wafer;
[0015] The isolation structure comprises an isolation trench located on the isolation region, wherein the bottom of the isolation trench extends to the second surface of the silicon wafer or below the second surface.
[0016] In one embodiment, the area of the first region is 80% to 85% of the area of the second surface.
[0017] In one embodiment, the isolation trench has a depth of 0.1 μm to 6 μm and a width of 20 μm to 100 μm; and / or,
[0018] An insulating layer is formed in the entire or partial area of the isolation trench.
[0019] In one embodiment, the second passivation structure includes a third passivation layer and an anti-reflection layer stacked on the first surface, wherein the third passivation layer is an intrinsic amorphous silicon layer, and the anti-reflection layer includes a combination of one or more of a TCO layer, a SiNx layer, and a SiNxOy layer.
[0020] In one embodiment, the second passivation structure further includes a third doping layer located between the third passivation layer and the anti-reflection layer, and the doping type of the third doping layer is the same as the doping type of the silicon wafer.
[0021] In one embodiment, the third doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or,
[0022] The thickness of the third doping layer is 15 nm to 30 nm; and / or,
[0023] The doping concentration of the third doping layer is 1E17cm -3 ~1E22cm -3 .
[0024] In one embodiment, the first surface is a pyramid structure velvet surface or a polished surface; and / or,
[0025] The first area is a pyramid structure velvet surface or a polished surface; and / or,
[0026] The second area is a pyramid structure velvet surface or a polished surface.
[0027] In one embodiment, the first electrode structure includes a first TCO layer located on the first doping layer and a first electrode electrically contacting the first TCO layer; and / or,
[0028] The second electrode structure includes a second TCO layer located on the second doping layer and a second electrode electrically contacting the second TCO layer.
[0029] In one embodiment, the first passivation layer is an intrinsic amorphous silicon layer; and / or,
[0030] The second passivation layer is an intrinsic amorphous silicon layer; and / or,
[0031] The thickness of the first passivation layer is 5 nm to 10 nm; and / or,
[0032] The thickness of the second passivation layer is 5 nm to 10 nm.
[0033] In one embodiment, the silicon wafer is a doped silicon wafer, the doping type of the first doping layer is opposite to the doping type of the silicon wafer, and the doping type of the second doping layer is the same as the doping type of the silicon wafer; and / or,
[0034] The first doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or,
[0035] The second doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or,
[0036] The thickness of the first doping layer is 20 nm to 40 nm; and / or,
[0037] The thickness of the second doping layer is 15 nm to 30 nm; and / or,
[0038] The doping concentration of the first doping layer is 1E17cm -3 ~1E20cm -3 and / or,
[0039] The doping concentration of the second doping layer is 1E17cm -3 ~1E22cm -3 .
[0040] The utility model has the following beneficial effects:
[0041] The HBC battery of the utility model combines the advantages of the HJT battery and the IBC battery. Both the front and back sides adopt a passivation structure to reduce the surface recombination rate. The passivation effect is good and the photoelectric conversion efficiency can be significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0043] Figure 1 This is a schematic diagram of the structure of an HBC battery in a specific embodiment of the utility model;
[0044] Figures 2a to 2k The present invention is a process flow chart for preparing HBC batteries in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0045] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0046] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0047] The utility model discloses an HBC battery, comprising:
[0048] A silicon wafer, comprising a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a first region, a second region and an isolation region, wherein the isolation region is located between the first region and the second region, and an area of the first region is 70% to 95% of an area of the second surface;
[0049] A heterostructure comprising a first passivation layer and a first doping layer stacked on the first region;
[0050] A first electrode structure is located on the first doped layer in the heterostructure;
[0051] A first passivation structure includes a second passivation layer and a second doping layer stacked on the second region;
[0052] a second electrode structure, located on the second doping layer in the first passivation structure;
[0053] A second passivation structure is located on the first surface of the silicon wafer;
[0054] The isolation structure comprises an isolation trench located on the isolation region, wherein the bottom of the isolation trench extends to the second surface of the silicon wafer or below the second surface.
[0055] The present invention is further described below in conjunction with specific embodiments.
[0056] Ginseng Figure 1 As shown, the HBC battery in a specific embodiment of the utility model includes:
[0057] A silicon wafer 10, which is a doped silicon wafer, comprises a first surface S1 and a second surface which are arranged opposite to each other, wherein the second surface comprises a first region S21, a second region S22 and an isolation region S23, wherein the isolation region S23 is located between the first region S21 and the second region S22, and the area of the first region S21 is greater than the area of the second region S22;
[0058] A heterostructure, comprising a first passivation layer 21 and a first doping layer 22 stacked on the first region S21, wherein the doping type of the first doping layer 22 is opposite to the doping type of the silicon wafer 10;
[0059] A first electrode structure, located on the first doped layer 22 in the heterostructure;
[0060] A first passivation structure includes a second passivation layer 31 and a second doping layer 32 stacked on the second region S22, wherein the doping type of the second doping layer 32 is the same as the doping type of the silicon wafer 10;
[0061] A second electrode structure, located on the second doping layer 32 in the first passivation structure;
[0062] A second passivation structure is located on the first surface of the silicon wafer;
[0063] The isolation structure includes an isolation trench 70 located on the isolation region S23 , and the bottom of the isolation trench 60 extends to the second surface of the silicon wafer 10 or below the second surface.
[0064] Exemplarily, the silicon wafer 10 in this embodiment is described by taking an N-type silicon wafer (i.e., N-type doping) as an example. The doping type of the first doping layer 22 is opposite to the doping type of the silicon wafer 10, which is P-type doping (such as boron doping, etc.), and the doping type of the second doping layer 32 is the same as the doping type of the silicon wafer 10, which is N-type doping (such as phosphorus doping, etc.).
[0065] In this embodiment, the first region S21 is a PN junction region, and the area of the first region S21 is 70% to 95% of the area of the second surface. Preferably, the area of the first region S21 is 80% to 85% of the area of the second surface.
[0066] Furthermore, in the heterogeneous structure of this embodiment, the first passivation layer 21 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the first doping layer 22 is a P-type doped amorphous silicon layer or a microcrystalline silicon layer with a thickness of 20nm to 40nm and a doping concentration of 1E17cm -3 ~1E20cm-3 .
[0067] The second region S22 in this embodiment is a back surface field passivation region. Preferably, in the first passivation structure, the second passivation layer 31 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the second doped layer 32 is an N-type doped amorphous silicon layer or a microcrystalline silicon layer with a thickness of 15nm to 30nm and a doping concentration of 1E17cm -3 ~1E22cm -3 .
[0068] In addition, the first electrode structure in this embodiment includes a first TCO layer 51 located on the first doping layer 22 and a first electrode 61 electrically contacting the first TCO layer 51 , and the second electrode structure includes a second TCO layer 52 located on the second doping layer 32 and a second electrode 62 electrically contacting the second TCO layer 52 .
[0069] Specifically, the TCO (transparent conductive oxide) layer may be one or more of ITO, AZO, IWO, etc. The first electrode 61 and the second electrode 62 are metal grid line electrodes, and the material thereof may be Ag or Ag / Cu alloy.
[0070] An isolation groove 70 is formed on the third region S23 in this embodiment. The isolation groove can isolate the epitaxial layer on the first region S21 and the second region S22 to avoid short circuit between the two regions. Specifically, the first passivation layer 21 and the second passivation layer 31, the first doping layer 22 and the second doping layer 32, and the first TCO layer 51 and the second TCO layer 52 are all electrically isolated by the isolation groove 70. The depth of the isolation groove (the distance from the first TCO layer 51 to the bottom of the groove) is 0.1μm to 6μm, and the width is 20μm to 100μm.
[0071] Furthermore, an insulating layer (not shown) is formed in all or part of the isolation trench 70, and the isolation effect can be further improved by the provision of the insulating layer. In this embodiment, the isolation trench 70 extends to the surface of the silicon wafer, and an extremely thin (about 1 nm thick) natural oxide layer (i.e., silicon oxide layer) is formed on the bottom wall and sidewall of the isolation trench.
[0072] In this embodiment, the first surface S1 is a front passivation area, and the second passivation structure thereon includes a third passivation layer 41 and an anti-reflection layer 53 stacked on the first surface S1, wherein the third passivation layer 41 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the anti-reflection layer 53 includes a combination of one or more of a TCO layer, a SiNx layer, a SiNxOy layer, etc., preferably a TCO layer.
[0073] Furthermore, in other embodiments, the second passivation structure further includes a third doping layer 42 located between the third passivation layer 41 and the anti-reflection layer 53. The third doping layer 42 is an amorphous silicon layer or a microcrystalline silicon layer, with a thickness of 15 nm to 30 nm, and the doping type is the same as that of the silicon wafer 10, which is N-type doping, and the doping concentration is 1E17 cm -3 ~1E22cm -3 .
[0074] For example, in this embodiment, the first surface S1 and the first area S21 are pyramid-structured velvet surfaces, and the light trapping effect is improved by the pyramid velvet structure, and the second area S22 is a polished surface. In other embodiments, the first surface S1 and the first area S21 may also be polished surfaces, and the second area S22 may also be a pyramid velvet structure, which will not be described one by one here.
[0075] The front and back sides of the HBC battery of the utility model both adopt passivation structures to reduce the surface recombination rate, and the amorphous silicon layer has a good passivation effect, which can significantly improve the photoelectric conversion efficiency, and the photoelectric conversion efficiency can be improved by at least 0.3% compared with the conventional BC battery.
[0076] Ginseng Figures 2a to 2k As shown, a method for preparing an HBC battery in a specific embodiment of the utility model comprises the following steps:
[0077] 1. Ginseng Figure 2a As shown, a silicon wafer 10 is provided. The silicon wafer is an N-type silicon wafer, including a first surface S1 and a second surface arranged opposite to each other. The second surface includes a first region S21, a second region S22 and an isolation region S23. The isolation region S23 is located between the first region S21 and the second region S22. The area of the first region S21 is larger than that of the second region S22.
[0078] In this embodiment, the first surface S1 of the silicon wafer is a front passivation area, the first area S21 in the second surface is a PN junction area, and the second area S22 is a back surface field passivation area. The first area S21 and the second area S22 are isolated by an isolation area 23. Preferably, the area of the first area S21 is 70% to 95% of the area of the second surface.
[0079] Illustratively, in this embodiment, a pyramid texture structure is first formed on the first surface and the second surface of the silicon wafer 10 through an alkali (such as NaOH solution) texturing process to trap light, and the size of the pyramid is 0.5 μm to 5 μm.
[0080] 2. Ginseng Figure 2b As shown, a first passivation layer 21 and a first doping layer 22 are sequentially deposited on the second surface by a double-sided PECVD (plasma enhanced chemical vapor deposition) process, and a third passivation layer 41 and a third doping layer 42 are sequentially deposited on the first surface S1.
[0081] Exemplarily, the first passivation layer 21 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the first doping layer 22 is a P-type doped amorphous silicon layer or a microcrystalline silicon layer with a thickness of 20nm to 40nm and a doping concentration of 1E17cm -3 ~1E20cm -3 The third passivation layer 41 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the third doping layer 42 is an N-type doped amorphous silicon layer or a microcrystalline silicon layer with a thickness of 15nm to 30nm and a doping concentration of 1E17cm -3 ~1E22cm -3 .
[0082] In other embodiments, only the third passivation layer 41 may be deposited on the first surface S1 of the silicon wafer without depositing the third doping layer 42 .
[0083] 3. Ginseng Figure 2c As shown, a first mask 81 is deposited on the first doping layer 22 and a second mask 82 is deposited on the third doping layer 42 by a double-sided PECVD (plasma enhanced chemical vapor deposition) process.
[0084] The first mask 81 and the second mask 82 may be any one of a SINx mask, a SiNxOy mask, a SiOx mask, etc., as masks for subsequent processes. For example, the SINx mask is used as an example in this embodiment, and its thickness is 40nm to 120nm, preferably 70nm to 80nm.
[0085] 4. Ginseng Figure 2d As shown, the first mask 81 on the second region S22 and the isolation region S23 is patterned and opened by laser technology, and the first passivation layer 21 and the first doping layer 22 on the second region S22 and the isolation region S23 are removed, thereby obtaining Figure 2e The structure shown.
[0086] First, the laser wavelength in the laser process of this step is 495nm-570nm, the pulse width is 10ns-50ns, the power is 5W-30W, the on-off ratio is 30%-80%, and the scribing speed is 15m / s-25m / s. The laser film opening depth is controlled by the above process parameters to completely remove the first mask 81 on the second area S22 and the isolation area S23. Exemplarily, in this embodiment, a green laser with a wavelength of 532nm is used for film opening.
[0087] In other embodiments, all or part of the first passivation layer 21 and the first doping layer 22 on the second region S22 and the isolation region S23 may be removed continuously by controlling the process parameters.
[0088] Then, the second region S22 and the isolation region S23 on the second surface of the silicon wafer are processed by an alkali (such as NaOH solution) etching process to form a polished surface.
[0089] Of course, in other embodiments, the second region S22 and the isolation region S23 on the second surface of the silicon wafer may be processed by an alkali (such as NaOH solution) texturing process to form a pyramid textured structure.
[0090] Among them, the alkaline etching process and the alkaline texturing process are conventional processing processes in this field and will not be described in detail here.
[0091] 5. Ginseng Figure 2f As shown, the second passivation layer 31 , the second doping layer 32 and the third mask 83 are sequentially deposited on the second region S22 , the isolation region S23 and the first mask 81 through a single-sided PECVD process.
[0092] Exemplarily, the second passivation layer 31 is an intrinsic amorphous silicon layer with a thickness of 5nm to 10nm, and the second doping layer 32 is an N-type doped amorphous silicon layer or a microcrystalline silicon layer with a thickness of 15nm to 30nm and a doping concentration of 1E17cm -3 ~1E22cm -3 .
[0093] In addition, the third mask 83 can be any one of a SINx mask, a SiNxOy mask, a SiOx mask, etc., as a mask for subsequent processes. For example, the SINx mask is used as an example for description in this embodiment, and its thickness is 40nm to 120nm, preferably 70nm to 80nm.
[0094] 6. Patterning and opening the third mask on the first region and the isolation region by laser process, and removing the second passivation layer and the second doping layer on the first region and the isolation region.
[0095] First, the laser wavelength in the laser process of this step is 380nm~450nm, the pulse width is 10ns~50ns, the power is 5W~20W, the switching ratio is 30%~80%, and the scribing speed is 15m / s~25m / s. The laser film opening depth is controlled by the above process parameters to completely remove the third mask 83 on the first area S21 and the isolation area S23.
[0096] In this step, the film opening depth of the laser process needs to be controlled to avoid damaging the first passivation layer 21 and the first doping layer 22 at the bottom of the first region S21, so the control of laser parameters is particularly important. For example, in this embodiment, a violet laser with a wavelength of 400 nm is selected for film opening.
[0097] In other embodiments, the portion of the second passivation layer 31 and the second doping layer 32 on the first region S21 and the isolation region S23 may be removed continuously by controlling the process parameters.
[0098] Then, the first region S21 and the isolation region S23 on the second surface of the silicon wafer are processed by an alkali etching process (such as NaOH solution) to remove the second passivation layer 31 and the second doping layer 32 on the first region S21 and the isolation region S23.
[0099] 7. Remove the second mask 82 on the first surface S1 of the silicon wafer and the first mask 81 and the third mask 83 on the second surface of the silicon wafer to form an isolation trench 70 on the isolation region S23.
[0100] Ginseng Figure 2h As shown, the second mask 82 on the first surface S1, the first mask 81 on the first region S21, and the third mask 83 on the second region S22 and the isolation region S23 are removed by an acid (such as HF solution with a mass fraction of 5%) etching process.
[0101] 8. Prepare a first electrode structure on the first doping layer 22 , prepare a second electrode structure on the second doping layer 22 , and prepare an anti-reflection layer 53 on the third doping layer 42 .
[0102] Exemplarily, the preparation of the first electrode structure and the second electrode structure in this embodiment is specifically as follows:
[0103] Ginseng Figure 2i As shown, a TCO layer is prepared on the first doping layer 22 and the second doping layer 22 and in the isolation trench 70;
[0104] Ginseng Figure 2j As shown, the TCO layer in the isolation groove 70 is removed by a laser process. The laser wavelength in the laser process in this step is 380nm-570nm, the pulse width is 10ns-50ns, the power is 5W-30W, the switching ratio is 30%-80%, and the scribing speed is 15m / s-25m / s. The laser processing depth (i.e., the isolation groove depth) is controlled to be 0.1μm-6μm and the width is 20μm-100μm by the above process parameters, so as to form an electrically isolated first TCO layer 51 and a second TCO layer 52 on the first doping layer 22 and the second doping layer 32, respectively.
[0105] Ginseng Figure 2k As shown, a first electrode 61 electrically contacting the first TCO layer 51 is formed on the first TCO layer 51 , and a second electrode 62 electrically contacting the second TCO layer 52 is formed on the second TCO layer 52 .
[0106] Preferably, the metal electrode (the first electrode 61 or the second electrode 62) is prepared by screen printing using a conductive paste, wherein the conductive paste is a low-temperature silver paste or a silver-copper paste, and the curing temperature is 190°C to 220°C.
[0107] In addition, the anti-reflection layer in this embodiment includes a combination of one or more of a TCO layer, a SiNx layer, and a SiNxOy layer. If the anti-reflection layer is a TCO layer, the preparation of the layer can be carried out in the same process as the preparation of the back TCO layer; if the anti-reflection layer is a SiNx layer or a SiNxOy layer, an additional process is required, but the anti-reflection effect of the SiNx layer or the SiNxOy layer is better than that of the TCO layer.
[0108] It can be seen from the above technical solutions that the utility model has the following beneficial effects:
[0109] The HBC battery of the utility model combines the advantages of HJT battery and IBC battery. Both the front and back sides adopt passivation structures to reduce the surface recombination rate, and the passivation effect is good, which can significantly improve the photoelectric conversion efficiency.
[0110] The utility model adopts laser technology to carry out patterning film opening of the mask, and can use the existing equipment of the battery production line without adding additional photolithography equipment, thus simplifying the process steps, improving the product yield and reducing the process cost.
[0111] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.
[0112] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A HBC battery, characterized in that: The HBC battery comprises: A silicon wafer, comprising a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a first region, a second region and an isolation region, wherein the isolation region is located between the first region and the second region, and an area of the first region is 70% to 95% of an area of the second surface; A heterostructure comprising a first passivation layer and a first doping layer stacked on the first region; A first electrode structure is located on the first doped layer in the heterostructure; A first passivation structure includes a second passivation layer and a second doping layer stacked on the second region; a second electrode structure, located on the second doping layer in the first passivation structure; A second passivation structure is located on the first surface of the silicon wafer; The isolation structure comprises an isolation trench located on the isolation region, wherein the bottom of the isolation trench extends to the second surface of the silicon wafer or below the second surface.
2. The HBC battery according to claim 1, characterized in that: The area of the first region is 80% to 85% of the area of the second surface.
3. The HBC battery according to claim 1, characterized in that: The isolation groove has a depth of 0.1 μm to 6 μm and a width of 20 μm to 100 μm; and / or, An insulating layer is formed in the entire or partial area of the isolation trench.
4. The HBC battery according to claim 1, characterized in that: The second passivation structure includes a third passivation layer and an anti-reflection layer stacked on the first surface, wherein the third passivation layer is an intrinsic amorphous silicon layer, and the anti-reflection layer includes a combination of one or more of a TCO layer, a SiNx layer, and a SiNxOy layer.
5. The HBC battery according to claim 4, characterized in that: The second passivation structure further includes a third doping layer located between the third passivation layer and the anti-reflection layer, and the doping type of the third doping layer is the same as the doping type of the silicon wafer.
6. The HBC battery according to claim 5, characterized in that: The third doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or, The thickness of the third doping layer is 15 nm to 30 nm.
7. The HBC battery according to claim 1, characterized in that: The first surface is a pyramid structure velvet surface or a polished surface; and / or, The first area is a pyramid structure velvet surface or a polished surface; and / or, The second area is a pyramid structure velvet surface or a polished surface.
8. The HBC battery according to claim 1, characterized in that: The first electrode structure includes a first TCO layer located on the first doping layer and a first electrode electrically contacting the first TCO layer; and / or, The second electrode structure includes a second TCO layer located on the second doping layer and a second electrode electrically contacting the second TCO layer.
9. The HBC battery according to claim 1, characterized in that: The first passivation layer is an intrinsic amorphous silicon layer; and / or, The second passivation layer is an intrinsic amorphous silicon layer; and / or, The thickness of the first passivation layer is 5 nm to 10 nm; and / or, The thickness of the second passivation layer is 5 nm to 10 nm.
10. The HBC battery according to claim 1, characterized in that: The silicon wafer is a doped silicon wafer, the doping type of the first doping layer is opposite to the doping type of the silicon wafer, and the doping type of the second doping layer is the same as the doping type of the silicon wafer; and / or, The first doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or, The second doped layer is an amorphous silicon layer or a microcrystalline silicon layer; and / or, The thickness of the first doping layer is 20 nm to 40 nm; and / or, The thickness of the second doping layer is 15 nm to 30 nm.