Switching circuit and electronic device

Abstract

The embodiment of the utility model provides a switching circuit and electronic equipment. The switching circuit comprises a switching transistor; the switch control circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a capacitor and a seventh transistor, the grid electrode of the first transistor is used for receiving the first clock signal, and the grid electrode of the fourth transistor is used for receiving the third clock signal; the input end of the first phase inverter receives an initial clock signal, and the output end of the first phase inverter outputs a first clock signal; the input end of the second phase inverter receives the initial clock signal, and the output end of the second phase inverter outputs a third clock signal; the transmission delay when the first inverter inputs the low level is smaller than the transmission delay when the second inverter inputs the low level. The embodiment of the utility model is at least beneficial to improving the performance of the bootstrapped gate voltage switch circuit.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of electronic circuits, and in particular to a switch circuit and an electronic device. Background Art

[0002] As the degree of digitization of signal processing chips continues to increase, the requirements for converting analog signals into digital signals continue to increase, requiring the analog-to-digital converter to have a higher sampling rate when sampling analog signals, which requires the use of a gate voltage bootstrap switching circuit.

[0003] Specifically, circuit designers often control the gate voltage of the MOS tube to determine whether the source and drain terminals are conducting, thereby achieving the purpose of switching. However, when the MOS tube is conducting and its source voltage increases to a high level, the conduction performance of the MOS tube will be affected, which has an impact on the transmission of sensitive signals. At this time, it is often necessary to increase the gate voltage synchronously to keep the voltage difference between the gate voltage and the source voltage stable to ensure good conduction performance of the MOS tube. The gate voltage bootstrap switch circuit can theoretically get rid of the dependence of the gate-source voltage VGS of the MOS tube on the input signal, so that the gate-source voltage VGS of the MOS tube is constant, improve the linearity of the on-resistance, and reduce harmonics.

[0004] However, the performance of the current gate voltage bootstrap switching circuit needs to be improved. Utility Model Content

[0005] The embodiments of the present disclosure provide a switch circuit and an electronic device, which are at least beneficial to improving the performance of a gate voltage bootstrap switch circuit.

[0006] On the one hand, an embodiment of the present disclosure provides a switching circuit, including: a switching transistor, the drain of the switching transistor serves as an input end of the switching circuit, and the source of the switching transistor serves as an output end of the switching circuit; a switching control circuit, the switching control circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a capacitor and a seventh transistor, wherein the source of the first transistor is connected to ground, the gate of the first transistor receives a first clock signal, the source of the second transistor is connected to the drain of the first transistor, the drain of the second transistor is connected to the source of the switching transistor, the gate of the second transistor is connected to the gate of the sixth transistor, the source of the sixth transistor is connected to a power supply voltage, the gate of the sixth transistor is connected to the gate of the switching transistor, the drain of the sixth transistor is connected to a first end of the capacitor, the second end of the capacitor is connected to the drain of the first transistor, the source of the seventh transistor is connected to the gate of the sixth transistor, and the The drain is connected to the first end of the capacitor, the gate of the seventh transistor is used to receive the second clock signal, the source of the third transistor is connected to the drain of the first transistor, the drain of the third transistor is connected to the gate of the seventh transistor, the gate of the third transistor is connected to the gate of the switching transistor, the source of the fourth transistor is connected to the ground, the gate of the fourth transistor is used to receive the third clock signal, the drain of the fourth transistor is connected to the source of the fifth transistor, the drain of the fifth transistor is connected to the gate of the sixth transistor, and the gate of the fifth transistor is connected to the power supply voltage; a first inverter, the input end of the first inverter receives the initial clock signal, and the output end of the first inverter outputs the first clock signal to the gate of the first transistor; a second inverter, the input end of the second inverter receives the initial clock signal, and the output end of the second inverter outputs the third clock signal to the gate of the fourth transistor; wherein the transmission delay when the first inverter inputs a low level is less than the transmission delay when the second inverter inputs a low level.

[0007] In some embodiments, the sixth transistor and the seventh transistor are both PMOS transistors, and the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all NMOS transistors.

[0008] In some embodiments, the first inverter includes an eighth transistor and a ninth transistor, the eighth transistor is a PMOS transistor, the second inverter includes a tenth transistor and an eleventh transistor, the tenth transistor is a PMOS transistor, and the channel width-to-length ratio of the eighth transistor is greater than the channel width-to-length ratio of the tenth transistor.

[0009] In some embodiments, a ratio of a channel width-to-length ratio of the eighth transistor to a channel width-to-length ratio of the tenth transistor is 1.8-2.2.

[0010] In some embodiments, a channel width-to-length ratio of the eighth transistor is 3-4, and a channel width-to-length ratio of the tenth transistor is 1-2.

[0011] In some embodiments, the switch circuit further includes a third inverter, an input terminal of the third inverter receives an initial clock signal, and an output terminal of the third inverter outputs a second clock signal to the gate of the seventh transistor.

[0012] In some embodiments, the channel width-to-length ratio of the PMOS transistor of the third inverter is equal to the channel width-to-length ratio of the PMOS transistor of the second inverter.

[0013] In some embodiments, the initial clock signal is a square wave clock signal.

[0014] In some embodiments, the switch control circuit further includes a resistor, and the gate of the fifth transistor is connected to the power supply voltage through the resistor.

[0015] Another aspect of the embodiments of the present disclosure further provides an electronic device, comprising at least a switch circuit as described in any one of the above embodiments.

[0016] The technical solution provided by the embodiment of the present disclosure has at least the following advantages: when the initial clock signal changes from a high level to a low level, the first transistor is turned on in advance to discharge the second end of the capacitor, thereby causing the voltage at the first end of the capacitor to drop, thereby alleviating the phenomenon that the source-drain voltage of the fifth transistor periodically exceeds the rated voltage range, which is beneficial to improving the performance of the gate voltage bootstrap switch circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the circuit structure of a switch circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] As can be seen from the background technology, the performance of the current gate voltage bootstrap switch circuit needs to be improved.

[0020] In the switching circuit provided by the embodiment of the present disclosure, when the initial clock signal changes from a high level to a low level, the first transistor is turned on in advance to discharge the second end of the capacitor, thereby causing the voltage at the first end of the capacitor to drop, thereby alleviating the phenomenon that the source-drain voltage of the fifth transistor periodically exceeds the rated voltage range, which is beneficial to improving the performance of the gate voltage bootstrap switching circuit.

[0021] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0022] Figure 1 A schematic diagram of the circuit structure of a switch circuit provided in an embodiment of the present disclosure.

[0023] refer to Figure 1In one aspect, an embodiment of the present disclosure provides a switch circuit, including: a switch transistor N0, wherein the drain of the switch transistor N0 serves as an input terminal of the switch circuit, and the source of the switch transistor N0 serves as an output terminal of the switch circuit; a switch control circuit, wherein the switch control circuit includes: a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor P6, a capacitor C, and a seventh transistor P7, wherein the source of the first transistor N1 is connected to the ground VSS, the gate of the first transistor N1 receives a first clock signal clksb1, and the gate of the second transistor N1 receives a first clock signal clksb2. The source of the transistor N2 is connected to the drain of the first transistor N1, the drain of the second transistor N2 is connected to the source of the switch transistor N0, the gate of the second transistor N2 is connected to the gate of the sixth transistor P6, the source of the sixth transistor P6 is connected to the power supply voltage VDD, the gate of the sixth transistor P6 is connected to the gate of the switch transistor N0, the drain of the sixth transistor P6 is connected to the first end of the capacitor C, the second end of the capacitor C is connected to the drain of the first transistor N1, the source of the seventh transistor P7 is connected to the gate of the sixth transistor P6, and the drain of the seventh transistor P7 is connected to the first end of the capacitor C. , the gate of the seventh transistor P7 is used to receive the second clock signal clksb2, the source of the third transistor N3 is connected to the drain of the first transistor N1, the drain of the third transistor N3 is connected to the gate of the seventh transistor P7, the gate of the third transistor N3 is connected to the gate of the switching transistor N0, the source of the fourth transistor N4 is connected to the ground VSS, the gate of the fourth transistor N4 is used to receive the third clock signal clksb3, the drain of the fourth transistor N4 is connected to the source of the fifth transistor N5, the drain of the fifth transistor N5 is connected to the gate of the sixth transistor P6, and the fifth transistor N 5 has a gate connected to the power supply voltage VDD; a first inverter, an input end of the first inverter 110 receives the initial clock signal clks, and an output end of the first inverter 110 outputs a first clock signal clksb1 to the gate of the first transistor N1; a second inverter 120, an input end of the second inverter 120 receives the initial clock signal clks, and an output end of the second inverter 120 outputs a third clock signal clksb3 to the gate of the fourth transistor N4; wherein, the transmission delay when the first inverter 110 inputs a low level is less than the transmission delay when the second inverter 120 inputs a low level.

[0024] According to the embodiment of the present disclosure, when the initial clock signal clks changes from a high level to a low level, the first transistor N1 is turned on in advance to discharge the second end of the capacitor C, thereby causing the voltage at the first end of the capacitor C to drop, thereby alleviating the phenomenon that the source-drain voltage of the fifth transistor N5 periodically exceeds the rated voltage range, thereby facilitating improving the performance of the gate voltage bootstrap switch circuit.

[0025] The voltage level of the initial clock signal clks jumps between a high level and a low level. The input terminal IN of the switch circuit is used to input a signal, and the output terminal OUT of the switch circuit is used to output a signal, which can be a sensitive signal. When the source S and the drain D of the switch transistor N0 are connected, the switch circuit is considered to be turned on, and when the source S and the drain D of the switch transistor N0 are disconnected, the switch circuit is considered to be turned off. When the switch circuit is in the on state, the voltage of the node P40 changes synchronously with the change of the voltage input to the drain D of the switch transistor N0, and the voltage of the node P40 is the gate voltage of the switch transistor N0.

[0026] The first clock signal clksb1 , the second clock signal clksb2 , and the third clock signal clksb3 are all inverted signals of the initial clock signal clks.

[0027] In some embodiments, the sixth transistor P6 and the seventh transistor P7 are both PMOS (P-channel metal oxide semiconductor) tubes, and the first transistor N1, the second transistor N2, the third transistor N3, the fourth transistor N4 and the fifth transistor N5 are all NMOS (N-channel metal oxide semiconductor) tubes.

[0028] When the initial clock signal clks is at a low level, the second clock signal clksb2 is at a high level, the seventh transistor P7 is turned off, the first clock signal clksb1 is at a high level, the first transistor N1 is turned on, the third clock signal clksb3 is at a high level, the fourth transistor N4 is turned on, the fifth transistor N5 is turned on, the ground voltage connected to the source of the fourth transistor N4 makes the node P40 at a low level, the gate of the switch transistor N0, the gate of the second transistor N2 and the gate of the third transistor N3 are all at a low level, so the switch transistor N0, the second transistor N2 and the third transistor N3 are all turned off, the gate of the sixth transistor P6 receives a low level, the sixth transistor P6 is turned on, the ground voltage connected to the source of the first transistor N1 makes the voltage of the node P36 0, and the power supply voltage VDD connected to the source of the sixth transistor P6 makes the voltage of the node P43 vdd. At this time, the voltage difference across the capacitor C is vdd, and the switch circuit is in the off state.

[0029] When the clock signal is at a high level, the second clock signal clksb2 is at a low level, the seventh transistor P7 is turned on, the sixth transistor P6 is turned off, the voltage of the node P43 passes through the seventh transistor P7 to make the voltage of the node P40 equal to the voltage of the node P43, the gate of the switch transistor N0, the gate of the second transistor N2, and the gate of the third transistor N3 are all at a high level, the switch transistor N0, the second transistor N2, and the third transistor N3 are all turned on, the first clock signal clksb1 is at a low level, the first transistor N1 is turned off, the third clock signal clksb3 is at a low level, the fourth transistor N4 is turned off, the voltage of the node P36 is equal to the voltage of the drain of the switch transistor N0, and the voltage of the node P43 is equal to the voltage of the node P36 plus vdd. The voltage of the gate of the switch transistor N0 is the voltage of the node P36 plus vdd, and the voltage difference between the gate voltage and the drain of the switch transistor N0 is always vdd, which can ensure that the switch transistor N0 has a good conduction performance.

[0030] Normally, the gate-drain voltage and source-drain voltage of a transistor are required not to exceed 1.15 times the power supply voltage, that is, they should not exceed the rated voltage range. If the source-drain voltage of the transistor periodically exceeds the rated voltage range, the reliability of the device cannot be guaranteed under long-term use.

[0031] The following is an explanation of the reason why the source-drain voltage of the fifth transistor N5 in the switch circuit may periodically exceed the rated voltage. Usually, the voltage of the signal input to the input terminal IN of the switch circuit is also relatively large. For example, it can be assumed that the voltage input to the input terminal IN of the switch circuit is vdd. When the clock signal clks is high and stable, the voltages of the nodes P40 and P44 are both 2vdd. When the clock signal Clks changes from a high level to a low level, the fourth transistor N4 is turned on to cause the voltage of the node P44 to drop. For the fifth transistor N5, the gate voltage of the fifth transistor N5 is vdd. Therefore, when the drain voltage of the fifth transistor N5 drops to vdd-vth, the voltage at the node P40 will drop more rapidly through the conduction of the fifth transistor N5. In other words, the voltage of the node P44 must drop to vdd-vth before the voltage at the node P40 can drop more rapidly. Although, before the source voltage of the fifth transistor N5 drops to vdd-vth, the first transistor N1 also discharges the node P36 to reduce the voltage of the node P43, but because the channel width-to-length ratio of the first transistor N1 is limited, the first transistor N1 cannot quickly discharge the capacitor C, resulting in a slow voltage reduction at the node P43. This may cause the source-drain voltage of the fifth transistor N5 to exceed the rated voltage when the source voltage of the fifth transistor N5 drops to vdd-vth. Even if the fifth transistor N5 is turned on to reduce the voltage of the node P43, the source-drain voltage of the fifth transistor N5 still exceeds the rated voltage within a certain period of time, affecting the reliability of the circuit.

[0032] In the technical solution provided by the embodiment of the present application, the first clock signal clksb1 is used to control the on or off of the first transistor N1, and the third clock signal clksb3 is used to control the on and off of the fourth transistor N4. Since the first clock signal clksb1 is the clock signal output by the initial clock signal clks through the first inverter 110, and the third clock signal clksb3 is the clock signal output by the initial clock signal clks through the second inverter 120, and since the transmission delay when the first inverter 110 inputs a low level is less than the transmission delay when the second inverter 120 inputs a low level, when the initial clock signal clks changes from a high level to a low level, the gate of the first transistor N1 receives a high level earlier than the gate of the fourth transistor N4, so that the first transistor N1 is turned on earlier than the fourth transistor N4, and then the node P36 is discharged, so that the voltage of the node P43 drops in advance, so that it is helpful to alleviate the phenomenon that the source-drain voltage of the fifth transistor N5 periodically exceeds the rated voltage range, and thus it is helpful to improve the reliability of the switching circuit and improve the performance of the switching circuit.

[0033] In some embodiments, the first inverter 110 includes an eighth transistor P8 and a ninth transistor N8, the eighth transistor P8 is a PMOS tube, the second inverter 120 includes a tenth transistor P10 and an eleventh transistor N11, the tenth transistor P10 is a PMOS tube, and the channel width-to-length ratio of the eighth transistor P8 is greater than the channel width-to-length ratio of the tenth transistor P10. In this way, the transmission delay when the first inverter 110 inputs a low level can be made shorter than the transmission delay when the second inverter 120 inputs a low level.

[0034] In some embodiments, the ratio of the channel width-to-length ratio of the eighth transistor P8 to the channel width-to-length ratio of the tenth transistor P10 is 1.8-2.2, for example, 1.8, 1.9, 2 or 2.1.

[0035] In some embodiments, the channel width-to-length ratio of the eighth transistor P8 is 3-4, for example, 3, 3.5, 3.8 or 4, and the channel width-to-length ratio of the tenth transistor P10 is 1-2, for example, 1.2, 1.5, 1.7 or 2.

[0036] In some embodiments, the switch circuit further includes a third inverter 130 , an input terminal of the third inverter 130 receives the initial clock signal clks, and an output terminal of the third inverter 130 outputs the second clock signal clksb2 to the gate of the seventh transistor P7 .

[0037] In some embodiments, the third inverter 130 includes a twelfth transistor P12 and a thirteenth transistor N13 , the twelfth transistor P12 is a PMOS transistor, and the thirteenth transistor N13 is an NMOS transistor.

[0038] In some embodiments, the twelfth transistor P12 is the same as the tenth transistor P10 , and the thirteenth transistor N13 is the same as the eleventh transistor N11 .

[0039] In some embodiments, the channel width-to-length ratio of the PMOS transistor of the third inverter 130 is equal to the channel width-to-length ratio of the PMOS transistor of the second inverter 120. That is, the channel width-to-length ratio of the twelfth transistor P12 is the same as the channel width-to-length ratio of the tenth transistor P10.

[0040] In some embodiments, the channel width-to-length ratio of the NMOS transistor of the third inverter 130 is equal to the channel width-to-length ratio of the NMOS transistor of the second inverter 120. That is, the channel width-to-length ratio of the thirteenth transistor N13 is the same as the channel width-to-length ratio of the eleventh transistor N11.

[0041] In some embodiments, the initial clock signal clks is a square wave clock signal.

[0042] In some embodiments, the switch control circuit further includes a resistor (not shown), and the gate of the fifth transistor N5 is connected to the power supply voltage VDD through the resistor.

[0043] In the switch circuit provided by the above embodiment, the first clock signal clksb1 is used to control the on or off of the first transistor N1, and the third clock signal clksb3 is used to control the on and off of the fourth transistor N4. Since the first clock signal clksb1 is a clock signal output by the initial clock signal clks through the first inverter 110, and the third clock signal clksb3 is a clock signal output by the initial clock signal clks through the second inverter 120, and since the transmission delay when the first inverter 110 inputs a low level is less than the transmission delay when the second inverter 120 inputs a low level, when the initial clock signal clks changes from a high level to a low level, the gate of the first transistor N1 receives a high level in advance compared to the gate of the fourth transistor N4, so that the first transistor N1 is turned on earlier than the fourth transistor N4, and then the node P36 is discharged, and then the voltage of the node P43 drops in advance. In this way, it is helpful to alleviate the phenomenon that the source-drain voltage of the fifth transistor N5 periodically exceeds the rated voltage range, and thus it is helpful to improve the reliability of the switch circuit and improve the performance of the switch circuit.

[0044] Another aspect of the present disclosure is to provide an electronic device, comprising at least a switch circuit as described in any one of the above embodiments. It should be noted that the same or corresponding parts as the above embodiments can refer to the detailed description of the above embodiments, and will not be repeated below.

[0045] It can be understood by those skilled in the art that the above-mentioned embodiments are specific embodiments of the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A switching circuit, characterized in that: include: A switch transistor, wherein the drain of the switch transistor serves as the input end of the switch circuit, and the source of the switch transistor serves as the output end of the switch circuit; A switch control circuit, the switch control circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a capacitor and a seventh transistor, wherein the source of the first transistor is connected to ground, the gate of the first transistor receives a first clock signal, the source of the second transistor is connected to the drain of the first transistor, the drain of the second transistor is connected to the source of the switch transistor, the gate of the second transistor is connected to the gate of the sixth transistor, the source of the sixth transistor is connected to a power supply voltage, the gate of the sixth transistor is connected to the gate of the switch transistor, the drain of the sixth transistor is connected to the first end of the capacitor, and the second end of the capacitor is connected to the a drain of the first transistor, a source of the seventh transistor connected to the gate of the sixth transistor, a drain of the seventh transistor connected to the first end of the capacitor, a gate of the seventh transistor for receiving a second clock signal, a source of the third transistor connected to the drain of the first transistor, a drain of the third transistor connected to the gate of the seventh transistor, a gate of the third transistor connected to the gate of the switch transistor, a source of the fourth transistor connected to ground, a gate of the fourth transistor for receiving a third clock signal, a drain of the fourth transistor connected to the source of the fifth transistor, a drain of the fifth transistor connected to the gate of the sixth transistor, and a gate of the fifth transistor connected to a power supply voltage; a first inverter, wherein an input terminal of the first inverter receives an initial clock signal, and an output terminal of the first inverter outputs the first clock signal to a gate of the first transistor; a second inverter, wherein an input terminal of the second inverter receives the initial clock signal, and an output terminal of the second inverter outputs the third clock signal to the gate of the fourth transistor; The transmission delay when the first inverter inputs a low level is smaller than the transmission delay when the second inverter inputs a low level.

2. The switch circuit according to claim 1, characterized in that: The sixth transistor and the seventh transistor are both PMOS transistors, and the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all NMOS transistors.

3. The switch circuit according to claim 1, characterized in that: The first inverter includes an eighth transistor and a ninth transistor, the eighth transistor is a PMOS transistor, the second inverter includes a tenth transistor and an eleventh transistor, the tenth transistor is a PMOS transistor, and a channel width-to-length ratio of the eighth transistor is greater than a channel width-to-length ratio of the tenth transistor.

4. The switch circuit according to claim 3, characterized in that: A ratio of a channel width-to-length ratio of the eighth transistor to a channel width-to-length ratio of the tenth transistor is 1.8 to 2.

2.

5. The switch circuit according to claim 3 or 4, characterized in that: The channel width-to-length ratio of the eighth transistor is 3-4, and the channel width-to-length ratio of the tenth transistor is 1-2.

6. The switch circuit according to claim 1, characterized in that: The switch circuit further includes a third inverter, an input terminal of the third inverter receives the initial clock signal, and an output terminal of the third inverter outputs the second clock signal to the gate of the seventh transistor.

7. The switch circuit according to claim 6, characterized in that: The channel width-to-length ratio of the PMOS tube of the third inverter is equal to the channel width-to-length ratio of the PMOS tube of the second inverter.

8. The switch circuit according to claim 1, characterized in that: The initial clock signal is a square wave clock signal.

9. The switch circuit according to claim 1, characterized in that: The switch control circuit further includes a resistor, and the gate of the fifth transistor is connected to a power supply voltage through the resistor.

10. An electronic device, characterized in that: At least comprising the switching circuit according to any one of claims 1 to 9.

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