Low-phase noise signal generation device and test system
By using a phase-locked loop to drive a direct digital frequency synthesizer in the signal generation device, combined with a filter and a voltage-controlled oscillator, the problem of phase-locked loop noise affecting the target signal is solved, low phase noise and arbitrary frequency output are achieved, and the output of low phase noise is improved. Accuracy of chip testing.
Patent Information
- Application Number
- CN202420468285.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-11
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-03-11
AI Technical Summary
In the prior art, the phase-locked loop's own noise affects the phase noise index of the target signal, resulting in limited chip testing accuracy.
Design a low-phase noise signal generator, and drive a direct digital frequency synthesizer using a phase-locked loop, which eliminates the phase-locked loop's own noise and reduces the phase noise of the target signal through the combination of a phase-locked loop, a filter and a voltage-controlled oscillator. .
It realizes reducing the phase noise of the target signal, meeting the needs of phase noise indicators, and supporting any frequency output, improving the accuracy of chip testing.
Smart Images
Figure CN222234840U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing, and in particular to a low phase noise signal generating device and a testing system. Background Art
[0002] Chip testing refers to using a test machine to control the signal generating device to output a target signal to detect various parameter indicators of the device under test, eliminate defective products and control the factory quality of semiconductor devices.
[0003] In the prior art, a direct digital frequency synthesizer is used to drive a phase-locked loop to output a clock signal. Although this reduces the impact of the phase noise of the reference clock signal on the target signal, the phase-locked loop itself has inherent noise due to its manufacturing process. Therefore, the phase noise index of the target signal output by it is restricted by the noise level of the phase-locked loop itself, which affects the test accuracy. Utility Model Content
[0004] Based on this, it is necessary to provide a low phase noise signal generating device and a testing system to address the above technical problems.
[0005] In a first aspect, an embodiment of the present utility model provides a low phase noise signal generating device, the device comprising:
[0006] A phase-locked loop, used for receiving a reference clock signal from a test machine and an external first feedback clock signal, and outputting a first signal after comparing the reference clock signal with the first feedback clock signal in frequency and phase;
[0007] A first filter, connected to the phase-locked loop, configured to filter the first signal and output a second signal;
[0008] a voltage-controlled oscillator, connected to the first filter and the phase-locked loop, and configured to output a first feedback clock signal and output a sampling clock signal according to the second signal;
[0009] A direct digital frequency synthesizer is connected to the voltage-controlled oscillator and is used to output a target signal according to the sampling clock signal.
[0010] In one embodiment, the phase-locked loop comprises:
[0011] A frequency and phase detector, used to detect the frequency difference and phase difference between the reference clock signal and the second feedback clock signal, and output a detection signal;
[0012] A charge pump connected to the frequency and phase detector, and configured to output a first signal according to the detection signal;
[0013] The frequency divider is connected to the voltage-controlled oscillator and the phase frequency detector, and is used for dividing the frequency of the first feedback clock signal to output the second feedback clock signal.
[0014] In one embodiment, the first filter is a loop filter.
[0015] In one embodiment, the first filter is a third-order loop filter, including a first filter circuit, a second filter circuit, and a third filter circuit connected in sequence.
[0016] In one embodiment, the first filtering circuit includes a capacitor C1, the second filtering circuit includes a capacitor C2 and a resistor R1, and the third filtering circuit includes a capacitor C3 and a resistor R2; the capacitor C1 is connected between the output end of the phase-locked loop and a common ground, the capacitor C2 and the resistor R1 are connected in series between the output end of the phase-locked loop and the common ground, the resistor R2 is connected in series at the output end of the phase-locked loop, and the capacitor C3 is connected between the output end of the resistor R2 and the common ground.
[0017] In one embodiment, the voltage controlled oscillator is external to the phase locked loop.
[0018] In one embodiment, the device further comprises:
[0019] a frequency multiplier connected between the voltage-controlled oscillator and the direct digital frequency synthesizer, for multiplying the frequency of the sampling clock signal to a target frequency and outputting a third signal;
[0020] The direct digital frequency synthesizer outputs a target signal according to the third signal.
[0021] In one embodiment, the device further comprises:
[0022] A second filter, connected between the frequency multiplier and the direct digital frequency synthesizer, for filtering the third signal and outputting a fourth signal;
[0023] The direct digital frequency synthesizer outputs a target signal according to the fourth signal.
[0024] In one embodiment, the voltage controlled oscillator is a narrow-band frequency controlled oven controlled crystal oscillator.
[0025] In a second aspect, an embodiment of the utility model provides a test system, comprising a test machine and a low phase noise signal generating device as described in the first aspect, wherein the test machine is used to output a reference clock signal.
[0026] Compared with the prior art, the technical solution has the following technical effects: using a phase-locked loop to drive a direct digital frequency synthesizer to output the target signal can eliminate the constraints of the phase-locked loop's own noise level and reduce the phase noise of the target signal, which can meet both the requirements of phase noise indicators and the requirements of arbitrary frequency output, thereby improving the accuracy of chip testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 This is a schematic diagram of the structure of a signal generating device in one embodiment of the utility model;
[0028] Figure 2 This is a schematic diagram of the structure of a phase-locked loop in one embodiment of the utility model;
[0029] Figure 3 This is a connection diagram of a phase negative feedback loop in one embodiment of the utility model;
[0030] Figure 4 This is a circuit diagram of a first filter in an embodiment of the utility model;
[0031] Figure 5 It is a schematic diagram of simulation of phase noise of each clock signal in an embodiment of the utility model;
[0032] Figure 6 It is a schematic diagram of the simulation of the phase noise of the voltage-controlled oscillator external to the phase-locked loop;
[0033] Figure 7 This is a simulation diagram of the phase noise of the voltage-controlled oscillator integrated inside the phase-locked loop;
[0034] Figure 8 This is a structural schematic diagram of a signal generating device in another embodiment of the utility model;
[0035] Fig. 9 This is a structural schematic diagram of a signal generating device in another embodiment of the utility model;
[0036] Fig.10 It is a structural schematic diagram of a test system in one embodiment of the utility model.
[0037] Among them, 10, test machine; 20, signal generating device; 210, phase-locked loop; 220, first filter; 230, voltage-controlled oscillator; 240, frequency multiplier; 250, second filter; 260, direct digital frequency synthesizer; 211, frequency detector and phase detector; 212, charge pump; 213, divider; 221, first filter circuit; 222, second filter circuit; 223, third filter circuit. DETAILED DESCRIPTION
[0038] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0039] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.
[0040] Reference to "embodiments" in this application means that the specific features, structures, or characteristics described in conjunction with the embodiments may be included in multiple embodiments of the application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.
[0041] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.
[0042] like Figure 1 As shown, an embodiment of the present application proposes a low phase noise signal generating device, including a phase-locked loop 210, for receiving a reference clock signal from a test machine 10 and an external first feedback clock signal, and outputting a first signal after comparing the reference clock signal and the first feedback clock signal in frequency and phase; a first filter 220, connected to the phase-locked loop 210, for filtering the first signal and outputting a second signal; a voltage-controlled oscillator 230, connected to the first filter 220 and the phase-locked loop 210, for outputting a first feedback clock signal and outputting a sampling clock signal according to the second signal; and a direct digital frequency synthesizer 260, connected to the voltage-controlled oscillator 230, for outputting a target signal according to the sampling clock signal.
[0043] In this embodiment, the target signal is generated by driving the direct digital frequency synthesizer 260 using the phase-locked loop 210, which can eliminate the limitation of the noise level of the phase-locked loop itself and reduce the phase noise of the target signal, thereby meeting both the phase noise index requirements and the requirements of arbitrary frequency output.
[0044] The frequency of the target signal output by the direct digital frequency synthesizer 260 is determined by the internal frequency control word register, so any frequency output within a certain frequency range can be achieved.
[0045] Furthermore, the voltage controlled oscillator 230 is external to the phase-locked loop 210. Since the sampling clock signal is the sampling clock input of the direct digital frequency synthesizer 260, based on the inherent characteristics of the direct digital frequency synthesizer 260, the phase noise index will be more outstanding when outputting target signals of other frequencies.
[0046] like Figure 2 As shown, the phase-locked loop 210 includes: a frequency detector 211, which is used to detect the frequency difference and phase difference between the reference clock signal and the second feedback clock signal, and output a detection signal; a charge pump 212, which is connected to the frequency detector 211, and is used to output a first signal according to the detection signal; a frequency divider 213, which is connected to the voltage-controlled oscillator 230 and the frequency detector 211, and is used to divide the first feedback clock signal and output the second feedback clock signal.
[0047] The phase-locked loop 210 integrates a phase-frequency detector 211, a charge pump 212 and a frequency divider 213. The phase-frequency detector 211 compares the frequency and phase of the reference clock signal and the second feedback clock signal, and drives the charge pump 212 to output a first signal related to the phase difference between the two. The first signal is a current signal, which is an input signal of the subsequent first filter 220. The second feedback clock signal is obtained by dividing the first feedback clock signal of the external voltage-controlled oscillator 230 by the frequency divider 213.
[0048] like Figure 3 As shown, the phase frequency detector 211, the charge pump 212, the first filter 220, the voltage controlled oscillator 230 and the frequency divider 213 form a phase negative feedback loop, which realizes the phase synchronization function of the external first feedback clock signal and the reference clock signal.
[0049] The first filter 220 is a loop filter. The loop filter converts the first signal output by the charge pump 212 into a second signal, and the second signal is a voltage signal after filtering out high-frequency noise, that is, the current signal is converted into a voltage signal and the high-frequency noise is filtered out as a tuning voltage input of the subsequent voltage-controlled oscillator 230. The loop filter is composed of a cascade of resistors and capacitors, and the bandwidth of the loop filter is determined by the resistor and capacitor parameters that constitute it.
[0050] In an exemplary embodiment, the first filter 220 is a third-order loop filter. Figure 4 As shown, the third-order loop filter includes a first filter circuit 221, a second filter circuit 222, and a third filter circuit 223 connected in sequence. The first filter circuit 221 includes a capacitor C1, the second filter circuit 222 includes a capacitor C2 and a resistor R1, and the third filter circuit 223 includes a capacitor C3 and a resistor R2; the capacitor C1 is connected between the output end of the phase-locked loop 210 and the common ground, the capacitor C2 and the resistor R1 are connected in series between the output end of the phase-locked loop 210 and the common ground, the resistor R2 is connected in series at the output end of the phase-locked loop 210, and the capacitor C3 is connected between the output end of the resistor R2 and the common ground.
[0051] The external voltage-controlled oscillator 230 is a narrow-band frequency constant temperature crystal oscillator, which outputs a first feedback clock signal to the phase negative feedback loop; in addition, it also outputs a sampling clock signal of a certain frequency under the action of a second signal as an input signal for the subsequent stage.
[0052] The phase noise of the above phase negative feedback loop is simulated to analyze the contribution of each component to the phase noise of the target signal. The simulation results are as follows: Figure 5 As shown, the horizontal axis Frequency represents the frequency, the vertical axis PhaseNoise represents the phase noise, the Total curve represents the phase noise of the sampling clock signal output by the phase negative feedback loop, the Loop Filter curve represents the phase noise of the first filter itself, the Ref curve represents the phase noise of the reference clock signal, the Chip curve represents the phase noise of the phase-locked loop itself, and the VCO curve represents the phase noise of the first feedback clock signal.
[0053] The analysis curve shows that the phase noise (corresponding to Figure 5The Total curve in the figure is mainly composed of the phase noise of the reference clock signal (corresponding to Figure 5 The phase noise of the target signal output by the signal generating device 20 outside the bandwidth of the first filter 220 is contributed by the voltage controlled oscillator 230 (corresponding to Figure 5 Based on this characteristic, by adjusting the resistance and capacitance parameters of the first filter 220 to make its bandwidth only a few Hz, the phase noise contributed by the reference clock signal and the first signal is filtered out by the first filter 220, and the phase noise of the target signal is determined by the phase noise index of the sampling clock signal. The above architecture solves the problem of deterioration of the phase noise index after synchronization.
[0054] Figure 6 This is the phase noise simulation result of the voltage-controlled oscillator outside the phase-locked loop. Figure 7 This is the phase noise simulation result of the voltage-controlled oscillator integrated inside the phase-locked loop. By analyzing the phase noise of the voltage-controlled oscillator outside the phase-locked loop and the voltage-controlled oscillator integrated inside the phase-locked loop, it can be seen that the phase noise performance of the voltage-controlled oscillator outside the phase-locked loop has obvious advantages at the same frequency.
[0055] In one embodiment, if Figure 8 As shown, the signal generating device 20 further includes: a frequency multiplier 240 connected between the voltage controlled oscillator 230 and the direct digital frequency synthesizer 260, for multiplying the frequency of the sampling clock signal to a target frequency and outputting a third signal.
[0056] The frequency multiplier 240 multiplies the frequency of the sampling clock signal to a frequency that meets the requirements of the direct digital frequency synthesizer 260 , and the frequency multiplier 240 outputs a third signal as an input of the subsequent direct digital frequency synthesizer 260 .
[0057] In one embodiment, if Fig. 9 As shown, the signal generating device 20 further includes: a second filter 250, connected between the frequency multiplier 240 and the direct digital frequency synthesizer 260, for filtering the third signal and outputting a fourth signal.
[0058] The second filter 250 is a bandpass filter, which filters the third signal to remove the fundamental frequency and unnecessary harmonic components in the third signal. The output of the bandpass filter is connected to the input end of the direct digital frequency synthesizer 260 .
[0059] The fourth signal is the sampling clock input of the direct digital frequency synthesizer 260. Under the action of the fourth signal, the direct digital frequency synthesizer 260 can realize the output of any frequency signal within a certain frequency range by configuring the frequency control word register inside the chip in actual application. The phase noise index of the fourth signal directly affects the phase noise index of its target signal. From a mathematical perspective, the phase noise values of the two at the same frequency offset are 20log(F clk / F out ) correlation improvement (an inherent characteristic of direct digital frequency synthesizers, where F clk is the frequency of the fourth signal, F out is the frequency of the target signal, and log is the logarithm), that is, the better the phase noise index of the fourth signal is, the better the phase noise index of the target signal is.
[0060] Since the frequency conversion time of the direct digital frequency synthesizer 260 is determined by the communication configuration time, its speed is much better than the locking speed of the phase-locked loop 210, and thus it is more suitable for the application scenario of the test machine.
[0061] like Fig.10 As shown, an embodiment of the present application proposes a test system, including a test machine 10 and the low phase noise signal generating device 20 in the above embodiment, and the test machine 10 is used to output a reference clock signal.
[0062] Since the test system includes the signal generating device 20 in the above embodiment, it can solve the same technical problem and achieve the same technical effect, which will not be described in detail here.
[0063] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0064] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A low phase noise signal generating device, characterized in that: The device comprises: A phase-locked loop, used for receiving a reference clock signal from a test machine and an external first feedback clock signal, and outputting a first signal after comparing the reference clock signal with the first feedback clock signal in frequency and phase; A first filter, connected to the phase-locked loop, configured to filter the first signal and output a second signal; a voltage-controlled oscillator, connected to the first filter and the phase-locked loop, and configured to output a first feedback clock signal and output a sampling clock signal according to the second signal; A direct digital frequency synthesizer is connected to the voltage-controlled oscillator and is used to output a target signal according to the sampling clock signal.
2. The low phase noise signal generating device according to claim 1, characterized in that: The phase-locked loop comprises: A frequency and phase detector, used to detect the frequency difference and phase difference between the reference clock signal and the second feedback clock signal, and output a detection signal; A charge pump connected to the frequency and phase detector, and configured to output a first signal according to the detection signal; The frequency divider is connected to the voltage-controlled oscillator and the phase frequency detector, and is used for dividing the frequency of the first feedback clock signal to output the second feedback clock signal.
3. The low phase noise signal generating device according to claim 1, characterized in that: The first filter is a loop filter.
4. The low phase noise signal generating device according to claim 3, characterized in that: The first filter is a third-order loop filter, including a first filter circuit, a second filter circuit and a third filter circuit which are connected in sequence.
5. The low phase noise signal generating device according to claim 4, characterized in that: The first filter circuit includes a capacitor C1, the second filter circuit includes a capacitor C2 and a resistor R1, and the third filter circuit includes a capacitor C3 and a resistor R2; the capacitor C1 is connected between the output end of the phase-locked loop and a common ground, the capacitor C2 and the resistor R1 are connected in series between the output end of the phase-locked loop and the common ground, the resistor R2 is connected in series at the output end of the phase-locked loop, and the capacitor C3 is connected between the output end of the resistor R2 and the common ground.
6. The low phase noise signal generating device according to claim 1, characterized in that: The voltage controlled oscillator is external to the phase locked loop.
7. The low phase noise signal generating device according to claim 1, characterized in that: The device also includes: a frequency multiplier connected between the voltage-controlled oscillator and the direct digital frequency synthesizer, for multiplying the frequency of the sampling clock signal to a target frequency and outputting a third signal; The direct digital frequency synthesizer outputs a target signal according to the third signal.
8. The low phase noise signal generating device according to claim 7, characterized in that: The device also includes: A second filter, connected between the frequency multiplier and the direct digital frequency synthesizer, for filtering the third signal and outputting a fourth signal; The direct digital frequency synthesizer outputs a target signal according to the fourth signal.
9. The low phase noise signal generating device according to claim 1, characterized in that: The voltage-controlled oscillator is a narrow-band frequency constant-temperature crystal oscillator.
10. A testing system, characterized in that: The invention comprises a test machine and a low phase noise signal generating device as claimed in any one of claims 1 to 9, wherein the test machine is used to output a reference clock signal.