Silicon carbide wafer annealing device
By designing a reusable silicon carbide wafer annealing device, the complex structure and high cost of existing devices are solved by using threaded connections and hollow annular structures, efficient wafer separation and pick-up, and improved production efficiency and finished product qualification Rate.
Patent Information
- Application Number
- CN202421027509.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2034-05-13
AI Technical Summary
The existing silicon carbide wafer annealing devices have complex structures, low reuse rate and high cost. The wafers are not easy to separate and take after annealing, resulting in a decrease in the pass rate of the finished product.
Design a silicon carbide wafer annealing device including a support cylinder, a bottom ring, an intermediate ring and a crucible cover, which can be reused by threaded connection, and set up multiple hollow annular structures and bosses to facilitate separation and pick-up of wafers and simplify the structure. Reduce costs.
The reuse rate of the annealing device is improved, the operation process is simplified, the cost is reduced, and the wafer separation and acquisition efficiency is improved, and the damage rate of the finished product is reduced.
Smart Images
Figure CN222251130U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of wafer processing, and in particular relates to a silicon carbide wafer annealing device. Background Art
[0002] Silicon carbide wafers are sheet-shaped objects made of silicon carbide powder. They are key materials for producing semiconductor products such as integrated circuits, discrete devices, sensors, and are a fundamental part of the semiconductor industry chain. In the production process of silicon carbide wafers, the annealing process is a very important step, which directly affects the production efficiency and manufacturing quality of the wafers. With the increasing manufacturing requirements of silicon carbide wafers, the shortcomings of the annealing device of silicon carbide wafers in actual work are also urgently needed to be improved.
[0003] In the prior art, an annealing furnace is usually used to anneal silicon carbide wafers. Specifically, first, the silicon carbide wafers are stacked together and placed in a crucible, and then the crucible is placed vertically in the annealing furnace to anneal the wafers so that the silicon carbide wafers are parallel or approximately parallel to the horizontal plane. However, when the wafer size increases to 6 to 8 inches, the weight of the wafer increases and the contact area between the wafers increases due to the increase in the wafer size. Therefore, when a large number of wafers are stacked together, it will cause the wafers to be difficult to separate after annealing is completed due to oxidation, which will cause cracking and breaking, thereby reducing the qualified rate of finished products. In addition, the annealing device has a complex structure, is not easy to operate, has a low reuse rate, and adds additional costs.
[0004] Therefore, it is urgent to design a silicon carbide wafer annealing device to solve the above-mentioned problems of the existing annealing device having a complex structure, low reuse rate, high cost, and difficulty in separating and removing the wafers after annealing. Utility Model Content
[0005] In order to solve the technical problems mentioned in the background technology that the existing annealing device has a complex structure, low reuse rate, high cost, and the wafers are difficult to separate and take out after annealing, a silicon carbide wafer annealing device is provided to solve the above problems.
[0006] To achieve the above purpose, the specific technical scheme of the silicon carbide wafer annealing device of the utility model is as follows:
[0007] A silicon carbide wafer annealing device comprises a support tube, a bottom ring is arranged on the support tube, a plurality of intermediate rings are stacked in sequence on the bottom ring, a crucible cover is arranged at one end of the plurality of intermediate rings away from the bottom ring, the bottom ring and the intermediate rings are both hollow annular structures, a plurality of bosses are arranged on the side of the hollow annular structure away from the support tube, and wafers are overlapped and arranged on the plurality of bosses.
[0008] Furthermore, the support tube, the bottom ring, the plurality of intermediate rings and the crucible cover are threadedly connected.
[0009] Furthermore, the bottom ring includes an annular first step and a second step, the first step and the second step are in a Z-shaped structure, the Z-shaped structure is overlapped on the support tube, the side wall of the second step is provided with a first internal thread, the outer periphery of the support tube is provided with a first external thread, and the first internal thread is screwed with the first external thread.
[0010] Furthermore, a plurality of bosses are arranged at intervals on the first step.
[0011] Furthermore, the middle ring includes annular third and fourth steps, the third and fourth steps are in a Z-shaped structure, the Z-shaped structure is overlapped on the bottom ring, the side wall of the fourth step is provided with a second internal thread, the outer periphery of the first step is provided with a second external thread, and the second internal thread is screwed to the second external thread.
[0012] Furthermore, an escape space is provided on the third step for escaping the wafer.
[0013] Furthermore, a plurality of bosses are arranged at intervals on the second step.
[0014] Furthermore, a plurality of bosses are recessed to form a placement portion, and the wafer is placed on the placement portion.
[0015] Furthermore, the crucible cover includes a cover body, on which a fifth step and a sixth step are arranged, the fifth step and the sixth step are L-shaped structures, the fifth step is overlapped on the middle ring, the side wall of the sixth step is arranged with a third internal thread, the outer periphery of the third step is arranged with a third external thread, and the third internal thread is screwed with the third external thread.
[0016] Furthermore, a thread groove is provided on the cover body, and a hanging ring or a handle is screwed into the thread groove.
[0017] The silicon carbide wafer annealing device of the utility model has the following advantages:
[0018] A bottom ring is arranged on the support tube, a plurality of intermediate rings are stacked on the bottom ring in sequence, a crucible cover is arranged on one end of the plurality of intermediate rings away from the bottom ring, the bottom ring and the intermediate ring are both hollow ring structures, a plurality of bosses are arranged on the side of the hollow ring structure away from the support tube, and wafers are overlapped and arranged on the plurality of bosses. The support tube, the bottom ring, the intermediate ring and the crucible cover can be reused to improve the utilization rate. A plurality of intermediate rings are arranged to facilitate separation of wafers, and a plurality of bosses are arranged to facilitate taking wafers. The structure is simple and the cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a schematic diagram of the structure of the silicon carbide wafer annealing device of the utility model;
[0020] Figure 2 This is a schematic cross-sectional structure diagram of a silicon carbide wafer annealing device of the utility model;
[0021] Figure 3 for Figure 2 A is a schematic diagram of the enlarged structure of the middle part;
[0022] Figure 4 for Figure 2 Schematic diagram of the enlarged structure of B;
[0023] Figure 5 This is a schematic diagram of the structure of the intermediate ring of the utility model;
[0024] Figure 6 It is a schematic diagram of the cross-sectional structure of the intermediate ring of the utility model;
[0025] Figure 7 It is a structural schematic diagram of the bottom ring of the utility model;
[0026] Figure 8 It is a schematic diagram of the cross-sectional structure of the bottom ring of the utility model;
[0027] Fig. 9 The structure of the crucible cover of the utility model is shown in FIG. Figure 1 ;
[0028] Fig.10 The structure of the crucible cover of the utility model is shown in FIG. Figure 2 ;
[0029] Fig.11 It is a structural schematic diagram of the support tube of the utility model.
[0030] Description of the markings in the figure:
[0031] 1. Support tube; 2. Bottom ring; 21. First step; 22. Second step; 3. Intermediate ring; 31. Third step; 311. Avoidance space; 32. Fourth step; 4. Crucible cover; 41. Cover body; 411. Threaded groove; 42. Fifth step; 43. Sixth step; 5. First crucible tube; 6. Second crucible tube; 7. Wafer; 8. Boss; 81. Placement part. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0033] Those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.
[0034] Please refer to the attached Figure 1 To Attachment Fig.11 The present invention describes a silicon carbide wafer annealing device.
[0035] like Figures 1 to 4 As shown, the silicon carbide wafer annealing device in the utility model includes a supporting tube 1, a bottom ring 2 is arranged on the supporting tube 1, a plurality of intermediate rings 3 are stacked in sequence on the bottom ring 2, a crucible cover 4 is arranged at one end of the plurality of intermediate rings 3 away from the bottom ring 2, the bottom ring 2 and the intermediate rings 3 are both hollow annular structures, a plurality of bosses 8 are arranged on the side of the hollow annular structure away from the supporting tube 1, and the wafer 7 is overlapped and arranged on the plurality of bosses 8.
[0036] By arranging a bottom ring 2 on the support tube 1, a plurality of intermediate rings 3 are stacked on the bottom ring 2 in sequence, a crucible cover 4 is arranged on one end of the plurality of intermediate rings 3 away from the bottom ring 2, the bottom ring 2 and the intermediate ring 3 are both hollow annular structures, a plurality of bosses 8 are arranged on the side of the hollow annular structure away from the support tube 1, and the wafer 7 is overlapped and arranged on the plurality of bosses 8, the support tube 1, the bottom ring 2, the intermediate ring 3 and the crucible cover 4 can be reused, and the utilization rate is improved. The plurality of intermediate rings 3 are arranged to facilitate the separation of the wafer 7, and the plurality of bosses 8 are arranged at intervals to facilitate the taking of the wafer 7, and the structure is simple and the cost is reduced. In this embodiment, the number of the intermediate rings 3 can be set to multiple according to the actual situation, and the structures of the plurality of intermediate rings 3 are the same. The plurality of intermediate rings 3 are stacked and arranged on the bottom ring 2 in sequence, and the wafer 7 is placed on each intermediate ring 3. In this embodiment, 4 bosses 8 are arranged at intervals on the bottom ring 2, and 4 bosses 8 are also arranged at intervals on the intermediate ring 3. In other embodiments, the number of bosses 8 can also be set to 3 or other numbers.
[0037] Further, if Figures 1 to 11 As shown, the support tube 1, the bottom ring 2, the plurality of intermediate rings 3 and the crucible cover 4 are threadedly connected. In other embodiments, the support tube 1, the bottom ring 2, the plurality of intermediate rings 3 and the crucible cover 4 can also be connected by snap-fitting or other connection methods.
[0038] Further, if Figure 7 and Figure 8As shown, the bottom ring 2 includes an annular first step 21 and a second step 22, the first step 21 and the second step 22 are in a Z-shaped structure, the Z-shaped structure is overlapped on the support tube 1, the side wall of the second step 22 is provided with a first internal thread, the outer periphery of the support tube 1 is provided with a first external thread, the first internal thread is screwed with the first external thread, and a plurality of bosses 8 are arranged at intervals on the first step 21. By providing the first external thread and the first internal thread, the threaded connection between the bottom ring 2 and the support tube 1 is achieved. In this embodiment, the bottom ring 2 is arranged in an annular structure to reduce the overall weight of the bottom ring 2 and save materials.
[0039] Further, if Figure 5 and Figure 6 As shown, the intermediate ring 3 includes an annular third step 31 and a fourth step 32, the third step 31 and the fourth step 32 are in a Z-shaped structure, the Z-shaped structure is overlapped on the bottom ring 2, the side wall of the fourth step 32 is provided with a second internal thread, the outer periphery of the first step 21 is provided with a second external thread, the second internal thread is screwed with the second external thread, and a plurality of bosses 8 are arranged at intervals on the second step 22. By providing the second external thread and the second internal thread, the threaded connection between the intermediate ring 3 and the bottom ring 2, and the threaded connection between the intermediate ring 3 and the adjacent intermediate ring 3 are realized. In this embodiment, the intermediate ring 3 is arranged in an annular structure to reduce the overall weight of the intermediate ring 3 and save materials.
[0040] Further, if Figures 2 to 4 As shown, the third step 31 is provided with an escape space 311 for evading the wafer 7. By providing the escape space 311, it is possible to avoid interference with the wafer 7 placed on the bottom ring 2 and the middle ring 3 or with the wafer 7 when the bottom ring 2 and the middle rings 3 are stacked together.
[0041] Further, if Figures 1 to 11 As shown, a plurality of bosses 8 are recessed to form a placement portion 81, and the chip 7 is placed on the placement portion 81. The placement portion 81 is provided on the boss 8, which can not only fix and limit the chip 7, but also protect the chip 7. At the same time, the bosses 8 arranged at intervals can facilitate the removal of the chip 7 from between the bosses 8 to prevent the chip 7 itself from being scratched.
[0042] Further, if Figure 1 and Figure 2As shown, the crucible cover 4 includes a cover body 41, and a fifth step 42 and a sixth step 43 are provided on the cover body 41. The fifth step 42 and the sixth step 43 are in an L-shaped structure. The fifth step 42 overlaps the intermediate ring 3, and the side wall of the sixth step 43 is provided with a third internal thread, and the outer periphery of the third step 31 is provided with a third external thread, and the third internal thread is threadedly connected with the third external thread. In this embodiment, after multiple intermediate rings 3 are provided according to actual conditions, the intermediate ring 3 farthest from the bottom ring 2 is threadedly connected with the crucible cover 4, specifically, the fifth step 42 of the crucible cover 4 overlaps the third step 31 of the intermediate ring 3 farthest from the bottom ring 2, and the side wall of the sixth step 43 is provided with a third internal thread, and the third internal thread is threadedly connected with the third external thread on the side wall of the third step 31, so as to realize the threaded connection between the crucible cover 4 and the intermediate ring 3.
[0043] Further, if Figure 1 and Fig.10 As shown, in order to facilitate the taking of the threaded support tube 1, the bottom ring 2, the plurality of intermediate rings 3 and the crucible cover 4, a thread groove 411 is provided on the cover body 41 of the crucible cover 4, and a lifting ring or a handle is screwed to the thread groove 411, so that the support tube 1, the bottom ring 2, the plurality of intermediate rings 3 and the crucible cover 4 can be taken as a whole. When the number of wafers 7 is large and the weight is heavy, a lifting ring or a handle is provided in the thread groove 411 for convenient lifting.
[0044] Further, if Figure 1 and Figure 2 As shown, the silicon carbide wafer annealing device in the utility model also includes a first crucible tube 5 and a second crucible tube 6. The second crucible tube 6 is overlapped and arranged on the first crucible tube 5 to form a receiving space. The support tube 1, the bottom ring 2, the plurality of intermediate rings 3 and the crucible cover 4 are placed in the receiving space to perform the annealing operation of the wafer 7.
[0045] The assembly process of the silicon carbide wafer annealing device in the utility model is as follows:
[0046] First, take out the crucible cover 4, multiple wafers 7, and multiple intermediate rings 3, place the multiple wafers 7 on the corresponding placement parts 81 of the intermediate rings 3, thread the crucible cover 4 and an intermediate ring 3, thread the multiple intermediate rings 3 on the intermediate ring 3 connected to the crucible cover 4 in sequence, until the required number of intermediate rings 3 are installed, and a wafer 7 is placed on the placement part 81 of each intermediate ring 3, then take out the bottom ring 2, place the wafer 7 on the installation part of the bottom ring 2, and thread the intermediate ring 3 away from the crucible cover 4 to the bottom ring 2, and thread the bottom ring 2 to the support tube 1. After the crucible cover 4, multiple intermediate rings 3, the bottom ring 2 and the support tube 1 are connected, the crucible cover 4, multiple intermediate rings 3, the bottom ring 2 and the support tube 1 are taken to the accommodating space formed by the first crucible tube 5 and the second crucible tube 6 by a lifting ring or a handle to perform an annealing operation on the wafer 7.
[0047] First, the silicon carbide wafer annealing device in the utility model can realize the simultaneous annealing of multiple wafers 7, and can freely determine the number of annealed wafers 7 according to the actual situation of the annealing furnace. At the same time, the wafers 7 are easy and convenient to take and put. The accessories in the annealing device can be batch-produced according to standard parts and can be reused many times, which effectively saves costs and greatly improves production efficiency. Secondly, the silicon carbide wafer annealing device in the utility model can be used for annealing 6-inch and 8-inch wafers 7 at the same time, greatly improving the utilization efficiency without causing waste materials, inventory waste, etc. Finally, when the number of wafers 7 in the silicon carbide wafer annealing device in the utility model is large and the weight is heavy, a lifting ring or a handle is set in the screw groove for easy lifting.
[0048] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation methods here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the claims of the present invention.
Claims
1. A silicon carbide wafer annealing device, characterized in that: It includes a supporting tube, on which a bottom ring is arranged, on which a plurality of intermediate rings are stacked in sequence, a crucible cover is arranged at one end of the plurality of intermediate rings away from the bottom ring, the bottom ring and the intermediate rings are both hollow ring structures, a plurality of bosses are arranged at one side of the hollow ring structure away from the supporting tube, and wafers are overlapped and arranged on the plurality of bosses.
2. The silicon carbide wafer annealing device according to claim 1, characterized in that: The support tube, the bottom ring, the plurality of intermediate rings and the crucible cover are threadedly connected.
3. The silicon carbide wafer annealing device according to claim 1, characterized in that: The bottom ring includes an annular first step and a second step, the first step and the second step are in a Z-shaped structure, the Z-shaped structure is overlapped on the support tube, the side wall of the second step is provided with a first internal thread, the outer periphery of the support tube is provided with a first external thread, and the first internal thread is screwed with the first external thread.
4. The silicon carbide wafer annealing device according to claim 3, characterized in that: A plurality of bosses are arranged on the first step at intervals.
5. The silicon carbide wafer annealing device according to claim 3, characterized in that: The middle ring includes annular third and fourth steps, which are in a Z-shaped structure. The Z-shaped structure is overlapped on the bottom ring. The side wall of the fourth step is provided with a second internal thread, and the outer periphery of the first step is provided with a second external thread. The second internal thread is screwed to the second external thread.
6. The silicon carbide wafer annealing device according to claim 5, characterized in that: The third step is provided with an escape space for escaping the wafer.
7. The silicon carbide wafer annealing device according to claim 5, characterized in that: A plurality of bosses are arranged on the second step at intervals.
8. The silicon carbide wafer annealing device according to claim 1, characterized in that: A plurality of bosses are recessed to form a placement portion, and a wafer is placed on the placement portion.
9. The silicon carbide wafer annealing device according to claim 5, characterized in that: The crucible cover includes a cover body, on which a fifth step and a sixth step are arranged, the fifth step and the sixth step are L-shaped structures, the fifth step is overlapped on the middle ring, the side wall of the sixth step is arranged with a third internal thread, the outer periphery of the third step is arranged with a third external thread, and the third internal thread is screwed with the third external thread.
10. The silicon carbide wafer annealing device according to claim 9, characterized in that: A thread groove is provided on the cover body, and a lifting ring or a handle is screwed into the thread groove.