Large-bandwidth high-speed acquisition playback circuit

Abstract

The utility model provides a large-bandwidth high-speed acquisition playback circuit, which comprises an HMC7044 high-performance clock manager, an AD9680 sampling chip, an XC7K410T processing chip and a single board computer, the HMC7044 high-performance clock manager is electrically connected with a control module in the XC7K410T processing chip, the XC7K410T processing chip is controlled by using a register, and the single board computer is connected with the AD9680 sampling chip. The HMC7044 high-performance clock manager is electrically connected with the AD9680 sampling chip and is used for providing a clock signal for the AD9680 sampling chip, and the HMC7044 high-performance clock manager is electrically connected with an IP control core module in the XC7K410T processing chip and is used for outputting the clock signal to the IP control core module; the AD9680 sampling chip is electrically connected with the XC7K410T processing chip and is used for register control, and a PCIE (Peripheral Component Interface Express) interface in the XC7K410T processing chip is electrically connected with the single-board computer and is used for realizing broadband data spectrum display.

Description

Technical Field

[0001] The utility model belongs to the technical field of data processing, and in particular relates to a large-bandwidth high-speed acquisition and playback circuit. Background Art

[0002] With the advancement of science and technology, the development of modern communications, aerospace and other fields, data throughput is increasing, and the demand for high-speed and large-bandwidth acquisition and playback equipment is also increasing, which requires a significant increase in the sampling rate of ADC. Most of the digital interfaces of traditional ADCs are differential LVDS interfaces, with high PCB wiring density and a single-channel maximum sampling rate of only about 250MSPS, which can no longer meet the requirements of modern large-bandwidth and high-speed acquisition. Summary of the invention

[0003] In view of this, the utility model aims to propose a large bandwidth high-speed acquisition and playback circuit to solve the technical problem that the reception of the line signal for serial communication in the prior art cannot meet the requirements of serial communication.

[0004] In order to achieve the above object, the technical solution of the utility model is implemented as follows:

[0005] A high-speed acquisition and playback circuit with large bandwidth, comprising:

[0006] HMC7044 high-performance clock manager, AD9680 sampling chip, XC7K410T processing chip and single-board computer, the HMC7044 high-performance clock manager is electrically connected to the control module in the XC7K410T processing chip, and the XC7K410T processing chip is controlled by registers. The HMC7044 high-performance clock manager is electrically connected to the AD9680 sampling chip to provide a clock signal to the AD9680 sampling chip. The HMC7044 high-performance clock manager is electrically connected to the IP control core module in the XC7K410T processing chip to output a clock signal to the IP control core module; the AD9680 sampling chip is electrically connected to the XC7K410T processing chip for register control, and the PCIE interface control in the XC7K410T processing chip is electrically connected to the single-board computer to realize broadband data spectrum display.

[0007] Furthermore, the XC7K410T processing chip includes: a multi-phase filtering algorithm module, one end of the multi-phase filtering algorithm module is electrically connected to the IP control core module, and the other end of the multi-phase filtering algorithm module is electrically connected to the PCIE interface control.

[0008] Furthermore, the HMC7044 high-performance clock manager outputs 8 clocks, of which 4 are supplied to a dual-channel ADC, the first is supplied to the XC7K410T processing chip FPGA as a high-speed BANK reference clock, the second is supplied to the FPGA in the XC7K410T processing chip as a common BANK synchronous global clock, the third is supplied to the XC7K410T processing chip FPGA as a common BANK low-speed system reference clock, and the last is designed as a redundant clock.

[0009] Furthermore, the IP control core module is set to 800MHz with a central frequency of 600MHz and a sampling bandwidth of 160MHz, refclk uses 200MHz of a high-speed BANK, glbclk uses 200MHz of a normal BANK, and rx_sysref selects 3.125MHz.

[0010] Furthermore, in the IP control core module, rxp is connected to ADC to output high-speed data, and the m_axis_rx interface outputs AXI standard AD sampling data.

[0011] Furthermore, the polyphase filtering module requires 4 groups of FIR filters, and the coefficients of each group of filters are divided into 4 parts according to the phase relationship by the FIR filter coefficients of sampling rate 800MHz, passband cutoff frequency 80MHz, stopband cutoff frequency 100MHz, passband flatness 0.5dB, and stopband attenuation 80dB.

[0012] Compared with the prior art, the large-bandwidth high-speed acquisition and playback circuit described in the utility model has the following advantages: the large-bandwidth high-speed acquisition and playback circuit described in the utility model, through the HMC7044 high-performance clock manager, AD9680 sampling chip, XC7K410T processing chip and single-board computer, the HMC7044 high-performance clock manager is electrically connected to the control module in the XC7K410T processing chip, and the XC7K410T processing chip is controlled by a register, the HMC7044 high-performance clock manager is electrically connected to the AD9680 sampling chip, and is used to provide a clock signal to the AD9680 sampling chip, the HMC7044 high-performance clock manager is electrically connected to the IP control core module in the XC7K410T processing chip, and is used to output a clock signal to the IP control core module; the AD9680 sampling chip is electrically connected to the XC7K410T processing chip for register control, and the PCIE interface control in the XC7K410T processing chip is electrically connected to the single-board computer to realize broadband data spectrum display. It can realize the ultra-short wave large bandwidth high-speed acquisition and playback function with two channels of 800MSPS sampling rate, center frequency 600MHz, and bandwidth 160MHz, breaking through the sampling rate limitation of traditional ADC based on LVDS digital interface and reducing the design complexity of AD circuit. At the same time, the AD sampling data can reach a dynamic range of 85dBFS and a signal-to-noise ratio of 65.3dBFS, providing technical guarantee for the acquisition and playback receiver of ultra-short wave and radar signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the accompanying drawings:

[0014] Figure 1 This is a schematic diagram of the structure of a high-speed acquisition and playback circuit with large bandwidth according to an embodiment of the utility model;

[0015] Figure 2 It is a schematic diagram of the AD9680 circuit design in the large-bandwidth high-speed acquisition and playback circuit described in the embodiment of the utility model;

[0016] Figure 3 It is a structural schematic diagram of an IP control core module in a high-speed acquisition and playback circuit with large bandwidth according to an embodiment of the utility model; DETAILED DESCRIPTION

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0018] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0020] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0021] Figure 1 This is a schematic diagram of the structure of the high-speed acquisition and playback circuit with large bandwidth according to the embodiment of the utility model, see Figure 1The large bandwidth high-speed acquisition and playback circuit may include: an HMC7044 high-performance clock manager, an AD9680 sampling chip, an XC7K410T processing chip and a single-board computer. The HMC7044 high-performance clock manager is electrically connected to a control module in the XC7K410T processing chip, and the XC7K410T processing chip is controlled by a register. The HMC7044 high-performance clock manager is electrically connected to the AD9680 sampling chip to provide a clock signal to the AD9680 sampling chip. The HMC7044 high-performance clock manager is electrically connected to an IP control core module in the XC7K410T processing chip to output a clock signal to the IP control core module; the AD9680 sampling chip is electrically connected to the XC7K410T processing chip for register control, and the PCIE interface control in the XC7K410T processing chip is electrically connected to the single-board computer to realize broadband data spectrum display. The XC7K410T processing chip includes: a multi-phase filtering algorithm module, one end of the multi-phase filtering algorithm module is electrically connected to the IP control core module, and the other end is electrically connected to the PCIE interface control.

[0022] Its working principle is to first control the register of the clock management chip through the HMC7044 control module inside the FPGA, so that it outputs an 800MHz sampling clock to the AD, and at the same time outputs the 200MHz high-speed global reference clock and 3.125MHz sysref low-speed system reference clock required by the JESD204B interface. After the clock management chip is configured, the ADC register is controlled through the AD9680 control module, and the JESD204 (7.2) IP core is correctly configured to output the correct AD waveform through the AXI bus. Then, the multi-phase filtering algorithm is used to reduce the speed to 200MHz broadband data inside the FPGA, and finally uploaded to the single-board computer through the PCIE high-speed interface for broadband data spectrum display.

[0023] The clock generation module on the board uses the clock solution HMC7044 of ADI. The external sampling clock or reference clock is switched through the high-speed RF switch to be output to the reference input and sampling input of HMC7044. This design chooses RF2 to output a single-ended 10MHz reference clock. The VCO of the clock management chip uses a 100MHz crystal oscillator, and outputs a total of 8 clocks, of which 4 are supplied to the dual-channel ADC, one is supplied to the FPGA as a high-speed BANK reference clock, one is supplied to the FPGA as a common BANK synchronous global clock, one is supplied to the FPGA as a common BANK low-speed system reference clock, and the last one is used as a redundant design.

[0024] Figure 3This is a schematic diagram of the AD9680 circuit design in the large bandwidth high-speed acquisition and playback circuit described in the embodiment of the utility model, see Figure 3 The ADC chip uses two pieces of ADI's AD9680BCPZ. A single chip supports dual channels, with a bit width of 14 bits and a maximum sampling rate of 1Gsps. The input end uses a Balun circuit to achieve single-ended to differential conversion, and the output interface protocol is JESD204B.

[0025] Among them, FPGA calls JESD204 (7.2) IP core, combined with the application requirements of the utility model of 800MHz sampling 600MHz center frequency and 160MHz sampling bandwidth, refclk uses 200MHz of high-speed BANK, glbclk uses 200MHz of ordinary BANK, and rx_sysref selects 3.125MHz. Since the fixed sampling rate of the utility model is 800MHz, there is no need to connect to the dynamic configuration interface, rxp connects to ADC to output high-speed data, and the m_axis_rx interface outputs AXI standard AD sampling data.

[0026] When the 8-bit frame selection is 8 and the line width is 1, the rx_data bit width is 32 bits, of which the lower 8 bits of every 16 bits are the lower 8 bits of AD sampling, and the upper 8 bits of every 16 bits are the upper 8 bits of AD sampling. rx_start_of_frame and rx_end_of_frame indicate the start and end of a multi-frame, and advance the data by one clock in timing.

[0027] After AD9680 analog-to-digital conversion, each channel outputs 4 parallel AD digital signals, and the working clock is 200MHz. The 4 parallel AD data of each channel are sent to the multiphase filter processing module. The multiphase filter processing flow of the two channels is exactly the same. The following takes one channel as an example to illustrate the corresponding processing flow. First, the incoming 4 parallel AD data is multiplied with the intermediate frequency signal generated by DDS to complete the frequency conversion processing, and then sent to the multiphase filter module to complete the DDC processing, and finally output a broadband signal with a frequency range of -80MHz to 80MHz. 多 The phase filter module requires 4 groups of FIR filters. The coefficients of each group of filters are obtained by dividing the FIR filter coefficients of sampling rate 800MHz, passband cutoff frequency 80MHz, stopband cutoff frequency 100MHz, passband flatness 0.5dB, and stopband attenuation 80dB into 4 parts according to the phase relationship.

[0028] For example, the external reference is 10MHz, the VCXO is 100MHz, R1 is configured as 1, N1 is configured as 10, so that the clock rate output to the second-stage PLL is 200MHz, R2 is configured as 1, N2 is configured as 16, so that the clock before the divider reaches 3.2GHz, and the ADC configuration steps are as follows:

[0029] Step 1: Global reset;

[0030] Step 2: Configure the sysref clock to sample on the falling edge;

[0031] Step 3: Configure the sysref clock detection mode to continuous detection;

[0032] Step 4: Configure to ignore the first 16 sysref clock detections;

[0033] Step 5: Configure the number of JESD204B lanes (L) to 4 lanes.

[0034] Step 6: Configure the ADC resolution to 14 bits wide.

[0035] Since the ADC data is received, the JESD204B interface is first set to receive mode, the number of channels is set to 4, the 8-bit frame is set to 1, the multi-frame is set to 32 frames, and the line rate is 800MHz×16bit×10 / 8 (8b / 10b encoding)×2 (dual channels) / 4 (JESD204B channel number) = 8Gbps. According to the manual, the Refclk clock is required to have a line rate of 8GHz / 40=200MHz. Since the Refclk clock is greater than 165MHz, the global clock is used to drive the output clock of JESD204 according to the manual. The Sysref clock selects falling edge sampling, which is consistent with the ADC configuration, and the configuration mode is continuous detection, and the scrambling is set to off.

[0036] The large-bandwidth high-speed acquisition and playback circuit described in the utility model is through an HMC7044 high-performance clock manager, an AD9680 sampling chip, an XC7K410T processing chip and a single-board computer. The HMC7044 high-performance clock manager is electrically connected to a control module in the XC7K410T processing chip, and the XC7K410T processing chip is controlled by a register. The HMC7044 high-performance clock manager is electrically connected to the AD9680 sampling chip to provide a clock signal to the AD9680 sampling chip. The HMC7044 high-performance clock manager is electrically connected to an IP control core module in the XC7K410T processing chip to output a clock signal to the IP control core module; the AD9680 sampling chip is electrically connected to the XC7K410T processing chip for register control, and the PCIE interface control in the XC7K410T processing chip is electrically connected to the single-board computer to realize broadband data spectrum display. It can realize the ultra-short wave large bandwidth high-speed acquisition and playback function with two channels of 800MSPS sampling rate, center frequency 600MHz, and bandwidth 160MHz, breaking through the sampling rate limitation of traditional ADC based on LVDS digital interface and reducing the design complexity of AD circuit. At the same time, the AD sampling data can reach a dynamic range of 85dBFS and a signal-to-noise ratio of 65.3dBFS, providing technical guarantee for the acquisition and playback receiver of ultra-short wave and radar signals.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed acquisition and playback circuit with large bandwidth, characterized in that: include: HMC7044 high-performance clock manager, AD9680 sampling chip, XC7K410T processing chip and single-board computer, the HMC7044 high-performance clock manager is electrically connected to the control module in the XC7K410T processing chip, and the XC7K410T processing chip is controlled by registers. The HMC7044 high-performance clock manager is electrically connected to the AD9680 sampling chip to provide a clock signal to the AD9680 sampling chip. The HMC7044 high-performance clock manager is electrically connected to the IP control core module in the XC7K410T processing chip to output a clock signal to the IP control core module; the AD9680 sampling chip is electrically connected to the XC7K410T processing chip for register control, and the PCIE interface control in the XC7K410T processing chip is electrically connected to the single-board computer to realize broadband data spectrum display.

2. The circuit according to claim 1, characterized in that The XC7K410T processing chip includes: a multi-phase filtering algorithm module, one end of the multi-phase filtering algorithm module is electrically connected to the IP control core module, and the other end is electrically connected to the PCIE interface control.

3. The circuit according to claim 1, characterized in that The HMC7044 high-performance clock manager outputs 8 clocks, 4 of which are supplied to dual-channel ADCs, the first is supplied to the XC7K410T processing chip FPGA as a high-speed BANK reference clock, the second is supplied to the FPGA in the XC7K410T processing chip as a common BANK synchronous global clock, the third is supplied to the XC7K410T processing chip FPGA as a common BANK low-speed system reference clock, and the last is designed as a redundant clock.

4. The circuit according to claim 1, characterized in that The IP control core module is set to 800MHz with a central frequency of 600MHz and a sampling bandwidth of 160MHz according to the application requirements. refclk uses 200MHz of high-speed BANK, glbclk uses 200MHz of ordinary BANK, and rx_sysref selects 3.125MHz.

5. The circuit according to claim 4, characterized in that In the IP control core module, the rxp interface is connected to the ADC to output high-speed data, and the m_axis_rx interface outputs the AD sampling data of the AXI standard.

6. The circuit according to claim 2, characterized in that The polyphase filtering algorithm module requires 4 groups of FIR filters, and the coefficients of each group of filters are divided into 4 parts according to the phase relationship by the FIR filter coefficients of sampling rate 800MHz, passband cutoff frequency 80MHz, stopband cutoff frequency 100MHz, passband flatness 0.5dB, and stopband attenuation 80dB.

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