Package structure
By setting through holes on the substrate and embeding a heat dissipation frame, the problems of improving the chip's heat dissipation performance and simplifying the manufacturing process are solved, and the effect of efficient heat dissipation and cost reduction is achieved, while avoiding the negative impact on electrical performance.
Patent Information
- Application Number
- CN202420987464.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2034-05-08
AI Technical Summary
While improving the thermal dissipation performance of the chip, it is difficult to simplify the manufacturing process of the packaging structure, reduce manufacturing costs, and reduce the impact on electrical performance, especially because the design complexity of the thermal conductivity channel increases the design difficulty of the circuit layer inside the substrate and cost.
Design a packaging structure, by providing a through hole running through the first direction on the substrate and embed a heat dissipation frame in the through hole, the heat dissipation frame is distributed around the side of the chip and covering its back surface, reducing the occupation of the substrate area and avoiding separate Design of thermal conductivity channels, simplifying line layer design.
It enhances the heat dissipation effect of the packaging structure, reduces the difficulty of manufacturing process and manufacturing cost, reduces the impact on electrical performance, avoids the space occupied by the thermally conductive channels, and improves the overall performance of the packaging structure.
Smart Images
Figure CN222261026U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuit manufacturing, in particular to a packaging structure. Background Art
[0002] With the rapid development of microelectronics technology, the size of chips is getting smaller and smaller, while the computing speed of chips is getting faster and faster, which makes the heat generated by chips also get larger and larger, which puts higher requirements on the heat dissipation performance of chips. Any chip must meet a temperature range to achieve normal operation. In order to maintain the chip in a normal temperature range, it is necessary to adopt certain technical means to quickly dissipate the heat generated during the operation of the chip to the environment. At present, in order to dissipate the heat generated during the operation of the chip from the substrate in a timely manner, it is necessary to design a separate heat conduction channel on the substrate, and the heat conduction channel needs to occupy a certain area of the substrate. However, since the circuit layer in the substrate itself is relatively complex, in order to meet the design requirements of the heat conduction channel, it is necessary to adjust the design of the circuit layer so that the circuit layer avoids the heat conduction channel, which not only increases the difficulty of designing the circuit layer in the substrate and increases the manufacturing cost of the packaging structure, but also causes the spacing between the traces in the circuit layer in the substrate to be reduced, thereby affecting the electrical properties of the circuit layer, for example, it will cause an increase in the parasitic capacitance effect.
[0003] Therefore, how to improve the heat dissipation performance of the packaging structure while simplifying the manufacturing process of the packaging structure, reducing the manufacturing cost of the packaging structure, and reducing the impact on the electrical performance of the packaging structure is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The utility model provides a packaging structure, which is used to improve the heat dissipation performance of the packaging structure, simplify the manufacturing process of the packaging structure, reduce the manufacturing cost of the packaging structure, and reduce the impact on the electrical performance of the packaging structure.
[0005] According to some embodiments, the utility model provides a packaging structure, including:
[0006] A substrate, wherein the substrate has a first through hole penetrating the substrate along a first direction, wherein the first direction is perpendicular to a top surface of the substrate;
[0007] A first functional chip, at least partially located in the first through hole, the first functional chip being electrically connected to the substrate;
[0008] The first heat dissipation frame is at least embedded in the first through hole and connected to the substrate. The first heat dissipation frame is distributed around the side surface of the first function chip and covers the back surface of the first function chip.
[0009] In some embodiments, the bottom surface of the first heat dissipation frame is flush with the bottom surface of the substrate; or,
[0010] The bottom surface of the first heat dissipation frame protrudes from the bottom surface of the substrate along the first direction.
[0011] In some embodiments, the first heat dissipation frame comprises:
[0012] A first part is embedded in the first through hole, and is distributed around the side of the first functional chip and covers the back of the first functional chip;
[0013] The second part is connected to the first part and covers a portion of the top surface of the substrate. The second part is distributed at least along a second direction on two opposite sides of the first through hole. The second direction is parallel to the top surface of the substrate.
[0014] In some embodiments, it also includes:
[0015] The first insulating adhesive layer is located between the first portion and the inner wall of the first through hole and between the second portion and the substrate, and the first insulating adhesive layer connects the first portion and the inner wall of the first through hole and the second portion and the substrate.
[0016] In some embodiments, a groove is formed on the top surface of the substrate, and an end of the second portion facing away from the first portion has a bending foot, and the bending foot is embedded in the groove.
[0017] In some embodiments, it also includes:
[0018] A plastic sealing layer covering the top surface of the substrate and the bottom surface of the substrate, wherein the plastic sealing layer located on the bottom surface of the substrate has a groove exposing the bottom of the first heat dissipation frame;
[0019] The heat dissipation element is located in the groove and covers the bottom of the first heat dissipation frame.
[0020] In some embodiments, it also includes:
[0021] a second function chip, at least partially located in the first through hole, the first function chip and the second function chip are arranged in a spaced relationship along the second direction, the front surface of the first function chip faces the same direction as the top surface of the substrate, and the front surface of the second function chip faces the same direction as the bottom surface of the substrate;
[0022] The first heat dissipation frames are continuously distributed on the side surface of the first function chip, on the back surface of the first function chip, on the side surface of the second function chip, and on the back surface of the second function chip.
[0023] In some embodiments, the substrate further has a second through hole penetrating the substrate along the first direction, the first through hole and the second through hole are arranged along a second direction, and the second direction is parallel to the top surface of the substrate; the packaging structure further includes:
[0024] a second functional chip, at least partially located in the second through hole, the second functional chip being electrically connected to the substrate;
[0025] The first heat dissipation frame is continuously embedded in the first through hole and the second through hole, and the first heat dissipation frame is also distributed around the side surface of the second function chip and covers the back surface of the second function chip.
[0026] In some embodiments, the substrate further has a second through hole penetrating the substrate along the first direction, the first through hole and the second through hole are arranged along a second direction, and the second direction is parallel to the top surface of the substrate; the packaging structure further includes:
[0027] a second functional chip, at least partially located in the second through hole, the second functional chip being electrically connected to the substrate;
[0028] The second heat dissipation frame is embedded in the second through hole and connected to the substrate. The second heat dissipation frame is distributed around the side of the second functional chip and covers the back of the second functional chip. The second heat dissipation frame is independent of the first heat dissipation frame.
[0029] In some embodiments, the substrate further has a second through hole penetrating the substrate along the first direction, the first through hole and the second through hole are arranged along a second direction, and the second direction is parallel to the top surface of the substrate; the packaging structure further includes:
[0030] a second functional chip, at least partially located in the second through hole, the second functional chip being electrically connected to the substrate;
[0031] A second heat dissipation frame is embedded in the second through hole and connected to the substrate. The second heat dissipation frame is distributed around the side of the second functional chip and covers the back of the second functional chip. The bottom of the first heat dissipation frame protrudes from the bottom surface of the substrate along the first direction, and the bottom of the second heat dissipation frame protrudes from the top surface of the substrate along the first direction.
[0032] In some embodiments, it also includes:
[0033] A plastic encapsulation layer, covering the top surface of the substrate and the bottom surface of the substrate, wherein the plastic encapsulation layer encapsulates the first function chip and the second function chip;
[0034] The bottom surface of the second heat dissipation frame is exposed to the top surface of the plastic packaging layer, and the bottom surface of the first heat dissipation frame is exposed to the bottom surface of the plastic packaging layer.
[0035] The packaging structure provided by the utility model is provided with a first through hole penetrating the substrate along a first direction on the substrate, and a first functional chip is at least partially placed in the first through hole, and a first heat dissipation frame at least partially embedded in the first through hole is provided, and the first heat dissipation frame is distributed around the side of the first functional chip and covers the back of the first functional chip. On the one hand, the first heat dissipation frame can dissipate heat for the first functional chip, thereby enhancing the heat dissipation effect of the packaging structure; on the other hand, the first heat dissipation frame and the first functional chip are simultaneously accommodated in the first through hole, and there is no need to provide a separate heat conduction channel in the substrate, which reduces the occupation of the substrate area and reduces the impact on the design of the circuit layer in the substrate, thereby reducing the difficulty and manufacturing cost of the manufacturing process of the packaging structure and avoiding the impact on the electrical performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Attached Figure 1 It is a cross-sectional schematic diagram of a first packaging structure in a specific implementation mode of the utility model;
[0037] Attached Figure 2 It is a top view schematic diagram of the first packaging structure in a specific implementation mode of the utility model;
[0038] Attached Figure 3 It is a cross-sectional schematic diagram of a second packaging structure in a specific implementation manner of the utility model;
[0039] Attached Figure 4 It is a cross-sectional schematic diagram of a third packaging structure in a specific implementation manner of the utility model;
[0040] Attached Figure 5 It is a cross-sectional schematic diagram of a fourth packaging structure in a specific implementation manner of the utility model;
[0041] Attached Figure 6 It is a cross-sectional schematic diagram of a fifth packaging structure in a specific implementation manner of the utility model;
[0042] Attached Figure 7 It is a cross-sectional schematic diagram of a sixth packaging structure in a specific implementation manner of the utility model;
[0043] Attached Figure 8 It is a cross-sectional schematic diagram of the seventh packaging structure in the specific implementation manner of the utility model. DETAILED DESCRIPTION
[0044] The specific implementation of the packaging structure provided by the utility model is described in detail below with reference to the accompanying drawings.
[0045] This specific implementation provides a packaging structure, Figure 1 is a cross-sectional schematic diagram of the first packaging structure in a specific implementation mode of the utility model, Figure 2 Schematic diagram of the top view of the first packaging structure in the specific implementation mode of the utility model. Figure 1 and Figure 2 As shown, the packaging structure includes:
[0046] A substrate 10, wherein the substrate 10 has a first through hole penetrating the substrate 10 along a first direction D1, wherein the first direction D1 is perpendicular to a top surface of the substrate 10;
[0047] A first functional chip 12, at least partially located in the first through hole, and the first functional chip 12 is electrically connected to the substrate 10;
[0048] The first heat dissipation frame 13 is at least embedded in the first through hole and connected to the substrate 10 . The first heat dissipation frame 13 surrounds the side surface of the first function chip 12 and covers the back surface of the first function chip 12 .
[0049] For example, if Figure 1 and Figure 2As shown, the substrate 10 includes a top surface and a bottom surface relatively distributed along the first direction D1, the substrate 10 has a circuit layer 11 inside, and a first functional device 16 is also mounted on the top surface of the substrate 10. The first through hole penetrates the substrate 10 along the first direction D1, thereby forming a hollow substrate structure. The first functional chip 12 is at least partially embedded in the first through hole, thereby further reducing the size of the packaging structure. The first functional chip 12 also includes a front and a back surface distributed along the first direction D1, the front of the first functional chip 12 is oriented in the same direction as the top surface of the substrate 10, and the front of the first functional chip 12 is electrically connected to the circuit layer 11 in the substrate 10 through a first welding wire 17. The first heat dissipation frame 13 is at least embedded in the first through hole, and the first heat dissipation frame 13 has a bent structure, so that the bent first heat dissipation frame 13 is continuously distributed around the side of the first functional chip and covers the back of the first functional chip 12, so that the heat generated during the operation of the first functional chip 12 and the heat generated in the substrate 10 can be dissipated to the external environment through the first heat dissipation frame 13, thereby enhancing the heat dissipation effect of the packaging structure. At the same time, the first heat dissipation frame 13 and the first functional chip 12 are simultaneously accommodated in the first through hole, and there is no need to set a separate heat conduction channel in the substrate, which reduces the occupation of the substrate area and reduces the impact on the circuit layer design in the substrate 10, thereby reducing the difficulty and manufacturing cost of the manufacturing process of the packaging structure, and avoiding the impact on the electrical performance of the packaging structure.
[0050] In one example, the first heat dissipation frame 13 can be formed by stamping and bending a whole piece of metal, thereby further simplifying the manufacturing process of the packaging structure. In another example, the first heat dissipation frame 13 can include a first frame body and heat dissipation holes penetrating the first frame body, thereby forming a hollow heat dissipation frame structure, so as to further enhance the heat dissipation effect of the first heat dissipation frame 13 and enhance the connection strength between the first heat dissipation frame 13 and the substrate 10.
[0051] In order to further dissipate the heat in the packaging structure (including the first functional chip 12 and the substrate 10) to the external environment as quickly as possible, in some embodiments, the bottom surface of the first heat dissipation frame 13 is flush with the bottom surface of the substrate 10; or,
[0052] The bottom surface of the first heat dissipation frame 13 protrudes from the bottom surface of the substrate 10 along the first direction D1.
[0053] In some embodiments, the first heat dissipation frame 13 includes:
[0054] The first portion 131 is embedded in the first through hole, and is distributed around the side of the first function chip 12 and covers the back of the first function chip 12;
[0055] The second portion 132 is connected to the first portion 131 and covers a portion of the top surface of the substrate 10 . The second portion 132 is distributed at least along a second direction D2 on two opposite sides of the first through hole. The second direction D2 is parallel to the top surface of the substrate 10 .
[0056] For example, if Figure 1 As shown, the first heat dissipation frame 131 includes the first part 131 and the second part 132 which are integrally formed by a stamping and bending process, the first part 131 is a bending structure, and the second part 132 is a horizontal structure. The first part 131 is located in the first through hole and continuously covers the inner wall of the first through hole and the back of the first functional chip 12. In one example, the back of the first functional chip 12 is connected to the first part 131 through the first thermal conductive adhesive 15 to further enhance the heat dissipation performance of the first functional chip 12. The second part 132 is distributed on the opposite sides of the first through hole at least along the second direction D2, thereby enhancing the stability of the connection between the first heat dissipation frame 13 and the substrate 10. In one example, the second part 132 is distributed around the periphery of the first through hole. In another example, the second portion 132 is distributed not only on the opposite sides of the first through hole along the second direction D2, but also on the opposite sides of the first through hole along a third direction D3, wherein the third direction D3 is parallel to the top surface of the substrate 10, and the second direction D2 intersects with the third direction D3 to further enhance the connection strength between the first heat dissipation frame 13 and the substrate 10.
[0057] In some embodiments, the packaging structure further includes:
[0058] The first insulating adhesive layer 14 is located between the first portion 131 and the inner wall of the first through hole and between the second portion 132 and the substrate 10 . The first insulating adhesive layer 14 connects the first portion 131 and the inner wall of the first through hole and the second portion 132 and the substrate 10 .
[0059] Specifically, the first insulating adhesive layer 14 is distributed on the inner wall of the first through hole and a portion of the top surface of the substrate 10 , and the first heat dissipation frame 13 is connected to the substrate 10 through the first insulating adhesive layer 14 to further enhance the connection strength between the first heat dissipation frame 13 and the substrate 10 .
[0060] Attached Figure 3is a cross-sectional schematic diagram of a second packaging structure in a specific embodiment of the utility model. Figure 3 As shown, a groove 30 is provided on the top surface of the substrate 10 , and an end of the second portion 132 facing away from the first portion 131 has a bending foot, and the bending foot is embedded in the groove 30 .
[0061] Specifically, if Figure 3 As shown, a plurality of grooves 30 are provided on the top surface of the substrate 10, and the end of the second part 132 away from the first part 131 may have a plurality of bending legs corresponding to the plurality of grooves 30 one by one. By embedding the plurality of bending legs into the plurality of grooves 30 one by one, the first heat dissipation frame 13 can be further prevented from shaking or position shifting, and the stability of the connection between the first heat dissipation frame 13 and the substrate 10 can be further improved. In an example, the first insulating adhesive layer 14 is also filled in the groove 30 to connect the bending legs to the substrate 10. The plurality described in this specific embodiment refers to more than two.
[0062] Attached Figure 4 is a cross-sectional schematic diagram of a third packaging structure in a specific implementation mode of the utility model. In other embodiments, such as Figure 4 As shown, the packaging structure also includes:
[0063] A plastic sealing layer 18 covering the top surface of the substrate 10 and the bottom surface of the substrate 10, wherein the plastic sealing layer 18 located on the bottom surface of the substrate 10 has a groove exposing the bottom of the first heat dissipation frame 13;
[0064] The heat sink 40 is located in the groove and covers the bottom of the first heat sink frame 13 .
[0065] Specifically, if Figure 4As shown, the plastic encapsulation layer 18 is distributed on the top surface of the substrate 10 and the bottom surface of the substrate 10, that is, the packaging structure is a double-sided packaging structure, thereby further enhancing the stability of the packaging structure, reducing the probability of the substrate 10 in the packaging structure being warped or reducing the deformation amount of the substrate 10 when warping occurs. The bottom surface of the substrate 18 also has a solder ball 41 and a second functional device 42, and the plastic encapsulation layer 18 plastic encapsulates the second functional device 42, and one end of the solder ball 41 is electrically connected to the circuit layer 11 in the substrate 10, and the other end protrudes from the surface of the plastic encapsulation layer 18. The plastic encapsulation layer 18 located on the bottom surface of the substrate 10 has a groove that exposes the bottom of the first heat dissipation frame 13, and the heat sink 40 fills the groove and covers the surface of the first heat dissipation frame 13 away from the first functional chip 12, so as to quickly remove the heat generated by the first functional chip 12. In an example, the heat sink 40 can be connected to the first heat dissipation structure 13 by a thermally conductive adhesive, thereby further enhancing the stability of the packaging structure. The material of the heat sink 40 may be the same as that of the first heat sink frame 13 , for example, both are metal materials.
[0066] In some further embodiments, the packaging structure further includes:
[0067] The plastic sealing layer 18 covers the top surface of the substrate 10 and the bottom surface of the substrate 10, and the first heat dissipation frame 13 also includes a thickened portion, and the thickened portion and the first functional chip 12 are located on opposite sides of the first part 131 along the first direction D1. The thickened portion is away from the surface of the first part 131 and the surface exposed to the plastic sealing layer 18, thereby reducing the warping of the substrate 10 and further enhancing the heat dissipation effect of the packaging structure.
[0068] Attached Figure 5 is a cross-sectional schematic diagram of a fourth packaging structure in a specific implementation mode of the utility model. In other embodiments, such as Figure 5 As shown, the packaging structure also includes:
[0069] The second function chip 50 is at least partially located in the first through hole, the first function chip 12 and the second function chip 50 are arranged in the second direction D2, the front surface of the first function chip 12 faces the same direction as the top surface of the substrate 10, and the front surface of the second function chip 50 faces the same direction as the bottom surface of the substrate 10;
[0070] The first heat dissipation frames 13 are continuously distributed on the side surface of the first function chip 12 , on the back surface of the first function chip 12 , on the side surface of the second function chip 50 , and on the back surface of the second function chip 50 .
[0071] Specifically, if Figure 5 As shown, the first through hole has the first function chip 12 and the second function chip 50 arranged at intervals along the second direction D2, the front of the first function chip 12 faces the same direction as the top surface of the substrate 10, and the front of the second function chip 50 faces the same direction as the bottom surface of the substrate 10, that is, the front of the first function chip 12 faces the opposite direction to the front of the second function chip 50. The first welding wire 17 is located on the top surface of the substrate 10, and one end of the first welding wire 17 is electrically connected to the front of the first function chip 12, and the other end is electrically connected to the circuit layer 11 exposed on the top surface of the substrate 10. The second welding wire 52 is located on the bottom surface of the substrate 10, and one end of the second welding wire 52 is electrically connected to the front of the second function chip 50, and the other end is electrically connected to the circuit layer 11 exposed on the bottom surface of the substrate 10. The portion of the first heat dissipation frame 13 located in the first through hole has a plurality of bends, so that the first heat dissipation frame 13 can be continuously distributed on the side of the first functional chip 12, the back of the first functional chip 12, the side of the second functional chip 50 and the back of the second functional chip 50, so that the first heat dissipation frame 13 can dissipate heat for the first functional chip 12 and the second functional chip 50 at the same time. The second functional chip 50 can also be bonded to the first heat dissipation frame 13 through a second insulating adhesive layer 51. In one example, the packaging structure further includes a plastic sealing layer 18, the plastic sealing layer 18 plastic seals the substrate 10, the first functional chip 12 and the second functional chip 50, and the plastic sealing layer 18 has an opening exposing the first heat dissipation frame 13, so as to quickly dissipate the heat generated by the first functional chip 12 and the second functional chip 50 to the external environment.
[0072] Attached Figure 6 is a cross-sectional schematic diagram of a fifth packaging structure in a specific implementation mode of the utility model. In other embodiments, such as Figure 6 As shown, the substrate 10 further has a second through hole penetrating the substrate 10 along the first direction D1, the first through hole and the second through hole are arranged along the second direction D2, and the second direction D2 is parallel to the top surface of the substrate 10; the packaging structure also includes:
[0073] A second functional chip 50, at least partially located in the second through hole, and the second functional chip 50 is electrically connected to the substrate 10;
[0074] The first heat dissipation frame 13 is continuously embedded in the first through hole and the second through hole, and the first heat dissipation frame 13 is also distributed around the side surface of the second function chip 50 and covers the back surface of the second function chip 50 .
[0075] Specifically, if Figure 6 As shown, the substrate 10 has the first through hole and the second through hole arranged along the second direction D2, the first function chip 12 is embedded in the first through hole, and the second function chip 50 is embedded in the second through hole. The front of the first function chip 12 is oriented in the same direction as the front of the second function chip 50, and the back of the first function chip 12 is oriented in the same direction as the back of the second function chip 50. The first heat dissipation frame 13 is continuously distributed around the side of the first function chip 12 and the side of the second function chip 50, and the first heat dissipation frame 13 covers the back of the first function chip 12 and the back of the second function chip 50. By continuously embedding the first heat dissipation frame 13 in the first through hole and the second through hole, the first function chip 12 and the second function chip 50 can be cooled at the same time, and the manufacturing process of the packaging structure can be further simplified. In one example, the first heat dissipation frame 13 covering the back of the first function chip 12 and the back of the second function chip 50 protrudes from the bottom surface of the substrate 10 along the first direction D1 to further improve the heat dissipation effect of the first heat dissipation frame 13.
[0076] Attached Figure 7 is a cross-sectional schematic diagram of a sixth packaging structure in a specific implementation mode of the utility model. In other embodiments, such as Figure 7 As shown, the substrate 10 further has a second through hole penetrating the substrate 10 along the first direction D1, the first through hole and the second through hole are arranged along the second direction D2, and the second direction D2 is parallel to the top surface of the substrate 10; the packaging structure also includes:
[0077] A second functional chip 50, at least partially located in the second through hole, and the second functional chip 50 is electrically connected to the substrate 10;
[0078] The second heat dissipation frame 70 is embedded in the second through hole and connected to the substrate 10. The second heat dissipation frame 70 is distributed around the side of the second functional chip 50 and covers the back of the second functional chip 50. The second heat dissipation frame 70 is independent of the first heat dissipation frame 13.
[0079] Specifically, if Figure 7As shown, the substrate 10 has the first through hole and the second through hole arranged along the second direction D2, the first functional chip 12 is embedded in the first through hole, and the second functional chip 50 is embedded in the second through hole. In one example, the second heat dissipation frame 70 includes a third part 701 embedded in the second through hole and a fourth part 702 connected to the third part 701 and covering a portion of the top surface of the substrate 10, and the third part 701 is distributed around the side of the second functional chip 50 and covers the back of the second functional chip 50. The first functional chip 12 dissipates heat through the first heat dissipation frame 13, and the second functional chip 50 dissipates heat through the second heat dissipation frame 70. The second heat dissipation frame 70 is independent of the first heat dissipation frame 13, that is, the second heat dissipation frame 70 is not connected to the first heat dissipation frame 13, so as to avoid occupying too much space on the top surface of the substrate 10, thereby improving the flexibility of the functional device design on the top surface of the substrate 10. In one example, the plurality of first through holes and the plurality of second through holes are evenly distributed in the substrate 10, the plurality of first heat dissipation frames 13 are distributed one by one in the plurality of first through holes, and the plurality of second heat dissipation structures are distributed one by one in the plurality of second through holes, so as to prevent stress concentration in the substrate 10 and reduce or even avoid warping of the substrate 10. In one example, the shape and size of the first through hole can be the same as the shape and size of the second through hole, and the structure of the first heat dissipation frame 13 is the same as the structure of the second heat dissipation frame 70, so as to further simplify the manufacturing process of the packaging structure.
[0080] Attached Figure 8 is a cross-sectional schematic diagram of the seventh packaging structure in the specific implementation mode of the utility model. In some other embodiments, such as Figure 8 As shown, the substrate 10 further has a second through hole penetrating the substrate 10 along the first direction D1, the first through hole and the second through hole are arranged along the second direction D2, and the second direction D2 is parallel to the top surface of the substrate 10; the packaging structure also includes:
[0081] A second functional chip 50, at least partially located in the second through hole, and the second functional chip 50 is electrically connected to the substrate 10;
[0082] The second heat dissipation frame 70 is embedded in the second through hole and connected to the substrate 10. The second heat dissipation frame 70 is distributed around the side of the second functional chip 50 and covers the back of the second functional chip 50. The bottom of the first heat dissipation frame 13 protrudes from the bottom surface of the substrate 10 along the first direction D1, and the bottom of the second heat dissipation frame 70 protrudes from the top surface of the substrate 10 along the first direction D1.
[0083] In some embodiments, the packaging structure further includes:
[0084] A plastic encapsulation layer 18, covering the top surface of the substrate 10 and the bottom surface of the substrate 10, wherein the plastic encapsulation layer 18 encapsulates the first function chip 12 and the second function chip 50;
[0085] The bottom surface of the second heat dissipation frame 70 is exposed to the top surface of the plastic packaging layer 18 , and the bottom surface of the first heat dissipation frame 13 is exposed to the bottom surface of the plastic packaging layer 18 .
[0086] Specifically, if Figure 8 As shown, the substrate 10 has the first through hole and the second through hole arranged along the second direction D2, the first function chip 12 is embedded in the first through hole, and the second function chip 50 is embedded in the second through hole. In one example, the second heat dissipation frame 70 includes a third part 701 embedded in the second through hole and a fourth part 702 connected to the third part 701 and covering a portion of the top surface of the substrate 10, and the third part 701 is distributed around the side of the second function chip 50 and covers the back of the second function chip 50. The front of the first function chip 12 is oriented in the same direction as the top surface of the substrate 10, and the front of the second function chip 50 is oriented in the same direction as the bottom surface of the substrate 10, that is, the front of the first function chip 12 is oriented opposite to the front of the second function chip 50. The first function chip 12 dissipates heat through the first heat dissipation frame 13, and the second function chip 50 dissipates heat through the second heat dissipation frame 70. The second heat dissipation frame 70 is independent of the first heat dissipation frame 13, that is, the second heat dissipation frame 70 is not connected to the first heat dissipation frame 13, so as to avoid occupying too much space on the top surface of the substrate 10, thereby improving the flexibility of designing functional devices on the top surface of the substrate 10. The plastic encapsulation layer 18 covers the top surface of the substrate 10 and the bottom surface of the substrate 10, and plastic encapsulates the first functional chip 12, the second functional chip 50 and the substrate 10. The bottom of the first heat dissipation frame 13 and the bottom of the second heat dissipation frame 70 are both thickened, so that the bottom surface of the second heat dissipation frame 70 and the bottom surface of the first heat dissipation frame 13 are exposed to the surface of the plastic encapsulation layer 18, so as to further enhance the heat dissipation effect of the packaging structure.
[0087] The packaging structure provided in this specific embodiment is provided with a first through hole penetrating the substrate along a first direction on the substrate, and a first functional chip is at least partially placed in the first through hole, and a first heat dissipation frame at least partially embedded in the first through hole is provided, and the first heat dissipation frame is distributed around the side of the first functional chip and covers the back of the first functional chip. On the one hand, the first heat dissipation frame can dissipate heat for the first functional chip, thereby enhancing the heat dissipation effect of the packaging structure; on the other hand, the first heat dissipation frame and the first functional chip are simultaneously accommodated in the first through hole, and there is no need to provide a separate heat conduction channel in the substrate, which reduces the occupation of the substrate area and reduces the impact on the design of the circuit layer in the substrate, thereby reducing the difficulty and manufacturing cost of the manufacturing process of the packaging structure and avoiding affecting the electrical performance of the packaging structure.
[0088] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A packaging structure, characterized in that: include: A substrate, wherein the substrate has a first through hole penetrating the substrate along a first direction, wherein the first direction is perpendicular to a top surface of the substrate; A first functional chip, at least partially located in the first through hole, the first functional chip being electrically connected to the substrate; The first heat dissipation frame is at least embedded in the first through hole and connected to the substrate. The first heat dissipation frame is distributed around the side surface of the first function chip and covers the back surface of the first function chip.
2. The packaging structure according to claim 1, characterized in that: The bottom surface of the first heat dissipation frame is flush with the bottom surface of the substrate; or, The bottom surface of the first heat dissipation frame protrudes from the bottom surface of the substrate along the first direction.
3. The packaging structure according to claim 1, characterized in that: The first heat dissipation frame comprises: A first part is embedded in the first through hole, and is distributed around the side of the first functional chip and covers the back of the first functional chip; The second part is connected to the first part and covers a portion of the top surface of the substrate. The second part is distributed at least along a second direction on two opposite sides of the first through hole. The second direction is parallel to the top surface of the substrate.
4. The packaging structure according to claim 3, characterized in that: Also includes: The first insulating adhesive layer is located between the first portion and the inner wall of the first through hole and between the second portion and the substrate, and the first insulating adhesive layer connects the first portion and the inner wall of the first through hole and the second portion and the substrate.
5. The packaging structure according to claim 3, characterized in that: A groove is provided on the top surface of the substrate, and a bending foot is provided at the end of the second part away from the first part, and the bending foot is embedded in the groove.
6. The packaging structure according to claim 1, characterized in that: Also includes: A plastic sealing layer covering the top surface of the substrate and the bottom surface of the substrate, wherein the plastic sealing layer located on the bottom surface of the substrate has a groove exposing the bottom of the first heat dissipation frame; The heat dissipation element is located in the groove and covers the bottom of the first heat dissipation frame.
7. The packaging structure according to claim 3, characterized in that: Also includes: a second function chip, at least partially located in the first through hole, the first function chip and the second function chip are arranged in a spaced relationship along the second direction, the front surface of the first function chip faces the same direction as the top surface of the substrate, and the front surface of the second function chip faces the same direction as the bottom surface of the substrate; The first heat dissipation frames are continuously distributed on the side surface of the first function chip, on the back surface of the first function chip, on the side surface of the second function chip, and on the back surface of the second function chip.
8. The packaging structure according to claim 1, characterized in that: The substrate further has a second through hole penetrating the substrate along the first direction, the first through hole and the second through hole are arranged along a second direction, and the second direction is parallel to the top surface of the substrate; The packaging structure further includes: a second functional chip, at least partially located in the second through hole, the second functional chip being electrically connected to the substrate; The first heat dissipation frame is continuously embedded in the first through hole and the second through hole, and the first heat dissipation frame is also distributed around the side surface of the second function chip and covers the back surface of the second function chip.
9. The packaging structure according to claim 1, characterized in that: The substrate further has a second through hole penetrating the substrate along the first direction, the first through hole and the second through hole are arranged along a second direction, and the second direction is parallel to the top surface of the substrate; The packaging structure further includes: a second functional chip, at least partially located in the second through hole, the second functional chip being electrically connected to the substrate; The second heat dissipation frame is embedded in the second through hole and connected to the substrate. The second heat dissipation frame is distributed around the side of the second functional chip and covers the back of the second functional chip. The second heat dissipation frame is independent of the first heat dissipation frame.
10. The packaging structure according to claim 1, characterized in that: The substrate further has a second through hole penetrating the substrate along the first direction, the first through hole and the second through hole are arranged along a second direction, and the second direction is parallel to the top surface of the substrate; The packaging structure further includes: a second functional chip, at least partially located in the second through hole, the second functional chip being electrically connected to the substrate; A second heat dissipation frame is embedded in the second through hole and connected to the substrate. The second heat dissipation frame is distributed around the side of the second functional chip and covers the back of the second functional chip. The bottom of the first heat dissipation frame protrudes from the bottom surface of the substrate along the first direction, and the bottom of the second heat dissipation frame protrudes from the top surface of the substrate along the first direction.
11. The packaging structure according to claim 10, characterized in that: Also includes: A plastic encapsulation layer, covering the top surface of the substrate and the bottom surface of the substrate, wherein the plastic encapsulation layer encapsulates the first function chip and the second function chip; The bottom surface of the second heat dissipation frame is exposed to the top surface of the plastic packaging layer, and the bottom surface of the first heat dissipation frame is exposed to the bottom surface of the plastic packaging layer.