Conductive bump structure

Abstract

A conductive bump structure is mainly characterized in that a protective layer, an insulating layer, a metal layer and a metal bump are sequentially formed on a welding pad of a semiconductor substrate, the thickness and the width of a second block, not covered by the metal bump, of the insulating layer are respectively larger than the thickness and the width of a first block covered by the metal bump, and the metal bump is arranged on the first block. Therefore, the stress on the semiconductor substrate is reduced.

Description

Technical Field

[0001] The present application relates to a conductive bump structure, and in particular to a conductive bump structure formed on a semiconductor substrate. Background Art

[0002] Compared to the wire bonding technology, the flip chip package is characterized by the electrical connection between the semiconductor chip and the package substrate through metal bumps instead of ordinary gold wires. Using metal bumps as electrical connection elements has the advantages of shortening the electrical conduction path, improving performance, providing a heat dissipation path, and reducing the size of the package, and thus has become a trend in packaging.

[0003] However, when the semiconductor chip is hot-pressed onto the packaging substrate in a flip-chip manner through the metal bumps, the thermal stress often causes the packaging substrate to produce a downward peeling force on the metal bumps, causing the dielectric layer and / or metal layer inside the semiconductor chip to break and be damaged, seriously affecting the reliability and dependability of the package.

[0004] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content

[0005] In view of the deficiencies of the above-mentioned prior art, the present application provides a conductive bump structure, which is formed on a pad of a semiconductor substrate, and comprises: a protective layer, which is disposed on the semiconductor substrate and has an opening formed therein corresponding to the pad to expose the pad; an insulating layer, which is disposed on the protective layer corresponding to the periphery of the opening, and the insulating layer defines a first block close to the opening and a second block away from the opening, wherein the first block has a first thickness and a first width, and the second block has a second thickness and a second width, and the second thickness is greater than the first thickness, and the second width is greater than the first width; and a metal bump, which is formed on the pad and the insulating layer corresponding to the opening, wherein the metal bump covers the pad and the first block of the insulating layer, but does not cover the second block of the insulating layer.

[0006] The aforementioned conductive bump structure also includes a metal layer formed between the metal bump and the pad.

[0007] In the aforementioned conductive bump structure, the metal layer covers the pad, a portion of the protection layer and the first area of ​​the insulating layer, but does not cover the second area of ​​the insulating layer.

[0008] In the aforementioned conductive bump structure, the metal layer is an under-bump metal layer.

[0009] In the aforementioned conductive bump structure, the protection layer is a passivation layer.

[0010] In the aforementioned conductive bump structure, the insulating layer is a polyimide layer.

[0011] In the aforementioned conductive bump structure, the insulating layer is a closed annular structure.

[0012] In the aforementioned conductive bump structure, the insulating layer is a ring-shaped structure with grooves.

[0013] In the aforementioned conductive bump structure, the second thickness is at least twice the first thickness.

[0014] In the aforementioned conductive bump structure, the second width is at least twice the first width.

[0015] From the above, it can be seen that the conductive bump structure of the present application mainly forms a protective layer, an insulating layer, a metal layer and a metal bump in sequence on the solder pad of the semiconductor substrate, wherein the thickness and width of the second block of the insulating layer not covered by the metal bump are respectively greater than the thickness and width of the first block covered by the metal bump. Accordingly, the stress on the semiconductor substrate can be reduced to avoid internal damage of the semiconductor substrate during the thermal process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a cross-sectional schematic diagram of the conductive bump structure of the present application.

[0017] Figure 2 It is a partial plan view of the conductive bump structure of the present application.

[0018] Figure 3 FIG. 1 is a partial plan view of another embodiment of the conductive bump structure of the present application.

[0019] Description of Reference Numerals

[0020] 1 Conductive bump structure

[0021] 10 Semiconductor substrate

[0022] 100 Solder pad

[0023] 11. Protective layer

[0024] 110 Opening

[0025] 12 Insulation layer

[0026] 120 Slotting

[0027] 121 First Block

[0028] 122 Second Block

[0029] 13 Metal layer

[0030] 14 metal bumps

[0031] S,X thickness

[0032] M,Y width. DETAILED DESCRIPTION

[0033] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0034] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0035] See also Figure 1 and Figure 2 , which is a cross-sectional and partial plan view of the conductive bump structure of the present application.

[0036] First, a semiconductor substrate 10 having a plurality of bonding pads 100 is provided. Since the structures on the bonding pads 100 are substantially the same, only a single bonding pad 100 is shown in the drawings.

[0037] In this embodiment, the semiconductor substrate 10 is a wafer or a chip, and in other embodiments, the semiconductor substrate 10 may also be a silicon substrate or a glass substrate. The semiconductor substrate 10 is covered with a protective layer 11, and the protective layer 11 has a plurality of openings 110, so that each of the bonding pads 100 is exposed in each of the openings 110. Furthermore, the material forming the bonding pads 100 may be aluminum, and the material forming the protective layer 11 may be silicon nitride (SiN) or silicon oxide (SiOX) as a passivation layer.

[0038] In addition, an insulating layer 12 is formed on the protective layer 11 corresponding to the periphery of the opening 110 to cover the protective layer 11 around the opening 110, and the insulating layer 12 is defined with a first block 121 close to the opening 110 and a second block 122 away from the opening 110. In this embodiment, the insulating layer 12 is, for example, a polyimide layer, which is disposed on the protective layer 11 by spin coating, and then undergoes processes such as curing, exposure and development to form a closed annular structure around the opening 110, and the pad 100 is exposed.

[0039] Then, a metal layer 13 is formed on the pad 100, the protection layer 11, and the insulating layer 12 corresponding to the periphery of the opening 110, wherein the metal layer 13 covers the pad 100, a portion of the protection layer 11, and a first block 121 of the insulating layer 12, but does not cover a second block 122 of the insulating layer 12. In this embodiment, the metal layer 13 is an underbump metallization (UBM) structure, and its material can be titanium / copper (Ti / Cu) or titanium / tungsten / copper (Ti / W / Cu).

[0040] Then, a metal bump 14 is formed on the metal layer 13 to form the conductive bump structure 1 of the present application. The material of the metal bump 14 is, for example, copper.

[0041] In the present embodiment, the first block 121 of the insulating layer 12 covered by the metal bump 14 (or the metal layer 13) has a first thickness S and a first width M, and the second block 122 of the insulating layer 12 not covered by the metal bump 14 (or the metal layer 13) has a second thickness X and a second width Y, wherein the second thickness X is greater than the first thickness S, and the second width Y is greater than the first width M. For example, the second thickness X is at least twice the first thickness S, and the second width Y is at least twice the first width M. Through the above-mentioned design of the insulating layer 12, the stress on the semiconductor substrate 10 can be reduced, and the problem of fracture of the dielectric layer and / or the metal layer in the semiconductor substrate 10 during the thermal process can be avoided.

[0042] See also Figure 3 , which is a partial plan view of another embodiment of the conductive bump structure of the present application.

[0043] This embodiment is substantially the same as the above-mentioned embodiment, and the main difference is that the insulating layer 12 is formed with a plurality of grooves 120 connecting the first block 121 and the second block 122 to form a ring structure with grooves.

[0044] In summary, the conductive bump structure of the present application mainly forms a protective layer 11, an insulating layer 12, a metal layer 13 and a metal bump 14 in sequence on the pad 100 of the semiconductor substrate 10, wherein the thickness and width of the second block 122 of the insulating layer 12 not covered by the metal bump 14 are respectively greater than the thickness and width of the first block 121 covered by the metal bump 14. Accordingly, the stress on the semiconductor substrate 10 can be reduced to avoid internal damage of the semiconductor substrate 10 during the thermal process.

[0045] The above embodiments are only used to illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application should be as listed in the claims.

Claims

1. A conductive bump structure formed on a pad of a semiconductor substrate, characterized in that: include: A protective layer is disposed on the semiconductor substrate and has an opening corresponding to the soldering pad to expose the soldering pad; an insulating layer, disposed on the protective layer corresponding to the periphery of the opening, the insulating layer defining a first block close to the opening and a second block away from the opening, wherein the first block has a first thickness and a first width, the second block has a second thickness and a second width, and the second thickness is greater than the first thickness, and the second width is greater than the first width; and A metal bump is formed on the pad and the insulating layer corresponding to the opening, wherein the metal bump covers the pad and the first area of ​​the insulating layer but does not cover the second area of ​​the insulating layer.

2. The conductive bump structure according to claim 1, wherein: The structure also includes a metal layer formed between the metal bump and the pad.

3. The conductive bump structure according to claim 2, wherein: The metal layer covers the pad, a portion of the protection layer and the first area of ​​the insulating layer, but does not cover the second area of ​​the insulating layer.

4. The conductive bump structure according to claim 2, wherein: The metal layer is an under bump metal layer.

5. The conductive bump structure according to claim 1, wherein: The protective layer is a passivation layer.

6. The conductive bump structure according to claim 1, wherein: The insulating layer is a polyimide layer.

7. The conductive bump structure according to claim 1, wherein: The insulating layer is a closed annular structure.

8. The conductive bump structure according to claim 1, wherein: The insulating layer is a ring-shaped structure with grooves.

9. The conductive bump structure according to claim 1, wherein: The second thickness is at least twice the first thickness.

10. The conductive bump structure according to claim 1, wherein: The second width is at least twice the first width.

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