Silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) capable of inhibiting drain voltage overshoot
By introducing leakage suppression zone and trench gate structure in silicon carbide VDMOS, the serious problem of reverse leakage in high-voltage applications is solved, the reliability and on-resistance of the device are improved, and the effective drain suppression of silicon carbide VDMOS is achieved. The effects of voltage overshoot and reverse leakage.
Patent Information
- Application Number
- CN202421010506.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-10
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-10
AI Technical Summary
In high-voltage applications, reverse leakage is severe with the increase in voltage levels, resulting in gate reliability problems, and suppressing reverse leakage has become an urgent problem.
A silicon carbide VDMOS including a silicon carbide substrate, a drift layer, a leakage suppression region, a conductive region, a gate dielectric layer, a gate metal layer and a drain metal layer are designed. The leakage suppression region is formed of an insulating material silicon dioxide and conducts electricity. The materials of the region and gate dielectric layer are the same as the leakage suppression zone. The gate dielectric at the bottom of the trench gate directly contacts the leakage suppression zone, increasing the concentrated thickness of the electric field at the corner of the gate.
Effectively suppress drain voltage overshoot, reduce reverse leakage, reduce off-state loss, improve gate reliability, and reduce on-resistance.
Smart Images
Figure CN222282007U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a silicon carbide VDMOS capable of suppressing drain voltage overshoot. Background Art
[0002] As a representative device among silicon carbide power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. The trench gate silicon carbide VDMOS has low on-resistance, but the gate reliability has not been perfectly solved; in high-voltage applications, reverse leakage becomes more serious as the voltage level increases, and suppressing reverse leakage has become an urgent problem to be solved for ultra-high voltage transmission devices. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS that suppresses drain voltage overshoot, effectively suppresses drain voltage overshoot, and avoids the current leaked from the drain generating a large electric field on the gate of the silicon carbide VDMOS and causing failure.
[0004] The utility model is implemented as follows: a silicon carbide VDMOS for suppressing drain voltage overshoot, comprising:
[0005] Silicon carbide substrate,
[0006] a drift layer, the lower side of the drift layer being connected to the upper side of the silicon carbide substrate;
[0007] A leakage suppression region, wherein a lower side of the leakage suppression region is connected to an upper side of the drift layer;
[0008] A conductive region, wherein the conductive region passes through the leakage suppression region, and a lower side surface of the conductive region is connected to an upper side surface of the drift layer;
[0009] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the leakage suppression region, and one side of the gate dielectric layer is connected to the side of the conductive region; a groove is provided in the gate dielectric layer;
[0010] A gate metal layer, wherein the gate metal layer is disposed in the groove;
[0011] A drain metal layer, wherein the lower side of the drain metal layer is connected to the upper side of the conductive region;
[0012] and a drain metal layer connected to a lower side of the silicon carbide substrate.
[0013] The advantages of the utility model are:
[0014] 1. The device contains a leakage suppression zone inside, which can effectively suppress the voltage overshoot of the drain and prevent the current leaking from the drain from generating a large electric field on the gate of the silicon carbide VDMOS and causing failure; 2. The leakage suppression zone can effectively suppress the reverse current generated by the high voltage of the drain when the device is turned off, reduce reverse leakage, and reduce off-state loss; 3. The gate of the device adopts a trench gate, and the gate dielectric at the bottom of the trench gate is directly connected to the leakage suppression zone. The thickness of the bottom gate dielectric increases the thickness of the leakage suppression zone. The electric field concentration problem at the corner of the device gate is solved by the equivalent thicker bottom gate dielectric, which improves the reliability of the gate; 4. The source metal of the device is directly connected to the conductive area, and the on-resistance of its JFET area is smaller, which reduces the on-resistance of the device; 5. The device is turned off when the gate is a negative voltage of -10V and turned on at 0V. It is a negative voltage controlled device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0016] Figure 1 The utility model is a schematic diagram of a silicon carbide VDMOS for suppressing drain voltage overshoot.
[0017] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide VDMOS for suppressing drain voltage overshoot.
[0018] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 1 .
[0019] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 2 .
[0020] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 3 .
[0021] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 4 .
[0022] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 5 .
[0023] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 6 .
[0024] Fig. 9 This is a cross-sectional view of the process of a silicon carbide VDMOS for suppressing drain voltage overshoot according to the utility model. Figure 7 . DETAILED DESCRIPTION
[0025] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0027] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0028] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0029] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0030] like Figure 1 As shown, the embodiment of the utility model provides a silicon carbide VDMOS for suppressing drain voltage overshoot, including:
[0031] Silicon carbide substrate 1,
[0032] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;
[0033] A leakage suppression region 3, wherein the lower side of the leakage suppression region 3 is connected to the upper side of the drift layer 2;
[0034] A conductive region 4, wherein the conductive region 4 passes through the leakage suppression region 3, and a lower side of the conductive region 4 is connected to an upper side of the drift layer 2;
[0035] A gate dielectric layer 5, wherein the lower side of the gate dielectric layer 5 is connected to the upper side of the leakage suppression region 3, and one side of the gate dielectric layer 5 is connected to the side of the conductive region 4; a groove 51 is provided in the gate dielectric layer 5, and the leakage suppression region 3 and the gate dielectric layer 5 are both made of silicon dioxide;
[0036] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 51;
[0037] A drain metal layer 7, wherein the lower side of the drain metal layer 7 is connected to the upper side of the conductive region 4;
[0038] And, a drain metal layer 8, wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1, and the silicon carbide substrate 1, the drift layer 2, and the conductive region 4 are all N-type.
[0039] The leakage suppression area 3 is formed of insulating material silicon dioxide, which can effectively suppress the voltage overshoot of the drain, and prevent the current leaking from the drain from generating a large electric field on the gate of the silicon carbide VDMOS, thereby preventing failure; the leakage suppression area 3 surrounds the conductive area 4, so that when the device is turned off and subjected to the leakage voltage, the drain can only pass through the conductive area when leaking to the source, reducing the reverse leakage channel area of the device, and can effectively suppress the reverse current generated by the drain high voltage when the device is turned off, reduce reverse leakage, and reduce off-state loss;
[0040] The gate of the device adopts a trench gate, and the gate dielectric layer 5 at the bottom of the trench gate is directly connected to the leakage suppression area 3. The material of the leakage suppression area 3 is the same as that of the gate dielectric layer 5, both of which are silicon dioxide. They are directly in contact in structure. From the perspective of the thickness of the bottom gate dielectric layer 5, the thickness of the gate dielectric layer at the corner of the gate is effectively increased. The electric field concentration problem at the corner of the device gate is solved by the equivalent thicker bottom gate dielectric layer 5, which improves the reliability of the gate.
[0041] The source metal layer 7 of the device is directly connected to the conductive region 4. The conductive region 4 has a high doping concentration, which is the same as the silicon carbide substrate 1. Its resistivity is much smaller than the drift layer 2 and the traditional VDMOS inversion conductive channel, so the on-resistance of its JFET region is smaller, reducing the on-resistance of the device; the device is turned off when the gate is a negative voltage of -10V and turned on at 0V, and is a negative voltage controlled device.
[0042] like Figures 1 to 9 As shown, the method for preparing the above silicon carbide VDMOS comprises the following steps:
[0043] Step 1: depositing metal on one side of the silicon carbide substrate 1 to form a drain metal layer 8, and depositing and growing a drift layer 2 on the other side of the silicon carbide substrate 1;
[0044] Step 2, depositing a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and depositing a leakage suppression region 3 on the drift layer 2 through the through hole, wherein the leakage suppression region 3 is silicon dioxide;
[0045] Step 3, removing the original barrier layer a, and depositing to form a conductive area 4;
[0046] Step 4, forming a barrier layer a above the conductive region 4, etching the barrier layer a and the conductive region 4 to form a through hole, and performing deposition through the through hole to form a gate dielectric layer 5, wherein for the sake of simplicity of the process, the redundant conductive regions on both sides of the gate dielectric layer 5 are not processed and are not used for conduction, and the gate dielectric layer 5 is silicon dioxide;
[0047] Step 5, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, and etching the gate dielectric layer 5 to form a groove 51, and depositing metal on the groove 51 through the through hole to form a gate metal layer 6;
[0048] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, deposit metal on the through hole to form a source metal layer 7, remove the barrier layer a, and complete the manufacturing.
[0049] The silicon carbide substrate 1, the drift layer 2, and the conductive region 4 are all N-type; the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 , the doping concentration of drift layer 2 is 3e16cm -3 , the doping concentration of conductive region 4 is 2e18 cm -3 .
[0050] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A silicon carbide VDMOS for suppressing drain voltage overshoot, characterized in that: include: Silicon carbide substrate, a drift layer, the lower side of the drift layer being connected to the upper side of the silicon carbide substrate; A leakage suppression region, wherein a lower side of the leakage suppression region is connected to an upper side of the drift layer; A conductive region, wherein the conductive region passes through the leakage suppression region, and a lower side surface of the conductive region is connected to an upper side surface of the drift layer; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the leakage suppression region, and one side of the gate dielectric layer is connected to the side of the conductive region; a groove is provided in the gate dielectric layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; A drain metal layer, wherein the lower side of the drain metal layer is connected to the upper side of the conductive region; and a drain metal layer connected to a lower side of the silicon carbide substrate.
2. A silicon carbide VDMOS for suppressing drain voltage overshoot as claimed in claim 1, characterized in that: The leakage suppression region and the gate dielectric layer are both made of silicon dioxide.
3. The silicon carbide VDMOS for suppressing drain voltage overshoot according to claim 1, characterized in that: The silicon carbide substrate, drift layer and conductive region are all N-type.