Novel matrix circuit

Abstract

The utility model discloses a novel matrix circuit. The novel matrix circuit comprises a plurality of matrix signal lines, a plurality of signal isolation relay units, a plurality of data transmission buses and a plurality of matrix relay units, the plurality of matrix signal lines are in one-to-one correspondence with the plurality of signal isolation relay units; each signal isolation relay unit is connected in series with the input end of each matrix signal line; the matrix signal lines are connected with the data transmission bus through the matrix relay units. According to the scheme, when signal detection is carried out on each input end of the novel matrix circuit of the relay, crosstalk of a detection signal to other input ends is avoided, so that the detection reliability is improved.

Description

Technical Field

[0001] The embodiment of the utility model relates to the technical field of relays, and in particular to a novel matrix circuit. Background Art

[0002] At present, the new relay matrix circuit requires more input terminals and is smaller in size, so smaller relays are used. Due to the use of smaller relays, when the signal is detected at each input terminal, when the relay is turned on, the detection signal will be transmitted from the input terminal to other input terminals, thus causing signal interference problems at other input terminals. Utility Model Content

[0003] The utility model provides a novel matrix circuit, which can avoid crosstalk of detection signals on other input terminals when performing signal detection on each input terminal of the novel matrix circuit of a relay, thereby improving the reliability of detection.

[0004] To achieve the above objectives, the present invention provides a novel matrix circuit, which includes: a plurality of matrix signal lines, a plurality of signal isolation relay units, a plurality of data transmission buses, and a plurality of matrix relay units; the plurality of matrix signal lines correspond one to one with the plurality of signal isolation relay units;

[0005] Each of the signal isolation relay units is connected in series to the input end of each of the matrix signal lines; the matrix signal line is connected to the data transmission bus through each of the matrix relay units.

[0006] Optionally, each of the signal isolation relay units includes a first common terminal, a first normally open terminal, a first normally closed terminal, and a first control coil; the first common terminal and the first normally closed terminal are connected via a first wire;

[0007] Each of the first common terminals is electrically connected to an input terminal of each of the matrix signal lines; each of the first normally open terminals is suspended; each of the matrix relay units includes a second common terminal, a second normally open terminal, a second normally closed terminal, and a second control coil; the second common terminal and the second normally closed terminal are connected via a second wire;

[0008] In the extension direction of each data transmission bus, each second common terminal is electrically connected to the data transmission bus; the second normally closed terminal is left floating; the second normally open terminal of the first stage is connected to the first normally closed terminal; the second normally open terminal C5 of the Nth stage is connected to the second normally open terminal C5 of the N+1th stage; N is a positive integer ≥ 2; the first control coil is coupled to the first wire; and the second control coil is coupled to the second wire.

[0009] The distance between the first normally open end and the first common end satisfies: 2.5 mm ≤ 1 ≤ 3.5 mm; the distance between the second common end and the second normally open end satisfies: 11 ≤ 2 mm.

[0010] Optionally, the signal isolation relay unit further includes: a first freewheeling diode;

[0011] The first freewheeling diode is connected in parallel to both ends of the first control coil.

[0012] Optionally, the matrix relay unit further includes: a second freewheeling diode;

[0013] The second freewheeling diode is connected in parallel to both ends of the second control coil.

[0014] Optionally, the circuit further comprises: a relay driver chip; the relay driver chip is electrically connected to each of the signal isolation relay units;

[0015] The relay driving chip is used to output a driving signal to the corresponding signal isolation relay unit when detecting a signal on any of the matrix signal lines, so that the signal isolation relay unit switches the working state.

[0016] Optionally, the model of the relay driver chip is: TLC5927.

[0017] Optionally, the relay driver chip further includes: a filter capacitor;

[0018] The driving pin of the relay driver chip is electrically connected to the signal isolation relay unit; the power supply end of the relay driver chip is electrically connected to the first end of the filter capacitor; and the second end of the filter capacitor is electrically connected to the ground end of the relay driver chip.

[0019] In an embodiment of the present utility model, a novel matrix circuit includes multiple matrix signal lines, multiple signal isolation relay units, multiple data transmission buses and multiple matrix relay units; the multiple matrix signal lines correspond one to one to the multiple signal isolation relay units; each signal isolation relay unit is respectively connected in series to the input end of each matrix signal line; the matrix signal line is connected to the data transmission bus through each matrix relay unit, so that when the input signal of any matrix signal line is detected, each matrix relay unit is in a normally closed state, or when all are in a normally open state, the signal isolation relay unit on the corresponding matrix signal line is controlled to be in a disconnected state, thereby avoiding crosstalk of the detection signal on the signals input by other matrix signal lines, thereby improving the reliability of detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1This is a structural diagram of a matrix circuit provided in the prior art;

[0021] Figure 2 This is a schematic structural diagram of a novel matrix circuit provided by an embodiment of the present utility model;

[0022] Figure 3 This is a schematic diagram of the specific structure of a novel matrix circuit provided by an embodiment of the utility model;

[0023] Figure 4 This is a structural diagram of a signal isolation relay unit provided by an embodiment of the present utility model;

[0024] Figure 5 This is a schematic structural diagram of a matrix relay unit provided by an embodiment of the present utility model;

[0025] Figure 6 This is a schematic diagram of the specific structure of a novel matrix circuit provided by an embodiment of the utility model;

[0026] Figure 7 This is a schematic diagram of the specific structure of a novel matrix circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all of its components.

[0028] Figure 1 It is a structural diagram of a matrix circuit in the prior art; Figure 1 As shown, the matrix circuit includes multiple matrix signal lines P1, multiple data transmission buses P2, and multiple matrix relay units K. The matrix signal line P1 is connected to the data transmission bus P2 via each matrix relay unit K. When detecting the input signal of any of the multiple matrix signal lines P1, the matrix relay unit K is in a normally closed state in the novel matrix circuit. The detection signal will crosstalk to other matrix signal lines P1 through any data transmission bus P2, thereby affecting the signals input to other matrix signal lines P1, thus causing signal interference. Even when the matrix relay unit K is in an open state, since the matrix relay unit K does not provide signal isolation, the detection signal will crosstalk to other matrix signal lines P1 through any data transmission bus P2, thereby affecting the signals input to other matrix signal lines P1, thus causing signal interference.

[0029] In order to solve the above problems, the utility model provides a new matrix circuit. Figure 2 Schematic diagram of a novel matrix circuit provided by an embodiment of the present utility model; Figure 2 As shown, the circuit includes: multiple matrix signal lines P1, multiple signal isolation relay units Q, multiple data transmission buses P2 and multiple matrix relay units K; the multiple matrix signal lines P1 correspond to the multiple signal isolation relay units Q one by one; each signal isolation relay unit Q is connected in series to the input end of each matrix signal line P1; the matrix signal line P1 is connected to the data transmission bus P2 through each matrix relay unit K.

[0030] In particular, each signal isolation relay unit Q is connected in series to the input end of each matrix signal line P1. When detecting the input signal of any matrix signal line P1, each matrix relay unit K is in a normally closed state, or when all are in a normally open state, the signal isolation relay unit Q on the corresponding matrix signal line P1 is controlled to be in an open state. Since the signal isolation relay unit Q in the open state can effectively perform signal isolation, it prevents the detection signal from crosstalking with other matrix signal lines P1 through any data transmission bus, thereby ensuring the reliability of detection. In this embodiment, when the signal isolation relay unit Q is in the open state, it can completely shield the detection signal.

[0031] Optionally, based on the above embodiment, further refinement is performed. Figure 3 Schematic diagram of a novel matrix circuit provided by the embodiment of the present utility model; Figure 3 As shown, each signal isolation relay unit Q includes a first common terminal C1, a first normally open terminal C2, a first normally closed terminal C3 and a first control coil Q1; the first common terminal C1 and the first normally closed terminal C3 are connected by a first wire;

[0032] Each first common terminal C1 is electrically connected to the input terminal of each matrix signal line P1; each first normally open terminal C2 is left floating; each matrix relay unit K includes a second common terminal C4, a second normally open terminal C5, a second normally closed terminal C6, and a second control coil K1; the second common terminal C4 and the second normally closed terminal C6 are connected via a second wire;

[0033] In the extension direction of each data transmission bus P2, each second common terminal C4 is electrically connected to the data transmission bus P2; the second normally closed terminal C6 is left floating; the first-stage second normally open terminal C5 is connected to the first normally closed terminal C3; the N-stage second normally open terminal C5 is connected to the N+1-stage second normally open terminal C5; N is a positive integer ≥ 2; the first control coil Q1 is coupled to the first conductive wire; and the second control coil K1 is coupled to the second conductive wire.

[0034] Among them, the distance between the first normally open end of the signal isolation relay unit Q and the first common end of the signal isolation relay unit Q satisfies: 2.5mm≤l≤3.5mm; the distance between the second common end of the matrix relay unit K and the second normally open end of the matrix relay unit satisfies: l≤2mm.

[0035] When the input signal of any matrix signal line P1 is detected, each matrix relay unit K is in a normally closed state, that is, the second control coil K1 outputs a control signal, the second common terminal C4 of each matrix relay unit K is connected to the second normally closed terminal C6, and the second normally open terminal C5 is in a floating state; or each matrix relay unit K is in a normally open state, that is, the second control coil K1 outputs a control signal, the second common terminal C4 of each matrix relay unit K is connected to the second normally open terminal C5, and the second normally closed terminal C6 is in a floating state;

[0036] And control the signal isolation relay unit Q on the corresponding matrix signal line P1 to be in a disconnected state, that is, output a control signal to the first control coil Q1, so that the first common terminal C1 and the first normally closed terminal C3 are in a disconnected state, and the first common terminal C1 and the first normally open terminal C2 are connected through a first wire. Since the distance between the first normally open terminal C2 of the signal isolation relay unit Q and the first common terminal C1 of the signal isolation relay unit Q meets the following requirements: 2.5mm≤l1≤3.5mm, compared with the distance between the second common terminal of the matrix relay unit K and the second normally open terminal of the matrix relay unit meeting the following requirements: l≤2mm, the distance between the first normally open terminal C2 of the signal isolation relay unit Q and the first common terminal C1 of the signal isolation relay unit Q is larger, thereby avoiding crosstalk of the detection signal to other matrix signal lines P1 through any data transmission bus, thereby ensuring the reliability of the detection.

[0037] Optional, Figure 4 Schematic diagram of the structure of the signal isolation relay unit provided by the embodiment of the present invention; Figure 4 As shown, the signal isolation relay unit Q also includes a first freewheeling diode D1 connected in parallel across the first control coil Q1. When the signal isolation relay unit Q is in the disconnected state, i.e., the first common terminal C1 and the first normally closed terminal C3 are disconnected, and the first common terminal C1 and the first normally open terminal C2 are connected via a first wire, the first freewheeling diode D1 can function as a freewheeling diode.

[0038] Optional, Figure 5 This is a schematic diagram of the structure of the matrix relay unit provided by the embodiment of the present utility model; Figure 5The matrix relay unit K also includes a second freewheeling diode D2 connected in parallel across the second control coil K1. If, under certain circumstances, the matrix relay unit K needs to be disconnected, a control signal is output to the second control coil K1, disconnecting the second common terminal C4 from the second normally closed terminal C6. The second common terminal C4 is connected to the second normally open terminal C5 via a second wire, allowing the second freewheeling diode D2 to provide freewheeling current.

[0039] Optional, Figure 6 Schematic diagram of a novel matrix circuit provided by the embodiment of the present utility model; Figure 6 As shown, the new matrix circuit also includes: a relay driver chip U1; the relay driver chip U1 is electrically connected to each signal isolation relay unit Q; the relay driver chip U1 is used to output a drive signal to the corresponding signal isolation relay unit Q when detecting a signal on any matrix signal line, so that the signal isolation relay unit Q switches the working state.

[0040] Among them, the model of the relay driver chip U1 is TLC5927; when detecting the signal on any matrix signal line, the drive signal is output to the corresponding signal isolation relay unit Q to switch the signal isolation relay unit from the normally closed state to the open state, thereby avoiding the detection signal from being crosstalked to other matrix signal lines P1 through any data transmission bus, thereby ensuring the reliability of the detection.

[0041] Optional, Figure 7 Schematic diagram of a novel matrix circuit provided by the embodiment of the present utility model; Figure 7 As shown, relay driver chip U1 also includes a filter capacitor C1; a drive pin of relay driver chip U1 is electrically connected to signal isolation relay unit Q; a power supply terminal of the relay driver chip is electrically connected to a first terminal of filter capacitor C1; and a second terminal of filter capacitor C1 is electrically connected to a ground terminal of the relay driver chip. Filter capacitor C1 provides filtering, thereby improving the reliability of the drive signal output by relay driver chip U1.

[0042] Note that the above are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present invention. Therefore, while the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A novel matrix circuit, characterized in that: include: A plurality of matrix signal lines, a plurality of signal isolation relay units, a plurality of data transmission buses and a plurality of matrix relay units; The plurality of matrix signal lines correspond one to one with the plurality of signal isolation relay units; Each of the signal isolation relay units is connected in series to the input end of each of the matrix signal lines; the matrix signal line is connected to the data transmission bus through each of the matrix relay units.

2. The novel matrix circuit according to claim 1 is characterized in that: Each of the signal isolation relay units comprises a first common terminal, a first normally open terminal, a first normally closed terminal and a first control coil; the first common terminal and the first normally closed terminal are connected via a first wire; Each of the first common terminals is electrically connected to the input terminal of each of the matrix signal lines; each of the first normally open terminals is suspended; each of the matrix relay units includes a second common terminal, a second normally open terminal, a second normally closed terminal and a second control coil; the second common terminal is connected to the second normally closed terminal via a second wire; In the extension direction of each of the data transmission buses, each of the second common terminals is electrically connected to the data transmission bus; the second normally closed terminal is suspended; the first-stage second normally open terminal is connected to the first normally closed terminal; the N-stage second normally open terminal C5 is connected to the N+1-stage second normally open terminal C5; N is a positive integer ≥ 2; the first control coil is coupled to the first wire; the second control coil is coupled to the second wire; Among them, the distance between the first normally open end and the first common end satisfies: 2.5mm≤1≤3.5mm; the distance between the second common end and the second normally open end satisfies: 1≤2mm.

3. The novel matrix circuit according to claim 2 is characterized in that: The signal isolation relay unit further includes: a first freewheeling diode; The first freewheeling diode is connected in parallel to two ends of the first control coil.

4. The novel matrix circuit according to claim 2 is characterized in that: The matrix relay unit further comprises: a second freewheeling diode; The second freewheeling diode is connected in parallel to two ends of the second control coil.

5. The novel matrix circuit according to claim 1 is characterized in that: Also includes: Relay driver chip; The relay driving chip is electrically connected to each of the signal isolation relay units; The relay driving chip is used to output a driving signal to the corresponding signal isolation relay unit when detecting a signal on any of the matrix signal lines so that the signal isolation relay unit switches the working state.

6. The novel matrix circuit according to claim 5 is characterized in that: The model of the relay driver chip is: TLC5927.

7. The novel matrix circuit according to claim 6 is characterized in that: The relay driver chip further includes: a filter capacitor; The driving pin of the relay driving chip is electrically connected to the signal isolation relay unit; the power supply end of the relay driving chip is electrically connected to the first end of the filter capacitor; the second end of the filter capacitor is electrically connected to the ground end of the relay driving chip.

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