Electronic device

Abstract

The embodiment of the utility model relates to an electronic device. In one embodiment, an electronic device includes an insulating encapsulant encapsulating a semiconductor die having an integrated Hall current sensor configured to measure a current flowing near an active surface of the semiconductor die. The conductive traces are embedded in the insulating encapsulant. A first conductive feature extends through the insulative encapsulant toward an opposite end of the conductive trace. The first conductive configuration is configured to flow a current subjected to measurement in a current flow path through the conductive trace. A second conductive feature extends through the insulating encapsulant toward the active surface of the semiconductor die. The second conductive configuration is configured to activate a Hall current sensor integrated in the semiconductor die.

Description

Technical Field

[0001] This description relates to semiconductor devices.

[0002] The solutions described herein may be applied to Hall effect based current sensor integrated circuit (IC) semiconductor devices for applications in, for example, automotive or industrial products. Background Art

[0003] One class of sensors for measuring electric current is based on the well-known Hall effect.

[0004] For low current applications, e.g. up to 50A, traditionally, Hall sensors are assembled in a package that is mounted (e.g. via surface mount technology (SMT)) on a substrate such as a printed circuit board (PCB) that includes conductive strips or traces that provide a current flow path for the current to be measured flowing beneath the package (i.e. outside the enclosure).

[0005] The magnetic field generated by the conductive strip is measured by a sensor arranged near the conductive strip.

[0006] The sensitivity of such devices is relatively low, and the measurements can be affected by noise. This results in poor sensor accuracy.

[0007] To improve the accuracy of the current sensor, a leadframe based package may be used where the leadframe is designed so that the current to be measured is redirected from the PCB via the leadframe leads and flows directly beneath the IC sensor.

[0008] Such devices involve complex assembly techniques, and the active portion of the sensor is still relatively far away from the conductive strips or traces through which the current flows, so sensor accuracy is difficult to improve.

[0009] By way of background, reference is made to US Pat. No. 11,422,164 or 6,812,687 as examples of various advances in providing current measurement devices with improved accuracy.

[0010] There is a need in the art for solutions directed to addressing the problems discussed above. Utility Model Content

[0011] According to one or more aspects of the present disclosure, there is provided an electronic device, comprising: an insulating encapsulant encapsulating a semiconductor die, wherein a Hall current sensor is integrated in the semiconductor die, the Hall current sensor being configured to measure a current flowing near an active surface of the semiconductor die; a conductive trace embedded in the insulating encapsulant, the conductive trace having opposite ends, a current flow path adjacent to the active surface of the semiconductor die being provided between the opposite ends; a first conductive structure passing through the insulating encapsulant toward the opposite ends of the conductive trace embedded in the insulating encapsulant, the first conductive structure being configured to cause a current to be measured to flow in a current flow path adjacent to the active surface of the semiconductor die; and a second conductive structure passing through the insulating encapsulant toward the active surface of the semiconductor die, the second conductive structure being configured to activate the Hall current sensor integrated in the semiconductor die.

[0012] In one or more embodiments, the electronic device further includes an insulating film laminated on the active surface of the semiconductor die, wherein the second conductive configuration includes a conductive feature at a via opened through the insulating film.

[0013] In one or more embodiments, the conductive trace embedded in the insulating encapsulation has a ring shape.

[0014] In one or more embodiments, the conductive trace embedded in the insulating encapsulation has a plate shape.

[0015] In one or more embodiments, wherein the conductive trace embedded in the insulating encapsulant has a middle portion located between opposite ends, and wherein the middle portion is wider than the opposite ends.

[0016] In one or more embodiments, wherein the conductive trace embedded in the insulating encapsulant has a middle portion between opposite ends, and wherein an aperture is disposed in the middle portion.

[0017] In one or more embodiments, the insulating encapsulant includes: an insulating film layer on an active surface of a semiconductor die; a first body of an encapsulation component encapsulating the semiconductor die, wherein a front surface of the body is coplanar with a front surface of the insulating film layer; a second body of the encapsulation component covering the first body and the insulating film layer; wherein a portion of the second conductive structure is positioned between the second body and the insulating film layer and extends through a via opening in the second body and the insulating film layer; and a third body of the encapsulation component covering the second body; wherein the conductive trace is positioned between the third body and the second body. wherein a portion of the first conductive structure extends through the third body; and wherein other portions of the second conductive structure extend through the third body.

[0018] In one or more embodiments, the electronic device in the package does not utilize a metal lead frame.

[0019] In one or more embodiments, the electronic device also includes: a current undergoing measurement applied across a first conductive structure, wherein the current undergoing measurement flows in a current flow path adjacent to an active surface of the semiconductor die; and a signal applied to a second conductive structure of a Hall current sensor integrated in the semiconductor die, wherein the signal is configured to activate the Hall current sensor to measure the current flowing in the current flow path adjacent to the active surface of the semiconductor die.

[0020] The solution described in this article proposes a simple, flexible and cost-effective method to manufacture Hall effect based current sensor semiconductor devices with improved accuracy and sensitivity.

[0021] In the solutions described herein, the manufacturing process can be performed at the wafer or panel level to facilitate concurrent processing of multiple devices.

[0022] In the solution described herein, conductive traces configured to carry the current to be measured are embedded in the package and extend close to the sensor die.

[0023] In the solution described herein, the shape of the conductive traces can be designed to increase / decrease the strength of the magnetic field generated by the current and measured by the Hall sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0025] Figures 1A to 1K is an example of a possible series of steps to implement an embodiment of the present description; and

[0026] Figures 2 to 5 is a plan view of a structure of a semiconductor device according to an embodiment of the present specification, illustrating Figures 1A to 1K The results of the individual steps in the order. DETAILED DESCRIPTION

[0027] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0028] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0029] The edges of a feature drawn in a diagram do not necessarily indicate the end of the feature's extent.

[0030] In the following description, one or more specific details are illustrated to provide a deeper understanding of the examples of embodiments of the present specification. Embodiments may be obtained without one or more specific details or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments will not be obscured.

[0031] Reference to "an embodiment" or "one embodiment" in the framework of this specification is intended to indicate that a particular configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to one and the same embodiment.

[0032] Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0033] The headings / reference numbers used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0034] For simplicity and ease of explanation, throughout the description, and unless the context indicates otherwise, the same parts or elements are indicated by the same reference numerals in the various figures, and the corresponding description will not be repeated for each figure.

[0035] One class of integrated circuit (IC) sensors for measuring current flow is based on the Hall effect. As known to those skilled in the art, these sensors are based on the principle of measuring the voltage induced (in the conductive part of the sensor) in response to the magnetic field generated by the current to be measured.

[0036] Conventional Hall sensors are mounted (eg, via surface mount technology (SMT)) on a substrate such as a printed circuit board (PCB) over a conductive trace or strip that carries the current to be measured.

[0037] In this package design, the conductive strips / traces are located outside the sensor package and relatively far away from the sensor.

[0038] This traditional method has been found to have low accuracy and the measurement results are strongly affected by noise. In fact, substrates such as PCBs may host a large number of current-carrying traces, which may adversely affect the measurement process.

[0039] To improve the accuracy of such Hall sensors, a lead frame based package can be used to redirect the current to be measured from the PCB strip into the package.

[0040] Such conventional lead frame based packages may cause various problems.

[0041] For example: each device design may involve a corresponding lead frame design; the assembly process may involve some steps, such as wire bonding, which may be overly complex; and processes such as wire bonding may degrade the electrical performance of the device (eg, have high electrical losses).

[0042] Furthermore, in such conventional devices, the conductor carrying the current to be measured is still relatively far from the sensor, which negatively affects accuracy.

[0043] The solution described herein proposes a simple, flexible and cost-effective method to manufacture a current sensor (integrated circuit IC) semiconductor device with improved accuracy.

[0044] In the solution described herein, conductive traces configured to carry the current to be measured are embedded in the package and extend close to the sensor die.

[0045] In the solution described herein, the shape of the conductive traces can be designed to increase / decrease the strength of the magnetic field generated by the current and measured by the Hall sensor.

[0046] Figures 1A to 1K A series of steps of a method for manufacturing a current sensor (integrated circuit) semiconductor device based on the Hall effect are illustrated.

[0047] It should be noted that Figures 1A to 1K The series of steps is exemplary only because: Figures 1A to 1K One or more of the steps illustrated may be omitted, performed in a different manner (e.g., using other tools), and / or replaced by other steps; additional steps may be added; and one or more steps may be performed in an order different from that illustrated.

[0048] Figures 1A to 1C The diagram illustrates processing steps that may be performed at the wafer level, thereby facilitating concurrent processing of multiple semiconductor devices.

[0049] Figure 1A There is shown a semiconductor (eg silicon) wafer 140 provided with an insulating film 18 laminated on its active surface.

[0050] The semiconductor wafer 140 includes an integrated circuit (IC), such as a Hall sensor (HS) chip or die, that has been formed therein in any manner known in the art.

[0051] As used throughout this specification, the terms "chip" and "die" are considered synonymous.

[0052] The insulating film 18 may be, for example, an Ajinomoto deposited film (ABF) available from Ajinomoto Fine-Techno Co., Inc., 1-2 Suzuki-cho, Kawasaki-ku, Kawasaki-shi, 210-0801, Japan.

[0053] Membrane 18 may be laminated onto the first (active) surface of wafer 14 and may vary in thickness depending on the design of the device; for example, as will be discussed below, the thickness of membrane 18 may be used to control the distance between Hall sensor HS (formed in wafer 140) and a conductive trace carrying the current to be measured.

[0054] Figure 1B A via 181 ′ (eg, via laser beam LB) is shown opening to a die pad (not visible in the figure due to scale reasons) on an active surface of a die / chip included in the wafer 140 .

[0055] like Figure 1C , the semiconductor wafer 140 can thus be cut (or "singulated") into individual dies or chips 14, in which the IC Hall sensors HS are formed. As shown, singulation can be performed via a blade or saw B, for example.

[0056] Before singulation, a grinding step may be performed in order to reduce as much as possible the thickness of the semiconductor wafer 140. For the sake of simplicity, this step is not visible in the figure.

[0057] like Figure 1D As shown in , the singulated die / chips 14 may be flipped upside down and arranged on a carrier (eg, tape) C1 for further processing, possibly with a release tape T1 laminated on the carrier C1 to facilitate releasing the device from the carrier C1 after processing.

[0058] By arranging and mounting a plurality of semiconductor devices in a flipped orientation on such a carrier C1 , simultaneous processing of the plurality of semiconductor devices is facilitated.

[0059] Processing using a panel-shaped or wafer-shaped carrier is generally referred to as wafer / panel-level packaging, the main difference being the shape of the carrier. The processing steps described below can be performed (in a manner known per se to a person skilled in the art) regardless of the shape of the carrier C1 and are therefore applicable to both wafer-level packaging and panel-level packaging.

[0060] Figure 1DIllustrated is the fact that the dies 14 may be “flipped” (ie turned upside down) so that their active surfaces, on which the film 18 is laminated, face the tape T1 and the carrier C1 and are arranged on the carrier C1 in such a way that there is some spacing between them.

[0061] Figure 1E A first molding step is illustrated, wherein an electrically insulating molding compound 20 , such as, for example, epoxy resin, is molded onto the die 14 arranged on the tape T1 in order to form a first part of an encapsulation body protecting and insulating the die 14 .

[0062] like Figure 1E and Figure 1F As shown in FIG. 1 , the dies 14 having the molding compound 20 molded on their back or bottom surfaces are detached from the (first) carrier C1 (which is facilitated by the peeling tape T) and arranged on the second carrier C2 with their active surfaces facing upwards, as shown in FIG. Figure 1F , in order to facilitate further processing. The second carrier C2 may also have a release tape T2 laminated thereon.

[0063] The different names used for the carriers C1 , C2 and the release tapes T1 , T2 are mainly for convenience of explanation: in fact, the same (types of) carriers and release tapes can be used in both examples.

[0064] Figure 1G A metallic material such as, for example, copper is shown grown / deposited on the active surface of die 14 .

[0065] Vias 181 (located in via openings 181 ′) and traces 182 are formed on the active surface of die 14 to provide input / output electrical coupling to the die.

[0066] like Figure 1G As shown in FIG. 1 , vias 181 are filled with conductive material (thus, they are no longer used to bond Figure 1B The die 14 is referenced by the reference numeral 181' introduced therein) and provides electrical coupling between traces 182 at the active surface of the component (here the front or top surface) and a die pad on the active surface of the die 14 (not visible in the figure for reasons of scale).

[0067] like Figure 1G The growing metal material illustrated in FIG. 1 may be performed in any manner known in the art.

[0068] For example, photolithography processes known in the art may be used to grow vias 181 and traces 182, as illustrated.

[0069] Such a lithography process may involve: depositing a seed layer (comprising, for example, a Ti layer followed by a Cu layer) via sputtering, for example, to facilitate subsequent electroplating / galvanic growth of a metal material (such as copper); providing a photoresist material on the seed layer, such as a dry photoresist film laminated on the previously deposited seed layer; exposing the dry film to (e.g., UV) light, and developing the dry film to transfer a desired pattern to the photoresist film, for example, via laser direct imaging (LDI); growing a metal material having a desired pattern via an electroplating / electrodeposition process to form conductive vias 181 and traces 182; and stripping the dry film and etching away the seed layer (where it is not covered by the metal material of the vias 181 and traces 182) to obtain Figure 1G Components shown in FIG.

[0070] This photolithography process itself is conventional in the art, which makes it unnecessary to provide a more detailed description.

[0071] Various techniques may be used to deposit the metal material to form the vias 181 and the traces 182. For example, the vias 181 and the traces 182 may be formed using laser induced forward transfer (LIFT).

[0072] LIFT designates a deposition process in which material is transferred from a donor tape or sheet to a receptor substrate by laser pulses.

[0073] General information about the LIFT process can be found, for example, in the article by P. Serra et al.: “Laser-Induced Forward Transfer: Fundamentals and Applications”, Advanced Materials Technologies / Vol. 4, No. 1 (incorporated herein by reference).

[0074] Figure 1H The diagram shows the deposition Figure 1G An additional layer of metal material (e.g., such as copper) is formed on the component to form input / output (I / O) pads 120 and (main) traces 100. Figure 1H The provision of the pads 120 and traces 100 as shown in FIG. 1 may involve the following steps: a molding step in which an additional molding compound 20′ is molded onto the Figure 1G ; providing (through-mold) vias to previously formed traces 182; and growing / depositing metal material (e.g., copper) to form pads 120 and main traces 100 in any manner known in the art (e.g., photolithography or LIFT as previously discussed).

[0075] The main trace 100 is a conductive structure that carries the current to be measured by the IC Hall sensor HS. As will be discussed below, the shape of the main trace 100 can play a role in determining the size / strength of the magnetic field generated by the current flowing in the main trace 100.

[0076] Regardless of the specific shape, in the exemplary case where photolithography is used to grow the main trace 100, the main trace 100 may be formed by deposition / growth as previously described, for example by varying a pattern transferred to a photoresist film.

[0077] Fig. 1I Illustrated are deposition steps that form studs 121 for I / O pads 120 and studs 101 for main traces 100. Again, the deposition / growth steps may be performed via any technique known in the art, such as photolithography or LIFT, for example.

[0078] When describing a device that can be obtained using the method described herein according to an embodiment of the present specification, Fig. 1I The schematic representation, in particular the shape of the main trace 100 and the position of the main trace studs 101, should not be interpreted in a limiting sense; the shape of the main trace will be described in more detail below.

[0079] Figure 1J A further molding step is shown in which a molding compound 20" (e.g., epoxy resin) is molded into the Fig. 1I , thereby completing the protective plastic package (encapsulant) of the device.

[0080] As described herein, the plastic package (i.e., encapsulant) is molded in three steps (i.e., Figure 1E , Figure 1H and Figure 1J ), resulting in the molding of three encapsulation / body / layers 20, 20' and 20". However, different sequences of steps may be envisioned to provide such a protective plastic package for the device.

[0081] Note also that traces 182 may be implemented (in a manner known to those skilled in the art) to provide multiple redistribution layers.

[0082] However, the plastic package as illustrated herein has the main trace 100 completely embedded therein. That is, the main trace 100 carrying the current to be measured is located inside the package of the device.

[0083] Figure 1K The final singulation step is illustrated, wherein the panel (or wafer) is singulated into final individual devices 10 .

[0084] After peeling of the panel / wafer from the carrier C (facilitated by the peeling tape T), a singulation step may be performed via dicing or sawing with a blade B.

[0085] May be in Figure 1K Optional processing steps performed before the final singulation step illustrated in FIG. 1 may include a grinding step for forming a flatter surface of the device; an electroplating step for forming a solderable conductive layer on the outer surface of the studs 101 , 121 ; and a laser marking step for identifying the device.

[0086] Figures 1A to 1K A description of an exemplary method for manufacturing a Hall current sensor (IC) semiconductor device is given in the order and related discussion.

[0087] As described herein, such a method involves encapsulating the semiconductor die 14 (eg, via several molding steps) in an insulating encapsulant 20 , 20 ′, 20 ″.

[0088] The semiconductor die 14 has integrated therein a Hall current sensor HS configured to measure a current I flowing near an active surface of the semiconductor die 14 .

[0089] Conductive (main) trace 100 is formed embedded in insulating encapsulant 20 , 20 ′, 20 ″. Conductive trace 100 has opposing ends between which a current flow path is provided adjacent to an active surface of semiconductor die 14 .

[0090] First (stud 101 ) and second (via 181 , trace 182 and external pads 120 , 121 ) conductive structures are provided through the insulating encapsulation 20 , 20 ′, 20 ″ (eg, via photolithography or LIFT).

[0091] First conductive construction 101 is coupled to opposite ends of conductive trace 100 and is configured to cause a current under measurement to flow through a current flow path adjacent to an active surface of semiconductor die 14 .

[0092] The second conductive structures 181 , 182 , 120 , 121 are directed toward an active surface of the semiconductor die 14 and are configured to activate (eg, transmit I / O signals and provide power) the Hall current sensor HS integrated in the semiconductor die 14 .

[0093] Advantageously, an insulating film 18 , such as an Ajinomoto deposited film, may be laminated on the active surface of semiconductor die 14 .

[0094] In this case, via 181 ′ is opened through insulating film 18 (via laser beam LB), and (a portion of) second conductive construction 181 facing the active surface of semiconductor die 14 comprises conductive material at via 181 ′ opened through insulating film 18 .

[0095] As mentioned, Figures 1A to 1K The series of steps are merely exemplary, and one or more steps illustrated in the figure may be omitted, performed in a different manner, additional steps may be added, and one or more steps may be performed in an order different from that illustrated.

[0096] It will be appreciated that the assembly flow described thus far may be performed at wafer or panel level (ie regardless of the shape of the carrier), thereby facilitating concurrent processing of (large numbers of) devices 10 , thereby providing a time-efficient and cost-effective manufacturing method.

[0097] Furthermore, the assembly flow described herein does not involve providing a substrate (eg, a conductive substrate such as a lead frame) to be designed for a specific device design, thereby further reducing design and manufacturing costs.

[0098] Furthermore, electrical coupling is provided via direct interconnects (i.e., vias 181, 120, traces 100, 182 and studs 101, 121), commonly referred to as direct copper interconnects (DCI) due to the widespread (but still not mandatory) use of copper to form such interconnects, rather than using (conductive) wires, which would degrade electrical performance and make the assembly process more complicated (e.g. involving a wire bonding formation step).

[0099] like Figure 1K The device 10 illustrated in FIG. 1 is intended to be mounted (eg, soldered) on a final substrate such as a printed circuit board (PCB).

[0100] Pads 121 , 120 (and corresponding electrical structures 182 , 181 ) may be used to power device 10 and provide I / O signals thereto.

[0101] The studs 101 provide electrical coupling between the traces / strips in the PCB carrying the current to be measured and the main traces 100 inside the package of the device 10 .

[0102] Note that the structure of device 10 using various encapsulating bodies / volumes / layers around and over the die enables the production of packaged IC devices that do not require or utilize metal leadframe structures. Specifically, there is no die pad of a metal leadframe to support die 14.

[0103] The current flowing in the main trace 100 generates a magnetic field that is measured by the sensor die 14. Such a sensor die 14 has an active portion that is configured to measure the magnetic field by measuring a voltage induced therein via the Hall effect. Such an IC sensor die 14 is itself conventional in the art, making it unnecessary to provide a more detailed description herein.

[0104] In addition to the current strength that generates the magnetic field, the magnetic field strength at the active part of the sensor chip 14 can also depend on the shape of the main trace 100 carrying the current, on the distance between the main trace 100 and the active part of the sensor tube core 14, and on the magnetic properties of (multiple) materials in between.

[0105] The distance between the main trace 100 and the active part of the IC Hall sensor die 14 can be controlled, for example, by varying the thickness of the film 18; in fact, insulating films with different thicknesses (such as the already mentioned ABF) are commercially available.

[0106] The thickness of the mold compound 20 layer between the main trace 100 and the insulating film 18 (in Figure 1H ) may also be varied (at least within certain limits) in order to fine tune the strength of the magnetic field at the active portion of the sensor die 14 .

[0107] Varying the strength of the magnetic field at the active portion of sensor die 14 (for the same current strength) (by “tuning” the features listed above) may advantageously improve the performance and flexibility of device 10 .

[0108] For example, the strength of the magnetic field may be increased / maximized by reducing the distance between the main trace 100 and the sensor die 14 in order to increase the signal-to-noise ratio and thus improve the accuracy of the measurement device 10 .

[0109] In fact, as mentioned, actual PCBs may be "overcrowded" with multiple current carrying lines / traces near the sensor device, which may negatively affect measurement accuracy; by increasing the magnetic field at the active part of the sensor die 14, the signal-to-noise ratio increases and measurement accuracy improves.

[0110] On the other hand, one may also be interested in reducing the strength of the magnetic field at the sensor die 14 by increasing the distance between the main trace 100 and the sensor die 14. For example, when it is desired to measure a relatively high intensity current, the reduction of the magnetic field at the sensor die 14 facilitates the use of a sensor die 14 configured for smaller currents, i.e., a smaller scale measurement device.

[0111] As mentioned, the shape of the main trace 100 may also play a role in determining the magnetic field strength at (the active portion of) the sensor die 14 .

[0112] In the following, devices having main traces 100 of different shapes will be described.

[0113] As can be understood by those skilled in the art, Figures 1A to 1K The same processing steps described in the order are used to obtain the various embodiments presented below.

[0114] For example, Figures 2 to 4 The different shapes of the main traces 100 shown in FIG. 1 can be used as discussed above and Figure 1K The EMBODIMENT 2 may be formed by a similar growth / deposition process (eg, photolithography or LIFT) as schematically illustrated in FIG.

[0115] Figure 2 is a plan view illustrating the bottom of a device 10 that can be obtained according to an embodiment of the present description.

[0116] As used herein, the term "bottom" refers to the side of the device 10 having the studs 101, 121 protruding therefrom, or in other words, the side of the device 10 that faces the final substrate (e.g., PCB) when mounted (e.g., soldered) thereon.

[0117] exist Figure 2 (and subsequent Figure 3 , Figure 4 and Figure 5 ), in order to clearly illustrate the details of the structure of device 10, the outermost molding compound layers 20' and 20". Only the "background" layer 20 is shown in these figures (e.g., Figure 1E ) is formed in the processing steps illustrated in FIG.

[0118] External pads 120 , 121 for I / O signals or power supply of device 10 are arranged at the periphery of device 10 and are electrically coupled to sensor die 14 via conductive traces 182 .

[0119] Thus, the conductive trace 182 couples the external pads 120, 121 to the die pad provided on the active surface of the die 14 via the via 181 opened in the insulating film 18 laminated on the active surface of the die 14 (and, for example, filled with a metal material such as copper). Due to proportional reasons, the via 181 and the die pad are located at the same level. Figure 2 Not visible in.

[0120] Figure 2 In (and Figure 3 , Figure 4 and Figure 5The number of external pads 120, 121, their positions, and the pattern of traces 182 illustrated in the figure are merely exemplary and should not be interpreted in a limiting sense. Different numbers and / or different arrangements of external pads 120, 121 may be envisioned depending on the specific design of the device 10. Accordingly, the conductive traces 182 may be provided with different patterns.

[0121] like Figure 2 As illustrated in , the device 10 may be provided with a main trace 100 in a ring shape configured to carry a current to be measured.

[0122] The studs 101 are provided to electrically couple conductive strips or traces provided on a final substrate (eg, a PCB) on which the device 10 is intended to be mounted to the main traces 100 of the device 10 embedded in the encapsulating mold compound 20 .

[0123] Strips or traces on the substrate carry the current to be measured.

[0124] The current is then redirected into the main trace 100 of the device 10 (eg, via the stud 101 illustrated on the left).

[0125] Therefore, current flows in the main trace 100 of the device 10. The current flow is given by Figure 2 It is indicated by the arrow in and is referenced therein by the reference symbol I.

[0126] The current eventually "returns" to a trace or strip in a substrate (eg, a PCB) via a stud 101 (eg, the stud 101 on the right).

[0127] As illustrated, the sensor die 14 may be arranged at the center of the annular shaped main trace 100 , in a plane parallel to one of the main traces 100 , and at a distance therefrom.

[0128] As mentioned, the distance between the two planes (ie, the plane of the sensor die 14 and the plane of the main trace 100) can be varied by varying the thickness of the insulating film 18 (eg, Ajinomoto buildup film) and the thickness of the molding compound layer therebetween, as previously discussed.

[0129] The current I flowing in the main trace 100 (at the active portion of the sensor die 14) generates a magnetic field having a strength that is measured by the sensor die 14 (e.g., via an induced Hall voltage). In the following it will be assumed that the magnetic field strength at point O of the sensor die 14 is the relevant quantity measured by the sensor die 14. As illustrated in the figure, point O is located at the center of the sensor die 14, but the exact location will depend on the actual design of the sensor die 14, the details of which are not of interest here, and point O will be assumed to be included in the active portion of the sensor die 14.

[0130] As discussed, the magnetic field strength at point O of the sensor die 14 may depend on: the strength of the current I to be measured; and the distance between the sensor die 14 and the main trace 100; the magnetic properties of the material between the sensor die 14 and the main trace 100; and the geometry of the main trace 100. Figure 2 The main trace 100 is in a ring shape in the embodiment illustrated in FIG.

[0131] Figure 2 The thickness and / or width of the main trace 100 illustrated in FIG. 1 may also be varied in order to change the strength of the magnetic field at point O.

[0132] It should be noted that by changing the thickness and width of the main trace 100 (that is, by changing the area of ​​its cross section), the resistance of the main trace 100 also changes.

[0133] As known to those skilled in the art, Figure 2 The magnetic field generated at point O by the current I flowing in the annular shaped main trace 100 illustrated in FIG. 1 will be (mainly) directed in a direction perpendicular to the plane of the main trace 100 .

[0134] Figure 3 A possible embodiment of the present description is illustrated, in which a current sensor device 10 is provided with a main track 100 in a plate-like shape.

[0135] Again, for simplicity and ease of understanding, unless the context indicates otherwise, the Figure 2 The parts or components discussed are similar to the parts or components in Figures 3 to 5 The same reference numerals are used to indicate the same parts, and the detailed description will not be repeated for the sake of brevity.

[0136] The studs 101 are provided to electrically couple the strips / traces on the substrate to the main traces 100 of the plate-like shape of the device 100 and are advantageously formed at two opposing sides thereof.

[0137] Figure 3The main trace 100 of the plate-like shape illustrated in FIG. 1 is formed in a plane parallel to and at a distance from the plane of the sensor die 14. Note that in this embodiment, the main trace 100 "overlaps" the sensor die 14, which is accordingly shown in dashed lines in the figure.

[0138] As illustrated, the plate-shaped main trace 100 is provided with a lateral width L1 (in the direction of the plane of the sensor die 14 ) which determines the strength of the magnetic field generated by the current I at point O of the sensor chip 14 , keeping all other factors constant.

[0139] like Figure 3 As illustrated in , the width of the main trace 100 may be constant along its length. However, main traces 100 having varying widths are contemplated.

[0140] like Figure 4 As illustrated in , main trace 100 may have an extreme width L1 (at stud 101 ) that is different from—eg, narrower than—a width L2 of a mid-portion therebetween.

[0141] In addition, with Figure 4 The main trace 100 with the stepped profile illustrated in can be replaced by a main trace 100 provided with a balloon-like profile showing a smoother transition between the extreme widths (e.g., having a minimum width L1) and the center width (e.g., characterized by a maximum width L2).

[0142] like Figure 3 As illustrated in , the magnetic field generated at point O by the current I flowing in the main trace 100 will be mainly directed in a direction parallel to the main trace 100 and transverse to the flow of the current I, and its strength also depends on the specific geometry of the plate-shaped main trace 100, i.e., for example, on the parameters L1, L2.

[0143] Note that the (varying) widths L1 , L2 of the plate-shaped main trace 100 also influence the overall resistance of the main trace 100 .

[0144] Figure 5 is an exemplary embodiment of the present specification, wherein trace 100 (similar to Figure 4 ) is provided with an aperture or slit 1000 in a portion of its length.

[0145] The aperture 1000 has a width L3 , the value of which affects the magnetic field generated at point O by the current I flowing through the main trace 100 .

[0146] Can be obtained through Figures 1A to 1K The same method described (with minor modifications) can be used to (easily) obtain Figures 2 to 5Various embodiments illustrated in .

[0147] In theory, only the steps of forming the main trace 100 and the stud 101 (i.e. Figure 1E and Figure 1F ) to obtain Figures 2 to 5 Different main trace 100 designs are shown in FIG.

[0148] Given a current intensity range to be measured (that is, the operating range of device 10), the active portion of sensor die 14 (assuming that it includes Figures 2 to 5 The magnetic field strength at point (O) shown in the figure is possible.

[0149] Table I below summarizes the calculated magnetic field strength Hy (kA / m) at point O for various configurations (L3 and L2) of the main trace 100.

[0150] Table I

[0151]

[0152] Table II below summarizes by reference the resistance values ​​(mOhm-DC) calculated for the corresponding configurations (L3 and L2) of the main trace 100.

[0153] Table I

[0154]

[0155] The results involve Figure 5 The plate-shaped main trace 100 illustrated in the table is characterized by an extreme width L1 having a fixed value, i.e., L1=1.2 mm, a central portion of width L2 (varying along the columns of the table) and an aperture 1000 of width L3 (varying along the rows of the table, where L3=0 means no aperture).

[0156] Assume that the DC current flowing through the main trace is 50 (A), and assume that the step profile of the main trace 100 is as follows Figure 4 and Figure 5 As shown in the figure.

[0157] The reported value of the magnetic field strength at point O is expressed in kA / m and refers to the component of the magnetic field parallel to the plane of the main trace 100 and perpendicular to the direction of current flow.

[0158] As reported in Table I, the value of the magnetic field can be effectively changed by shaping the main trace 100 differently.

[0159] The maximum value (13.5 kA / m) is obtained for the main trace 100 of a plate shape with a constant width (L1=L2) and no aperture (L3=0), while the minimum value (2.9 kA / m) is obtained with the maximum values ​​of the center and aperture widths L2=2.0 mm and L3=0.5 mm, and a difference of (almost) one order of magnitude is obtained.

[0160] The values ​​and widths indicated in Table I and Table II are merely exemplary and should not be interpreted in a limiting sense: they are reported herein for exemplary purposes only.

[0161] In some cases, such as for low current applications, it may be desirable to increase the strength of the magnetic field generated by the current to be measured as much as possible to reduce the signal-to-noise ratio and thereby improve the accuracy of the measurement device 10 .

[0162] In fact, as mentioned, the final substrate (eg, a PCB) comprising the traces / strips carrying the current to be measured may include several current-carrying lines / traces, which may negatively affect the measurement accuracy.

[0163] In this case, for example, it may be desirable to provide device 10 with a main trace 100 that is formed into a loop shape ( Figure 2 ) or a plate-shaped trace 100 without an aperture ( Figure 3 ) to maximize the magnetic field generated by the current.

[0164] For example, in the case of high currents, it may be desirable to reduce the strength of the magnetic field at the sensor die 14. In this case, the reduction of the magnetic field at the sensor die 14 facilitates the use of a sensor die 14 configured to measure lower strength magnetic fields.

[0165] In summary, the main trace 100 configured to carry the current I to be measured may be provided with various shapes.

[0166] Advantageous options include: a main trace 100 in annular shape; a main trace 100 in plate shape with a constant (eg L1 = L2 ) or varying ( L1 ≠ L2 ) width; and a main trace 100 in plate shape provided with an aperture 1000 .

[0167] Without prejudice to the basic principles, details and embodiments may vary, even significantly, from what is described merely by way of example without departing from the scope of protection. The claims are an integral part of the technical teaching provided with respect to the embodiments. The scope of protection is determined by the appended claims.

Claims

1. An electronic device, characterized in that: include: an insulating encapsulant encapsulating a semiconductor die, wherein the semiconductor die has a Hall current sensor integrated therein, the Hall current sensor being configured to measure a current flowing near an active surface of the semiconductor die; a conductive trace embedded in the insulating encapsulant, the conductive trace having opposing ends between which a current flow path is disposed adjacent the active surface of the semiconductor die; a first conductive configuration extending through the insulating encapsulation toward the opposite end of the conductive trace embedded in the insulating encapsulation, the first conductive configuration configured to cause a current under measurement to flow in the current flow path adjacent to the active surface of the semiconductor die; as well as A second conductive structure extends through the insulating encapsulant toward the active surface of the semiconductor die, the second conductive structure being configured to activate the Hall current sensor integrated in the semiconductor die.

2. The electronic device according to claim 1, characterized in that Also included is an insulating film laminated on the active surface of the semiconductor die, wherein the second conductive construction includes a conductive feature at a via opening through the insulating film.

3. The electronic device according to claim 1, characterized in that: The conductive trace embedded in the insulating enclosure has a ring shape.

4. The electronic device according to claim 1, characterized in that: The conductive trace embedded in the insulating enclosure has a plate shape.

5. The electronic device according to claim 1, characterized in that Wherein the conductive trace embedded in the insulating encapsulation has a middle portion located between the opposite end portions, and wherein the middle portion is wider than the opposite end portions.

6. The electronic device according to claim 1, characterized in that Wherein the conductive trace embedded in the insulating encapsulation has a middle portion located between the opposing ends, and wherein an aperture is disposed in the middle portion.

7. The electronic device according to claim 1, characterized in that: The insulating package comprises: an insulating film layer on the active surface of the semiconductor die; A first body of the encapsulation component encapsulating the semiconductor die, wherein a front surface of the body is coplanar with a front surface of the insulating film layer; A second body of the encapsulation component, covering the first body and the insulating film layer; wherein a portion of the second conductive structure is positioned between the second body and the insulating film layer and extends through a via opening in the second body and the insulating film layer; and a third body of the encapsulating component, covering the second body; wherein the conductive trace is positioned between the third body and the second body; wherein a portion of the first conductive structure extends through the third body; and The other portion of the second conductive structure extends through the third body.

8. The electronic device according to claim 7, characterized in that: The electronic device in the package does not utilize a metal lead frame.

9. The electronic device according to claim 1, characterized in that: Also includes: a current under measurement applied across the first conductive configuration, wherein the current under measurement flows in the current flow path adjacent the active surface of the semiconductor die; as well as A signal applied to the second conductive structure of the Hall current sensor integrated in the semiconductor die, wherein the signal is configured to activate the Hall current sensor to measure the current flowing in the current flow path adjacent to the active surface of the semiconductor die.

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