SPI chip time sequence test system
By designing an SPI chip timing test system including host computer, communication module and clock synchronization module, the problem of complex and inauspicious SPI chip timing test operation in the existing technology is solved, automatic testing and rapid analysis are realized, and testing efficiency is improved. Accuracy.
Patent Information
- Application Number
- CN202420804156.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-17
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-04-17
AI Technical Summary
The existing SPI chip timing testing methods are complex in operation and cannot implement automatic testing, resulting in waste of human resources and the inability to automatically record and analyze data.
A SPI chip timing test system is designed, including a computer, communication module, clock synchronization module, signal conversion module, first-in-first-out memory, flash memory module and power supply module. The clock of the communication module and the SPI chip to be tested is controlled through the clock synchronization module. Synchronize, realize automatic testing, and optimize signal processing through the signal conversion module, and transmit it to the upper computer for analysis.
Automatic testing of SPI chip timing is realized, which improves testing efficiency and accuracy, reduces waste of human resources, and can quickly analyze and display test results.
Smart Images
Figure CN222337627U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip timing test, in particular to a SPI chip timing test system. Background Art
[0002] Serial Peripheral Interface (SPI) is a four-wire synchronous serial peripheral interface launched by Motorola. It is a high-speed, full-duplex, synchronous communication bus, and only occupies four wires on the chip pins, saving chip pins and saving space on PCB layout, providing convenience. It is precisely because of this simple and easy-to-use feature that more and more chips are now integrated with this communication protocol and are widely used in mobile phones, tablets, automobiles, industry, etc.
[0003] When the SPI chip is communicating data, the interface timing parameters of the registers in the SPI chip need to conform to the parameter range corresponding to the SPI chip. However, due to the differences in SPI chips and manufacturing processes, the parameter ranges corresponding to different SPI chips are also different. Therefore, when using the SPI chip, the timing of the SPI chip needs to be tested.
[0004] The existing testing methods mainly implement testing through related instruments (such as signal sources and logic analyzers, etc.), which are relatively complicated to operate and cannot achieve automatic testing. Data analysis and processing cannot be automatically recorded, resulting in a huge waste of manpower. Utility Model Content
[0005] The main purpose of the utility model is to provide a SPI chip timing test system, aiming to solve the problem that the SPI chip timing cannot be automatically tested.
[0006] To achieve the above object, the utility model proposes a SPI chip timing test system, the test system comprising:
[0007] Host computer;
[0008] A communication module, the communication module is electrically connected to the host computer and the SPI chip to be tested;
[0009] A clock synchronization module is electrically connected to the communication module and the SPI chip to be tested, and is used to control the clock synchronization between the communication module and the SPI chip to be tested.
[0010] In some embodiments, the test system further includes a signal conversion module, and the communication module is electrically connected to the SPI chip to be tested through the signal conversion module.
[0011] In some embodiments, the signal conversion module includes an operational amplifier unit, and the operational amplifier unit is connected to the SPI chip to be tested via an SMA interface.
[0012] In some embodiments, the signal conversion module further includes a differential driver chip, and the differential driver chip is used to convert a single-ended signal into a differential signal.
[0013] In some embodiments, the signal conversion module also includes an analog-to-digital converter, which is electrically connected to the differential driver chip. The analog-to-digital converter is provided with a low voltage differential signaling interface (LVDS), which is electrically connected to the communication module.
[0014] In some embodiments, there are several signal conversion modules, and the several signal conversion modules are electrically connected to the several SPI chips to be tested, and the several signal conversion modules are connected in series to ensure clock synchronization.
[0015] In some embodiments, the test system further includes a first-in-first-out (FIFO) memory, and the communication module is electrically connected to the host computer via the first-in-first-out memory.
[0016] In some embodiments, the test system further includes a flash memory module, the flash memory module is electrically connected to the communication module, and the flash memory module stores operating firmware.
[0017] In some embodiments, the clock synchronization module includes a phase-locked loop circuit.
[0018] In some embodiments, the test system further includes a power supply module, and the power supply module is used to supply power to the test system.
[0019] The utility model controls the clock of the SPI chip to be tested and the clock of the communication module to keep synchronization through the clock synchronization module. The communication module tests the SPI chip to be tested and receives and processes the returned signal, and then transmits the processed signal to the host computer for analysis, thereby realizing automatic testing of the timing of the SPI chip to be tested. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a structural schematic diagram of an embodiment of a test system for SPI chip timing of the utility model;
[0021] Figure 2 It is a structural schematic diagram of another embodiment of the test system for SPI chip timing of the utility model;
[0022] Figure 3It is a structural schematic diagram of another embodiment of the test system of the SPI chip timing of the utility model;
[0023] Figure 4 It is a structural schematic diagram of another embodiment of the test system of the SPI chip timing of the utility model;
[0024] Figure 5 A preparation flow chart of an embodiment of a test system for SPI chip timing of the utility model;
[0025] Figure 6 This is a test flow chart of another embodiment of the test system for SPI chip timing of the present invention. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the scheme in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0027] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0028] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.
[0029] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.
[0030] The utility model proposes a SPI chip timing test system, referring to Figure 1 , the test system includes:
[0031] Host computer 10;
[0032] The communication module 20 is electrically connected to the host computer 10 and the SPI chip 40 to be tested;
[0033] The clock synchronization module 30 is electrically connected to the communication module 20 and the SPI chip 40 to be tested, and is used to control the clock synchronization between the communication module 20 and the SPI chip 40 to be tested.
[0034] For example, refer to Figure 5 , the test process in this embodiment is that the test system is powered on first, and after the communication module 20 loads the startup program, a handshake signal is sent to the host computer 10. After receiving the handshake signal, the host computer 10 connects with the communication module 20, that is, the preparation before the test is completed, and the communication module 20 enters the idle waiting mode. It can be understood that the host computer 10 can automatically connect to the communication module 20, or the connection can be completed manually by the staff. When the test starts, the host computer 10 sends a test command to the communication module 20, and the communication module 20 starts the signal acquisition function according to the test command, receives the signal returned from the SPI chip 40 to be tested and processes the signal; after the processing is completed, it is transmitted to the host computer 10 for further analysis, and the host computer 10 quickly analyzes and compares the standard timing threshold, and finally displays the timing result. Preferably, after the test is completed, the test results can be saved in a predetermined storage module, and the simulated timing graphics of each channel can be displayed on a display connected to the host computer 10.
[0035] The host computer 10 can be a computer device or an embedded system, which is used to control and monitor the test process and analyze and display the collected test results. The host computer 10 can interact with the staff, and the staff can input the parameters, test mode and other relevant configuration information of the SPI chip 40 to be tested through the interface of the host computer 10; the test program can also be pre-stored in the host computer 10, so that the host computer 10 automatically completes the test of the SPI chip 40 to be tested and analyzes the test results.
[0036] The communication module 20 is responsible for generating a test timing signal, communicating with the SPI chip 40 to be tested, collecting test data, and transmitting the test data to the host computer 10. Specifically, there are many types of communication modules 20, such as a microcontroller (MCU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), etc. Preferably, an editable logic gate array (FPGA) can be used as the communication module 20. Due to the differences in SPI chips of different brands or models, and the timing threshold of the SPI chip needs to be adjusted according to the application scenario, the test parameters may also be different. FPGA can not only be programmed according to specific needs, but also can be programmed and reconfigured multiple times. The staff can quickly iterate and modify as needed without redesigning the hardware.
[0037] The clock synchronization module 30 is connected to the FPGA and the SPI chip 40 to be tested, monitors the clock signals of both, and adjusts the clock signal of the FPGA to synchronize it with the clock signal of the chip to be tested, thereby reducing the test error caused by clock deviation or jitter to ensure the accuracy and stability of the test timing signal.
[0038] In this embodiment, the clock synchronization module 30 is used to control the clock synchronization of the SPI chip 40 to be tested and the communication module 20. The communication module 20 tests the SPI chip 40 to be tested and receives the returned signal. After processing the received test signal, it is transmitted to the host computer 10 for processing and analysis, thereby realizing automatic testing of the timing of the SPI chip 40 to be tested.
[0039] like Figure 2 As shown, in some embodiments, the test system further includes a signal conversion module 50, and the communication module 20 is electrically connected to the SPI chip 40 to be tested through the signal conversion module 50. Since the signal output by the SPI chip 40 to be tested is weak and not easy to be read and analyzed by the communication module 20, the signal conversion module 50 is used to optimize the signal and convert it into a stable and easy-to-analyze form. Compared with the previous embodiment, this embodiment refers to Figure 6 After receiving the test command from the host computer 10, the communication module 20 first configures the working mode of the signal conversion module 50, and then the signal conversion module 50 receives the signal of the SPI chip 40 to be tested and converts it. The communication module 20 then receives and processes the converted signal and finally transmits it to the host computer 10.
[0040] like Figure 3 and Figure 4 As shown, in some embodiments, the signal conversion module 50 includes an operational amplifier unit 51, and the operational amplifier unit 51 is connected to the SPI chip 40 to be tested through an SMA interface. The SMA interface is connected to the signal pin of the SPI chip, and the operational amplifier unit 51 is used to amplify the signal output by the SPI chip and convert it into a single-ended signal to facilitate subsequent reading of the signal. The SMA interface is a radio frequency coaxial connector interface, which has a stable connection and can reduce the impact of external interference on signal transmission.
[0041] like Figure 3 and Figure 4 As shown, in some embodiments, the signal conversion module 50 also includes a differential driver chip 52. The differential driver chip 52 can receive a single-ended signal from the operational amplifier unit 51 and convert it into a differential signal. The differential signal has good performance in terms of anti-interference and transmission distance. By converting the single-ended signal into a differential signal, the stability and anti-interference ability of the signal can be improved.
[0042] like Figure 3 and Figure 4 As shown, in some embodiments, the signal conversion module 50 also includes an analog-to-digital converter 53, the analog-to-digital converter 53 is electrically connected to the differential drive chip 52, and the analog-to-digital converter 53 is provided with a low voltage differential signal interface, and the low voltage differential signal interface is electrically connected to the communication module 20. During the test, the analog-to-digital converter 53 converts the differential signal from the differential drive chip 52 into a digital signal, and then transmits the digital signal to the communication module 20 through the LVDS interface. LVDS is a high-speed serial communication technology. The LVDS interface is used to transmit data in a digital system, has a fast transmission speed, and has a strong anti-interference ability, which is of great help to improve the test efficiency and test accuracy. It can be understood that the analog-to-digital converter 53 can be connected to multiple differential drive chips 52 and multiple operational amplifiers at the same time, and then test multiple SPI chips 40 to be tested at the same time, further improving the test efficiency.
[0043] like Figure 4 As shown, in some embodiments, there are several signal conversion modules 50, several signal conversion modules 50 are electrically connected to several SPI chips 40 to be tested, and several signal conversion modules 50 are connected in series to ensure clock synchronization. Multiple signal conversion modules 50 can be connected to multiple SPI chips 40 to be tested, further improving the test efficiency. Exemplarily, if there are three signal conversion modules 50, each of which can process the signals of two SPI chips 40 to be tested, six SPI chips 40 to be tested can be tested at the same time. At this time, the analog-to-digital converters 53 in each signal conversion module 50 are connected, and the clocks of the three analog-to-digital converters 53 are synchronized by the clock synchronization module 30, so that the clocks of the three signal conversion modules 50 can be synchronized with the clocks of the SPI chip 40 to be tested.
[0044] like Figure 4 As shown, in some embodiments, the test system further includes a first-in-first-out memory (FIFO), and the communication module 20 is electrically connected to the host computer 10 through the first-in-first-out memory. FIFO is used to alleviate the speed difference between the communication module 20 and the host computer 10 in processing data. Since the host computer 10 is responsible for more complex analysis and storage work, its processing speed is often slower than that of the communication module 20. At this time, the data generated by the communication module 20 can be temporarily stored through the FIFO, so that the host computer 10 can process the data at a normal rate without causing data loss. By providing temporary storage and data flow control, FIFO can ensure the normal operation of the system and improve the stability of the system.
[0045] like Figure 4 As shown, in some embodiments, the test system further includes a flash memory module, which is electrically connected to the communication module 20, and the flash memory module stores the running firmware. When testing is required, the communication module 20 can directly read the firmware from the flash memory. Since the firmware is directly loaded into the hardware, the startup time of the test can be shortened, and the firmware is closely integrated with the hardware, less affected by the external environment or the operating system, and is not prone to failure or crash.
[0046] In some embodiments, the clock synchronization module 30 includes a phase-locked loop circuit. The main function of the phase-locked loop circuit is to generate a stable and accurate output signal, the phase and frequency of which are synchronized with the input reference clock, so after receiving the clock signal of the SPI chip 40 to be tested, the clocks of the communication module 20 and the signal conversion module 50 can be kept consistent with those of the SPI chip 40 to be tested.
[0047] In some embodiments, the test system further includes a power supply module, which is used to supply power to the test system. The power supply module is used to supply power to the entire test system to ensure the continued normal operation of the test system. It is understandable that the power supply module can provide corresponding voltages to different modules in the test system to prevent malfunctions.
[0048] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.
Claims
1. A SPI chip timing test system, characterized in that: The test system comprises: Host computer; A communication module, the communication module is electrically connected to the host computer and the SPI chip to be tested; A clock synchronization module is electrically connected to the communication module and the SPI chip to be tested, and is used to control the clock synchronization between the communication module and the SPI chip to be tested.
2. The test system according to claim 1, characterized in that: The test system further comprises a signal conversion module, and the communication module is electrically connected to the SPI chip to be tested via the signal conversion module.
3. The test system according to claim 2, characterized in that: The signal conversion module includes an operational amplifier unit, and the operational amplifier unit is connected to the SPI chip to be tested through an SMA interface.
4. The test system according to claim 3, characterized in that: The signal conversion module further includes a differential driving chip, and the differential driving chip is used to convert a single-ended signal into a differential signal.
5. The test system according to claim 4, characterized in that: The signal conversion module further includes an analog-to-digital converter, which is electrically connected to the differential driving chip. The analog-to-digital converter is provided with a low-voltage differential signal interface, which is electrically connected to the communication module.
6. The test system according to claim 2, characterized in that: There are a plurality of signal conversion modules, and the plurality of signal conversion modules are electrically connected to a plurality of SPI chips to be tested, and the plurality of signal conversion modules are connected in series to ensure clock synchronization.
7. The test system according to claim 1, characterized in that: The test system further comprises a first-in-first-out memory, and the communication module is electrically connected to the host computer via the first-in-first-out memory.
8. The test system according to claim 1, characterized in that: The test system further comprises a flash memory module, the flash memory module is electrically connected to the communication module, and the operating firmware is stored in the flash memory module.
9. The test system according to claim 1, characterized in that: The clock synchronization module includes a phase-locked loop circuit.
10. The test system according to any one of claims 1 to 9, characterized in that: The test system further comprises a power supply module, and the power supply module is used to supply power to the test system.