Testing device for time sequence of memory card

Abstract

The utility model discloses a memory card time sequence testing device. The memory card time sequence testing device comprises an upper computer; the test seat is provided with a signal output interface, and the signal output interface is connected with a signal pin of the memory card to be tested; the signal acquisition module is electrically connected with the signal output interface; the signal acquisition module comprises an analog-to-digital converter and an SPI controller arranged on the analog-to-digital converter, the SPI controller is used for configuring the analog-to-digital converter, and the analog-to-digital converter and the SPI controller are electrically connected with the upper computer. According to the utility model, the type of the current memory card to be tested is detected through the upper computer, and the analog-to-digital converter can be configured with different signal acquisition modes according to different types of memory cards to be tested through the SPI controller in the signal acquisition module, so that the time sequence test of the memory card to be tested can be completed at the fastest speed; according to the invention, automatic testing of different types of memory cards to be tested is realized, manpower and time cost are saved, and testing efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip timing test, in particular to a memory card timing test device. Background Art

[0002] With the enrichment of various multimedia entertainment contents, consumers have higher and higher requirements for the storage capacity of the electronic products they use, making memory cards widely used in various electronic devices. Memory cards are small removable storage devices that store data through flash memory technology. They are of various types and usually connected to devices using specific interfaces.

[0003] In order to ensure that the memory card works stably and reliably, manufacturers generally test the sampling timing of the memory card during production. The existing timing test method mainly uses related instruments to implement the test (such as signal sources and logic analyzers, etc.), which is relatively complicated to operate and cannot test different types of memory cards. At the same time, it cannot automatically record and analyze the processed data, which causes a great waste of manpower. Utility Model Content

[0004] The main purpose of the utility model is to provide a memory card timing test device, aiming to solve the problem that timing tests cannot be performed on different types of memory cards.

[0005] To achieve the above object, the utility model provides a memory card timing test device for testing a secure digital memory card (SD card) and an embedded multimedia card (EMMC card). The test device comprises:

[0006] Host computer;

[0007] A test socket, wherein the test socket is provided with a signal output interface, and the signal output interface is connected to a signal pin of the memory card to be tested;

[0008] A signal acquisition module, the signal acquisition module is electrically connected to the signal output interface;

[0009] The signal acquisition module includes an analog-to-digital converter and an SPI controller arranged on the analog-to-digital converter, the SPI controller is used to configure the analog-to-digital converter, and the analog-to-digital converter and the SPI controller are both electrically connected to the host computer.

[0010] In some embodiments, the memory card timing test device further includes an editable logic gate array module (Field Programmable Gate Array, FPGA), and the editable logic gate array module is electrically connected to the host computer and the signal acquisition module.

[0011] In some embodiments, the analog-to-digital converter is electrically connected to the editable logic gate array module via an FMC interface (FPGA Mezzanine Card), and the SPI controller is connected to the editable logic gate array module via an SPI interface.

[0012] In some embodiments, the memory card timing test device also includes a clock synchronization module, which is electrically connected to the signal acquisition module, the editable logic gate array module and the test socket, and is used to control the clock synchronization of the signal acquisition module, the editable logic gate array module and the memory card to be tested.

[0013] In some embodiments, the clock synchronization module includes a phase-locked loop circuit.

[0014] In some embodiments, the test device further includes a signal conversion module, and the signal acquisition module is electrically connected to the test socket via the signal conversion module.

[0015] In some embodiments, the signal conversion module includes an operational amplifier unit and a differential drive chip, the operational amplifier unit is electrically connected to the test socket, the differential drive chip is electrically connected to the operational amplifier unit, and the signal acquisition module is electrically connected to the differential drive chip.

[0016] In some embodiments, the testing device further includes a first-in first-out (FIFO) memory, and the editable logic gate array module is electrically connected to the host computer via the first-in first-out memory.

[0017] In some embodiments, the testing device further comprises a flash memory module, the flash memory module is electrically connected to the editable logic gate array module, and the flash memory module stores operating firmware.

[0018] In some embodiments, the testing device further includes a power supply module, and the power supply module is electrically connected to the signal acquisition module and the test socket.

[0019] The utility model detects the type of the current memory card to be tested by a host computer, and through the SPI controller in the signal acquisition module, enables the analog-to-digital converter to configure different signal acquisition modes according to different types of memory cards to be tested, completes the timing test of the memory card to be tested at the fastest speed, realizes automatic testing of different types of memory cards to be tested, saves manpower and time costs, and improves test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of an embodiment of a memory card timing test device of the utility model;

[0021] Figure 2 It is a structural schematic diagram of another embodiment of the memory card timing test device of the utility model;

[0022] Figure 3 It is a structural schematic diagram of another embodiment of the memory card timing test device of the utility model;

[0023] Figure 4 It is a structural schematic diagram of another embodiment of the memory card timing test device of the utility model;

[0024] Figure 5 It is a structural schematic diagram of another embodiment of the memory card timing test device of the present utility model.

[0025] Reference numerals:

[0026] 10. Host computer; 20. Signal conversion module; 21. Analog-to-digital converter; 22. SPI controller; 30. Test socket; 40. Editable logic gate array module; 50. Clock synchronization module; 60. Signal conversion module; 61. Operational amplifier unit; 62. Differential driver chip; 70. First-in-first-out memory; 80. Flash memory module. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the scheme in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0028] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0029] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0030] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0031] The utility model provides a memory card timing test device for testing a secure digital memory card and an embedded multimedia card. Figure 1 , the test device comprises:

[0032] Host computer 10;

[0033] A test socket 30, on which a signal output interface is provided, and the signal output interface is connected to a signal pin of the memory card to be tested;

[0034] A signal acquisition module 20, the signal acquisition module 20 is electrically connected to the signal output interface;

[0035] The signal acquisition module 20 includes an analog-to-digital converter 21 and an SPI controller 22 disposed on the analog-to-digital converter 21 . The SPI controller 22 is used to configure the analog-to-digital converter 21 . Both the analog-to-digital converter 21 and the SPI controller 22 are electrically connected to the host computer 10 .

[0036] When the test starts, the host computer 10 sends a test command to the signal acquisition module 20. After the SPI controller 22 in the signal acquisition module 20 identifies the type of the memory card to be tested, the working mode of the analog-to-digital converter 21 is configured, that is, the number of appropriate signal acquisition channels is set, wherein the signal acquisition channel is the connection channel between the signal output interface and the signal pin of the memory card to be tested. For example, if a secure digital memory card, that is, an SD card, is tested, the signal output interface of the test socket 30 only needs to be connected to the 4 data transmission pins of the SD card, and connected to the CLK and CMD pins of the SD card, wherein the CLK pin is used to output a clock signal, synchronize data transmission and drive the operation of the device, and the CMD pin is used for the interaction between the memory card and the signal acquisition module 20; if an embedded multimedia card, that is, an EMMC card, is tested, the signal output interface of the test socket 30 can be connected to all data transmission pins of the EMMC card as well as the CLK and CMD pins to collect data faster.

[0037] Then the signal acquisition module 20 starts the signal acquisition function according to the test command of the host computer 10, receives the signal output from the test socket 30, and converts the signal into a digital signal. The converted signal is then transmitted to the host computer 10 for further analysis, and the host computer 10 quickly analyzes and compares the standard timing threshold (usually the reference value range of the SD card / EMMC card of each manufacturer), and finally displays the timing result. Preferably, after the test is completed, the test results can be saved in a predetermined storage module, and the analog timing graph of each channel and the corresponding recommended measures can be displayed on the display module connected to the host computer 10.

[0038] The host computer 10 can be a computer device or an embedded system, which is used to control and monitor the test process and analyze and display the collected test results. The host computer 10 can interact with the staff, and the staff can input the parameters, test mode and other relevant configuration information of the memory card to be tested through the host computer 10 operation interface; the test program can also be pre-stored in the host computer 10, so that the host computer 10 automatically completes the test of the memory card to be tested and analyzes the test results.

[0039] The test socket 30 is used to connect the memory card to be tested, and a signal output interface is provided on the test socket 30 for outputting various signals of the memory card to be tested. The signal output interface is usually an SDIO interface (Secure Digital Input and Output). Preferably, the test socket 30 can be connected to multiple memory cards to be tested, and a plurality of signal output interfaces are provided corresponding to the memory cards to be tested, so as to facilitate the timing of multiple memory cards to be tested to be tested simultaneously and improve the test efficiency.

[0040] The utility model detects the type of the current memory card to be tested by the host computer 10, and through the SPI controller 22 in the signal acquisition module 20, enables the analog-to-digital converter 21 to configure different signal acquisition modes according to the different types of memory cards to be tested, completes the timing test of the memory card to be tested at the fastest speed, realizes automatic testing of different types of memory cards to be tested, saves manpower and time costs, and improves test efficiency.

[0041] like Figure 2 As shown, in some embodiments, the memory card timing test device further includes an editable logic gate array module 40, and the editable logic gate array module 40 is electrically connected to the host computer 10 and the signal acquisition module 20. Since different brands or models of memory cards to be tested are different, and the timing threshold of the memory cards to be tested needs to be adjusted according to the application scenario, the test parameters may also be different, and the editable logic gate array module 40 (hereinafter referred to as FPGA module) can not only be programmed according to specific needs, but also can be programmed and reconfigured multiple times, and the staff can quickly iterate and modify as needed without redesigning the hardware.

[0042] After the FPGA module is set, the FPGA module can be connected to the host computer 10 by handshake before testing to determine whether the test can be performed normally. Exemplarily, after the FPGA module loads the startup program, it sends a handshake signal to the host computer 10. If the host computer 10 connects to the FPGA module after receiving the handshake signal, the preparation before the test is completed, and the FPGA module enters the idle waiting mode; if the host computer 10 is not connected to the FPGA module, the FPGA module continues to send a handshake signal. If the connection fails three times in a row, the test is terminated and an alarm signal is sent to report the cause of the error and the error code and other information to remind the staff to handle it. It is understandable that the host computer 10 can also manually confirm the connection with the FPGA module through the staff.

[0043] like Figure 2 As shown, in some embodiments, the analog-to-digital converter 21 is electrically connected to the editable logic gate array module 40 via an FMC interface, and the SPI controller 22 is connected to the editable logic gate array module 40 via an SPI interface.

[0044] The FMC interface is an interface for connecting an FPGA module, supporting high-speed serial connection, and is suitable for application scenarios that require high bandwidth and low latency. The FMC interface usually has multiple connection pins and can support a variety of different types of peripherals or modules, so it has strong scalability. When it is necessary to expand functions, new modules can be directly added without large-scale modifications to the entire system. The SPI interface usually supports high-speed transmission and has a high data transmission rate. The SPI interface supports full-duplex communication, allowing data to be sent and received simultaneously, thereby achieving higher communication efficiency. The SPI controller 22 is connected to the FPGA module through the SPI interface, so that the FPGA module controls the signal acquisition module 20 more quickly and conveniently.

[0045] like Figure 3 As shown, in some embodiments, the memory card timing test device also includes a clock synchronization module 50, and the clock synchronization module 50 is electrically connected to the signal acquisition module 20, the editable logic gate array module 40 and the test socket 30, and is used to control the signal acquisition module 20, the editable logic gate array module 40 and the memory card to be tested to synchronize the clock.

[0046] The clock synchronization module 50 receives the clock signal from the memory to be tested by connecting with the signal acquisition module 20, the editable logic gate array module and the test socket 30, and adjusts the clock signal of the signal acquisition module 20 and the editable logic gate array module to synchronize with the clock signal of the memory to be tested, thereby reducing the test error caused by clock deviation or jitter to ensure the accuracy and stability of the test timing signal. Furthermore, by setting the clock synchronization module 50, the clock frequency can be dynamically adjusted during the communication process to control the clock frequency within the minimum range to save power and realize the data flow control function.

[0047] In some embodiments, the clock synchronization module 50 includes a phase-locked loop circuit. The main function of the phase-locked loop circuit is to generate a stable and accurate output signal, the phase and frequency of which are synchronized with the input reference clock, so after receiving the clock signal of the memory card to be tested, the clock of the signal acquisition module 20 can be kept consistent with that of the memory card to be tested.

[0048] like Figure 4As shown, in some embodiments, the test device also includes a signal conversion module 60, and the signal acquisition module 20 is electrically connected to the test socket 30 through the signal conversion module 60. Since the signal output by the memory card to be tested is weak and not easy to be read by the signal acquisition module 20, the signal conversion module 60 is used to optimize the signal and convert it into a stable and easy-to-read form. During the test, the signal conversion module 60 first receives the signal output by the memory card to be tested, and then the signal conversion module 60 converts the signal, and the signal acquisition module 20 receives and processes the converted signal, and finally transmits it to the host computer 10. Furthermore, due to the different types and signals of the memory cards to be tested, the number of their signal pins is also different. By setting a plurality of signal conversion modules 60, correspondingly connecting a plurality of signal pins, the signal output by each signal pin is converted, which is convenient for the host computer 10 to read and analyze.

[0049] like Figure 4 As shown, in some embodiments, the signal conversion module 60 includes an operational amplifier unit 61 and a differential drive chip 62, the operational amplifier unit 61 is electrically connected to the test socket 30, the differential drive chip 62 is electrically connected to the operational amplifier unit 61, and the signal acquisition module 20 is electrically connected to the differential drive chip 62.

[0050] The operational amplifier unit 61 is used to amplify the signal output by the memory card to be tested and convert it into a single-ended signal, so as to facilitate the subsequent reading of the signal. The differential driver chip 62 can receive the single-ended signal from the operational amplifier unit 61 and convert it into a differential signal. The differential signal has good performance in terms of anti-interference and transmission distance. By converting the single-ended signal into a differential signal, the stability and anti-interference ability of the signal can be improved. The differential signal is then transmitted to the signal acquisition module 20, and the analog-to-digital converter 21 in the signal acquisition module 20 converts the differential signal into a digital signal, that is, realizes the conversion of the signal, and then transmits the converted signal to the FPGA module for processing, and finally transmits it to the host computer 10, so that the host computer 10 can read and analyze it.

[0051] like Figure 5 As shown, in some embodiments, the test device also includes a first-in-first-out memory 70, and the editable logic gate array module is electrically connected to the host computer 10 through the first-in-first-out memory 70. FIFO is used to alleviate the speed difference between the editable logic gate array module and the host computer 10 in processing data. Since the host computer 10 is responsible for more complex analysis and storage work, its processing speed is often slower than that of the editable logic gate array module. At this time, the data generated by the editable logic gate array module can be temporarily stored through the FIFO, so that the host computer 10 can process data at a normal rate without causing data loss. By providing temporary storage and data flow control, FIFO can ensure the normal operation of the system and improve the stability of the system.

[0052] like Figure 5 As shown, in some embodiments, the test device further includes a flash memory module 80, which is electrically connected to the editable logic gate array module, and the flash memory module 80 stores running firmware. When testing is required, the editable logic gate array module can directly read the firmware from the flash memory. Since the firmware is directly loaded into the hardware, the startup time of the test can be shortened, and the firmware is closely integrated with the hardware, less affected by the external environment or the operating system, and is not prone to failure or crash.

[0053] In some embodiments, the test device further includes a power supply module, which is electrically connected to the signal acquisition module 20 and the test socket 30. It is understandable that the power supply module can provide appropriate voltages to the signal acquisition module 20 and the test socket 30, respectively, so that the entire test device can run smoothly and prevent malfunctions.

[0054] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A memory card timing test device for testing secure digital memory cards and embedded multimedia cards, characterized in that: The testing device comprises: Host computer; A test socket, wherein the test socket is provided with a signal output interface, and the signal output interface is connected to a signal pin of the memory card to be tested; A signal acquisition module, the signal acquisition module is electrically connected to the signal output interface; The signal acquisition module includes an analog-to-digital converter and an SPI controller arranged on the analog-to-digital converter, the SPI controller is used to configure the analog-to-digital converter, and the analog-to-digital converter and the SPI controller are both electrically connected to the host computer.

2. The testing device according to claim 1, characterized in that: The memory card timing test device further comprises an editable logic gate array module, and the editable logic gate array module is electrically connected to the host computer and the signal acquisition module.

3. The testing device according to claim 2, characterized in that: The analog-to-digital converter is electrically connected to the editable logic gate array module via an FMC interface, and the SPI controller is connected to the editable logic gate array module via an SPI interface.

4. The testing device according to claim 3, characterized in that: The memory card timing test device also includes a clock synchronization module, which is electrically connected to the signal acquisition module, the editable logic gate array module and the test socket, and is used to control the signal acquisition module, the editable logic gate array module and the memory card to be tested to synchronize clocks.

5. The testing device according to claim 4, characterized in that: The clock synchronization module includes a phase-locked loop circuit.

6. The testing device according to claim 5, characterized in that: The testing device further comprises a signal conversion module, and the signal acquisition module is electrically connected to the testing socket via the signal conversion module.

7. The testing device according to claim 6, characterized in that: The signal conversion module includes an operational amplifier unit and a differential drive chip. The operational amplifier unit is electrically connected to the test socket, the differential drive chip is electrically connected to the operational amplifier unit, and the signal acquisition module is electrically connected to the differential drive chip.

8. The testing device according to claim 2, characterized in that: The testing device further comprises a first-in-first-out memory, and the editable logic gate array module is electrically connected to the host computer via the first-in-first-out memory.

9. The testing device according to claim 2, characterized in that: The testing device further comprises a flash memory module, which is electrically connected to the editable logic gate array module and stores operating firmware.

10. The testing device according to any one of claims 1 to 9, characterized in that: The testing device further comprises a power supply module, and the power supply module is electrically connected to the signal acquisition module and the test socket.

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