Digital phase-locked amplifier

Abstract

The utility model belongs to the technical field of amplifiers, and discloses a digital lock-in amplifier which comprises an ARM communicated with a user side, an FPGA communicated with the ARM, an ADC acquisition mode communicated with the FPGA, a low pass connected with the ADC, an amplifier connected with the low pass and a to-be-detected data signal connected with the amplifier, the FPGA is communicated with a reference data signal, and the FPGA is directly communicated with the amplifier; under the overall data signal control flow and transmission effect, the FPGA is used for collection at the front end, the ARM processor is used at the rear end, and the front end and the rear end are connected through the high-speed bus, so that the FPGA can effectively process high-speed sampling processing logic with strict time sequence, and then data is transmitted to the ARM processor for processing after being subjected to low-pass filtering, so that the data processing efficiency is improved. Therefore, the high-speed sampling capability and the flexible algorithm function are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of amplifiers, and more specifically, to a digital lock-in amplifier. Background Art

[0002] A digital lock-in amplifier is a lock-in amplifier based on digital signal processing. According to the degree of digitization, the lock-in amplifier is divided into an analog lock-in amplifier, a digital-analog hybrid lock-in amplifier, and a digital lock-in amplifier. A general lock-in amplifier is mainly composed of an oscillator, a mixer, and a filter. The digital lock-in amplifier realizes the full digitization of the mixer and the filter. With the continuous improvement of digital signal processing technology, digital lock-in amplifiers are gradually replacing traditional analog lock-in amplifiers. Because of the digitalization of signal processing, digital lock-in amplifiers have the characteristics of high integration, convenient configuration, and online upgrade, etc.

[0003] In the digital phase-locked amplifiers currently used in the market, ARM processors or FPGA acquisition methods are usually used internally, which makes these two methods have the problems of slow speed and stable sampling can only be achieved below 1MHz. At the same time, there are problems such as fast speed but inflexible information processing and simple algorithms that can be implemented, which affects the overall performance of the digital phase-locked amplifier.

[0004] In order to solve the above problems, the present application provides a digital lock-in amplifier. Utility Model Content

[0005] The digital lock-in amplifier provided in this application adopts the following technical solution:

[0006] A digital phase-locked amplifier includes an ARM connected to a user end, an FPGA connected to the ARM, an ADC acquisition mode connected to the FPGA, a low pass connected to the ADC, an amplifier connected to the low pass, and a data signal to be tested connected to the amplifier, wherein the FPGA is connected to a reference data signal, and the FPGA is directly connected to the amplifier.

[0007] Through the above technical solution, the stable performance of data information collection of the FPGA status can be effectively guaranteed by utilizing the set ADC collection mode.

[0008] Furthermore, the reference data signal is phase-shifted to generate two orthogonal sinusoidal signals of the same frequency, which are respectively multiplied, amplified and low-passed with the data signal to be measured before reaching the ADC for collection, and are fed back to the FPGA for controlled amplification.

[0009] Through the above technical solution, the collection and amplification functions of the reference data information and the data information to be measured can be effectively guaranteed by using two orthogonal sinusoidal signals of the same frequency generated by phase shifting of the reference data signal.

[0010] Furthermore, the FPGA and ARM are connected via a high-speed bus, and the FPGA is a front-end acquisition processing mode, and the ARM is a back-end control processing mode.

[0011] Through the above technical solution, the high-speed bus is utilized to achieve a stable and high-speed connection between FPGA and ARM. At the same time, with the joint action of FPGA acquisition at the front end and ARM processor at the back end, the overall high-speed sampling capability of data information and flexible algorithm functions can be well guaranteed.

[0012] Furthermore, the user terminal is connected to the ARM via a serial port, USB, or network port, and the ARM implements a variety of low-pass processing on incoming data.

[0013] Through the above technical solution, the connection effect between the user terminal interface and the data information processing terminal can be achieved by utilizing the provided serial port, USB, and network port connection methods.

[0014] In summary, this application includes the following beneficial technical effects:

[0015] Through the overall data signal control process and transmission, and with the use of FPGA acquisition at the front end and ARM processor at the back end, and the front and back ends using a high-speed bus connection method, the FPGA can effectively process high-speed and time-strict sampling processing logic. The data is then low-pass filtered and transmitted to the ARM processor for processing, thereby ensuring high-speed sampling capabilities and flexible algorithm functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is the overall principle block diagram of this application;

[0017] Figure 2 For this application Figure 1 Refer to the block diagram of the generated signal principle. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application; obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments, and all other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application without making creative work are within the scope of protection of the present application.

[0019] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", "top / bottom" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "set / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0021] Example:

[0022] The present application embodiment discloses a digital lock-in amplifier. Figure 1 and Figure 2 , including an ARM connected to a user end, an FPGA connected to the ARM, an ADC acquisition method connected to the FPGA, a low pass connected to the ADC, an amplifier connected to the low pass, and a data signal to be measured connected to the amplifier, the FPGA is connected to a reference data signal, and the FPGA is directly connected to the amplifier. The FPGA is a product further developed on the basis of programmable devices such as PAL (programmable array logic) and GAL (general array logic). It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices;

[0023] The reference data signal is phase-shifted to generate two orthogonal sinusoidal signals of the same frequency. The two orthogonal sinusoidal signals of the same frequency are respectively multiplied, amplified, and low-passed with the data signal to be measured before reaching the ADC for acquisition, and are fed back to the FPGA for control amplification.

[0024] FPGA and ARM are connected through a high-speed bus, and FPGA is the front-end acquisition processing mode, and ARM is the back-end control processing mode. The front-end and back-end information processing mode jointly presented by the FPGA and ARM can effectively overcome the problems of slow speed and stable sampling that can only be achieved below 1MHz in the existing market, or the problems of fast speed but inflexible information processing and simple algorithm implementation. Therefore, a sampling processing logic with high-speed processing and strict timing is formed, and the high-speed sampling capability and flexible algorithm function benefits are effectively guaranteed;

[0025] The user end is connected to ARM through serial port, USB and network port, and ARM implements multiple low-pass processing on the incoming data. Under the action of the ARM processor used, it can ensure multiple low-pass processing of the incoming data information, while being able to play a good role in calculating phase, calculating complex application data and providing user interface communication.

[0026] The implementation principle of this embodiment is as follows: during use, the data signal to be tested is collected by the ADC after amplification and low-pass processing, and fed back to the FPGA, and the data signal is controlled and processed by the ARM by using the high-speed bus connection between the FPGA and the ARM, and then the processed data signal to be tested is fed back to the user interface by using the connection between the serial port, USB, and network port between the ARM and the user end;

[0027] The reference data signal and the data signal to be tested are two lines entering the system. After the reference data signal is phase-shifted by 90 degrees to generate two orthogonal sinusoidal signals of the same frequency, they are respectively multiplied and amplified, low-pass processed and ADC collected with the data signal to be tested. Finally, the data signal is fed back to the user-end interface by using the high-speed bus connection between the FPGA and ARM.

[0028] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A digital lock-in amplifier, characterized in that: It includes an ARM connected to the user end, an FPGA connected to the ARM, an ADC acquisition method connected to the FPGA, a low pass connected to the ADC, an amplifier connected to the low pass, and a data signal to be tested connected to the amplifier. The FPGA is connected to the reference data signal, and the FPGA is directly connected to the amplifier.

2. A digital lock-in amplifier according to claim 1, characterized in that: The reference data signal is phase-shifted to generate two orthogonal sinusoidal signals with the same frequency. The two orthogonal sinusoidal signals with the data signal to be measured are respectively multiplied, amplified, and low-passed to reach the ADC for collection, and are fed back to the FPGA for control amplification.

3. A digital lock-in amplifier according to claim 1, characterized in that: The FPGA and ARM are connected via a high-speed bus, and the FPGA is a front-end acquisition processing mode, and the ARM is a back-end control processing mode.

4. A digital lock-in amplifier according to claim 1, characterized in that: The user terminal is connected to the ARM via a serial port, USB, or network port, and the ARM implements a variety of low-pass processing on incoming data.

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