Switching circuit
By designing a switching circuit including a switching tube unit and a voltage divider circuit, the impact of OOK signal communication on the antenna standing wave ratio performance in the AISG2.0 protocol is solved, and dynamic control of OOK signal during signal communication in the AISG2.0 protocol is realized. Ensure external communication performance and independence of the antenna.
Patent Information
- Application Number
- CN202421003556.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-05-09
AI Technical Summary
In communication systems using the AISG2.0 protocol, OOK signal communication of 2.176MHz will affect the stability of the standing wave ratio performance index of the antenna.
A switching circuit is designed, including AISG2.0 power supply input circuit, voltage divider circuit, first switching tube unit, second switching tube unit, third switching tube unit and OOK signal carrier modulation chip, and detects AISG2.0 power supply input The voltage of the circuit controls the opening and closing of the switch tube unit, ensuring that the working power of the OOK signal carrier modulation chip is turned off during the AISG2.0 protocol signal communication, and avoiding the mutual influence of the two communication methods.
It realizes that the working state of the OOK signal is dynamically controlled during the AISG2.0 protocol signal communication process, so as not to affect the external communication performance of the antenna and ensures the independence and stability of the two communication methods.
Smart Images
Figure CN222339402U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of communication equipment, in particular to a switch circuit. Background Art
[0002] Antennas are key elements in wireless communication systems. They are responsible for transmitting electromagnetic energy from cables to the air, or collecting electromagnetic energy from the air and transmitting it to cables. The performance of antennas directly affects the performance of communication systems, and the standing wave ratio is one of the important indicators for measuring antenna performance.
[0003] In recent years, in order to improve the communication efficiency and function of communication equipment, a communication protocol called AISG2.0 has been widely used, which can achieve more stable and easy-to-maintain communication between devices. At the same time, OOK (On-OffKeying) modulation has also been widely used in different communication systems, especially in fast wireless data transmission. However, during continuous communication using the AISG2.0 protocol, if there is 2.176MHz OOK signal communication in the communication system at the same time, it will affect the stability of the antenna's standing wave ratio performance index. Summary of the invention
[0004] In view of the above problems, on the first aspect, an embodiment of the utility model provides a switching circuit, which includes: an AISG2.0 power supply input circuit, a voltage divider circuit, a first switch tube unit, a second switch tube unit, a third switch tube unit and an OOK signal carrier modulation chip, the voltage divider circuit is connected to the AISG2.0 power supply input circuit, the first switch tube unit is connected to the voltage divider circuit, the second switch tube unit is connected to the first switch tube unit, the third switch tube unit is connected to the second switch tube unit, and the OOK signal carrier modulation chip is connected to the third switch tube unit.
[0005] In one embodiment, the AISG2.0 power supply input circuit includes: capacitor C101, capacitor C102, gas discharge tube G102, inductor L101, inductor L102, transient voltage suppression diode D104, transient voltage suppression diode D105, thermistor RPTC102 and diode D110, wherein the capacitor C101 and capacitor C102 are connected in parallel with the gas discharge tube G102, the gas discharge tube G102 is connected in parallel with the inductor L101 and the inductor L102, the other ends of the inductors L101 and L102 are connected to the parallel route formed by the transient voltage suppression diode D104 and the transient voltage suppression diode D105, the thermistor RPTC102 and the diode D110 are connected in parallel and connected to the parallel route formed by the transient voltage suppression diode D104 and the transient voltage suppression diode D105.
[0006] In one embodiment, the voltage divider circuit includes a resistor R11, a resistor R12 and a resistor R13, wherein one end of the resistor R11 is used to connect to the AISG2.0 power supply input circuit, the other end of the resistor R11 is connected to the resistor R12 and one end of the resistor R13, the other end of the resistor R12 is connected to the third switch tube unit, and the other end of the resistor R13 is grounded.
[0007] In one embodiment, the voltage divider circuit further includes: a capacitor C14, and the capacitor C14 is connected in parallel with the resistor R13.
[0008] In one embodiment, the first switch tube unit includes a MOS tube Q1, the second switch tube unit includes a triode Q2, and the third switch tube unit includes a triode Q3, the base of the triode Q3 is connected to the voltage divider circuit, the collector of the triode Q3 is connected to the base of the triode Q2, the emitter of the triode Q2 is connected to the source of the MOS tube Q1, the drain of the MOS tube Q1 is connected to the OOK signal carrier modulation chip, the collector of the triode Q3, the base of the triode Q2 and the source of the MOS tube Q1 are connected to the voltage input terminal, and the emitter of the triode Q3, the collector of the triode Q2 and the gate of the MOS tube Q1 are all grounded.
[0009] In one embodiment, a resistor R9 is connected between the collector of the transistor Q3 and the base of the transistor Q2.
[0010] In one embodiment, a resistor R5 is connected between the base of the transistor Q2 and the voltage input terminal.
[0011] In one embodiment, the collector of the transistor Q2 and the gate of the MOS transistor Q1 are both connected to one end of a resistor R10, and the other end of the resistor R10 is grounded.
[0012] In one embodiment, the OOK signal carrier modulation chip includes a chip U1, and the drain of the MOS tube Q1 is connected to a voltage input pin of the chip U1.
[0013] The above one or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
[0014] A switch circuit provided in an embodiment of the utility model includes: an AISG2.0 power supply input circuit, a voltage divider circuit, a first switch tube unit, a second switch tube unit, a third switch tube unit and an OOK signal carrier modulation chip. If the AISG2.0 protocol has signal communication, the voltage divider circuit detects that the AISG2.0 power supply input circuit has voltage input, and the voltage will be sent to the third switch tube unit and control it to turn on. Subsequently, the third switch tube unit will control the second switch tube unit to turn on, and finally the second switch tube unit controls the first switch tube unit to turn off. In this way, the first switch tube unit has no voltage output to the OOK signal carrier modulation chip, so that it has no OOK signal output. Conversely, if the AISG2.0 protocol has no signal communication, the voltage divider circuit detects the "0V" voltage of the AISG2.0 power supply input circuit, then it will control the third switch tube unit to turn off, and the third switch tube unit will turn off the second switch tube unit, and finally the second switch tube unit controls the first switch tube unit to turn on. Under this condition, the first switch tube unit will have voltage output to the OOK signal carrier modulation chip, so that the OOK signal resumes communication. The main function of the switching circuit of this design is to shut down the working power of the OOK signal carrier modulation chip during the AISG2.0 protocol signal communication process, and then change the OOK signal from the original waiting call state to a completely stopped state. In this way, the external communication of the antenna RET can dynamically choose one of the two external communications, and the two communication methods will not affect each other.
[0015] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] Figure 1 It is a schematic diagram of a circuit module in an embodiment of the utility model;
[0018] Figure 2 This is a schematic diagram of the AISG2.0 power supply input circuit principle in the embodiment of the utility model;
[0019] Figure 3 It is a schematic diagram of the circuit principle in the embodiment of the utility model;
[0020] Figure 4 This is a schematic diagram of the circuit principle of the OOK signal carrier modulation chip in an embodiment of the utility model.
[0021] Explanation of the reference numerals: 100, AISG2.0 power supply input circuit; 200, voltage divider circuit; 300, first switch tube unit; 400, second switch tube unit; 500, third switch tube unit; 600, OOK signal carrier modulation chip. DETAILED DESCRIPTION
[0022] The overall idea of the technical solution provided by the utility model is as follows:
[0023] See also Figure 1 The switching circuit includes: an AISG2.0 power supply input circuit 100, a voltage divider circuit 200, a first switch tube unit 300, a second switch tube unit 400, a third switch tube unit 500 and an OOK signal carrier modulation chip 600. The voltage divider circuit 200 is connected to the AISG2.0 power supply input circuit 100, the first switch tube unit 300 is connected to the voltage divider circuit 200, the second switch tube unit 400 is connected to the first switch tube unit 300, the third switch tube unit 500 is connected to the second switch tube unit 400, and the OOK signal carrier modulation chip 600 is connected to the third switch tube unit 500.
[0024] In the AISG2.0 signal communication process, the AISG2.0 power input circuit 100 is the main part that provides power supply for the entire remote electrical antenna (RET). Specifically, the AISG2.0 power input circuit 100 is used to receive and convert power from the AISG2.0 device to drive the circuits and components of the RET device. When the RET device communicates with the AISG2.0 device, the AISG2.0 power input circuit 100 will provide power for the operation of the RET.
[0025] The voltage divider circuit 200 is connected to the AISG2.0 power supply input circuit 100 to detect the voltage of the AISG2.0 power supply input circuit 100. If there is signal communication in the AISG2.0 protocol, the voltage divider circuit 200 detects that there is voltage input to the AISG2.0 power supply input circuit 100, and the voltage will be sent to the third switch tube unit 500 and control it to turn on. Subsequently, the third switch tube unit 500 will control the second switch tube unit 400 to turn on, and finally the second switch tube unit 400 will control the first switch tube unit 300 to turn off. In this way, the first switch tube unit 300 has no voltage output to the OOK signal carrier modulation chip 600, so that it has no OOK signal output. Conversely, if there is no signal communication in the AISG2.0 protocol, and the voltage divider circuit 200 detects the "0V" voltage of the AISG2.0 power supply input circuit 100, it will control the third switch tube unit 500 to turn off, and the third switch tube unit 500 will turn off the second switch tube unit 400, and finally the second switch tube unit 400 controls the first switch tube unit 300 to turn on. Under this condition, the first switch tube unit 300 will output a voltage to the OOK signal carrier modulation chip 600, so that the OOK signal resumes communication. The main function of the switch circuit of this design is to shut off the working power of the OOK signal carrier modulation chip during the AISG2.0 protocol signal communication process, and then change the OOK signal from the original waiting call state to completely stop working. In this way, the external communication of the antenna RET can be dynamically selected from two external communications, and the two communication methods will not affect each other.
[0026] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0027] See also Figure 2The AISG2.0 power supply input circuit 100 includes: a capacitor C101, a capacitor C102, a gas discharge tube G102, an inductor L101, an inductor L102, a transient voltage suppression diode D104, a transient voltage suppression diode D105, a thermistor RPTC102 and a diode D110, wherein the capacitor C101 and the capacitor C102 are connected in parallel with the gas discharge tube G102, the gas discharge tube G102 is connected in parallel with the inductor L101 and the inductor L102, the other ends of the inductors L101 and L102 are connected to a parallel route formed by the transient voltage suppression diode D104 and the transient voltage suppression diode D105, the thermistor RPTC102 and the diode D110 are connected in parallel and connected to a parallel route formed by the transient voltage suppression diode D104 and the transient voltage suppression diode D105. Specifically, the power supply first filters out electromagnetic noise and interference through capacitors C101 and C102, which plays the role of initial power supply filtering. The gas discharge tube G102 is used to quickly conduct when the voltage suddenly increases, short-circuit the high voltage, and play the role of overvoltage protection. Inductors L101 and L102 further filter out noise from the power line. Then transient voltage suppression diodes D104 and transient voltage suppression diodes D105 provide secondary overvoltage protection for the circuit. Thermistor RPTC102 is used to limit the flow of excessive current to achieve current overload protection. Diode D110 is used to avoid the flow of reverse current and reduce the forward voltage drop to provide a suitable voltage for the equipment. Finally, a stable and safe power supply is output from the AISG1_VDD pin to provide power for the operation of RET.
[0028] See also Figure 3 , the voltage divider circuit 200 includes a resistor R11, a resistor R12, and a resistor R13, wherein one end of the resistor R11 is used to connect to the AISG2.0 power supply input circuit 100, the other end of the resistor R11 is connected to one end of the resistor R12 and the resistor R13, the other end of the resistor R12 is connected to the third switch tube unit 500, and the other end of the resistor R13 is grounded. Specifically, the resistors R11, R12, and R13 receive the voltage from the AISG2.0 power supply input circuit 100, and then divide the voltage and provide it to the third switch tube unit 500.
[0029] Furthermore, the voltage divider circuit 200 also includes a capacitor C14, which is connected in parallel with the resistor R13. The capacitor C14 is connected in parallel with the resistor R13, and can store electric energy in the circuit. When the circuit power supply is unstable, the stored electric energy can be released to maintain the normal operation of the circuit. At the same time, the capacitor C14 can also play a filtering role, filtering out the AC component in the power supply and reducing interference to the circuit.
[0030] See also Figure 3The first switch tube unit 300 includes a MOS tube Q1, the second switch tube unit 400 includes a transistor Q2, and the third switch tube unit includes a transistor Q3. The base of the transistor Q3 is connected to the voltage divider circuit 200, the collector of the transistor Q3 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the source of the MOS tube Q1, the drain of the MOS tube Q1 is connected to the OOK signal carrier modulation chip 600, the collector of the transistor Q3, the base of the transistor Q2 and the source of the MOS tube Q1 are connected to the voltage input terminal, and the emitter of the transistor Q3, the collector of the transistor Q2 and the gate of the MOS tube Q1 are all grounded. Specifically, if the AISG2.0 protocol has signal communication, the voltage divider circuit 200 detects that the AISG2.0 power supply input circuit 100 has voltage input, and the voltage will be sent to the base of the transistor Q3, so that the base and emitter of the transistor Q3 are turned on. At this time, the base voltage of the transistor Q2 is "0V" low level, so that the transistor Q2 is turned on. At this time, the voltages at both ends of the MOS tube Q1 are equal, the MOS tube Q1 is turned off, and the drain pin voltage of the MOS tube Q1 is "0V", and the voltage of the OOK signal carrier modulation chip 600 connected to it is "0V". , so that the OOK signal has no output; on the contrary, if there is no signal communication in the AISG2.0 protocol, the voltage divider circuit 200 detects that a "0V" voltage is input to the base of the transistor Q3, so that the base and emitter of the transistor Q3 are closed, and the base voltage of the transistor Q2 is the voltage of the voltage input terminal, such as 3.3V, so that the transistor Q2 is closed, and the gate of the MOS tube Q1 is a low level. At this time, the MOS tube Q1 is turned on, and the drain of the MOS tube Q1 outputs the voltage transmitted from the voltage output terminal to the OOK signal carrier modulation chip 600, so that the OOK signal communication is restored.
[0031] For further information, see Figure 3 , a resistor R9 is connected between the collector of the transistor Q3 and the base of the transistor Q2, a resistor R5 is connected between the base of the transistor Q2 and the voltage input terminal, the collector of the transistor Q2 and the gate of the MOS transistor Q1 are both connected to one end of the resistor R10, and the other end of the resistor R10 is grounded. It can be understood that the resistors R5, R9 and R10 play the role of voltage stabilization and current limiting.
[0032] See also Figure 4 The OOK signal carrier modulation chip 600 includes a chip U1, and the drain of the MOS tube Q1 is connected to the voltage input pin of the chip U1. It can be understood that the chip U1 will perform corresponding OOK signal communication according to the voltage input to the drain of the MOS tube Q1. For example, if the drain of the MOS tube Q1 inputs a "0V" voltage, the chip U1 has no OKK signal output. If the drain of the MOS tube Q1 inputs a "3.3" voltage, the chip U1 has an OKK signal output.
[0033] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.
[0034] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A switching circuit, characterized in that: include: AISG2.0 power supply input circuit, voltage divider circuit, first switch tube unit, second switch tube unit, third switch tube unit and OOK signal carrier modulation chip, the voltage divider circuit is connected to the AISG2.0 power supply input circuit, the first switch tube unit is connected to the voltage divider circuit, the second switch tube unit is connected to the first switch tube unit, the third switch tube unit is connected to the second switch tube unit, and the OOK signal carrier modulation chip is connected to the third switch tube unit.
2. A switch circuit according to claim 1, characterized in that: The AISG2.0 power supply input circuit includes: capacitor C101, capacitor C102, gas discharge tube G102, inductor L101, inductor L102, transient voltage suppression diode D104, transient voltage suppression diode D105, thermistor RPTC102 and diode D110, wherein the capacitor C101 and capacitor C102 are connected in parallel with the gas discharge tube G102, the gas discharge tube G102 is connected in parallel with the inductor L101 and the inductor L102, the other ends of the inductors L101 and L102 are connected to the parallel route formed by the transient voltage suppression diode D104 and the transient voltage suppression diode D105, the thermistor RPTC102 and the diode D110 are connected in parallel and connected to the parallel route formed by the transient voltage suppression diode D104 and the transient voltage suppression diode D105.
3. A switch circuit according to claim 1, characterized in that: The voltage divider circuit includes a resistor R11, a resistor R12 and a resistor R13, wherein one end of the resistor R11 is used to connect to the AISG2.0 power supply input circuit, the other end of the resistor R11 is connected to the resistor R12 and one end of the resistor R13, the other end of the resistor R12 is connected to the third switch tube unit, and the other end of the resistor R13 is grounded.
4. A switch circuit according to claim 3, characterized in that: The voltage divider circuit further includes a capacitor C14, and the capacitor C14 is connected in parallel with the resistor R13.
5. A switch circuit according to claim 1, characterized in that: The first switch tube unit includes a MOS tube Q1, the second switch tube unit includes a triode Q2, and the third switch tube unit includes a triode Q3. The base of the triode Q3 is connected to the voltage divider circuit, the collector of the triode Q3 is connected to the base of the triode Q2, the emitter of the triode Q2 is connected to the source of the MOS tube Q1, the drain of the MOS tube Q1 is connected to the OOK signal carrier modulation chip, the collector of the triode Q3, the base of the triode Q2 and the source of the MOS tube Q1 are connected to the voltage input terminal, and the emitter of the triode Q3, the collector of the triode Q2 and the gate of the MOS tube Q1 are all grounded.
6. A switch circuit according to claim 5, characterized in that: A resistor R9 is connected between the collector of the transistor Q3 and the base of the transistor Q2.
7. A switch circuit according to claim 5, characterized in that: A resistor R5 is connected between the base of the transistor Q2 and the voltage input terminal.
8. A switch circuit according to claim 5, characterized in that: The collector of the transistor Q2 and the gate of the MOS transistor Q1 are both connected to one end of a resistor R10, and the other end of the resistor R10 is grounded.
9. A switch circuit according to claim 5, characterized in that: The OOK signal carrier modulation chip includes a chip U1, and the drain of the MOS tube Q1 is connected to the voltage input pin of the chip U1.