Semiconductor device

Abstract

A semiconductor device is provided. An exemplary semiconductor device includes an isolation layer over a semiconductor material; a plurality of source / drain regions over the isolation layer; and an isolation structure in a trench of the semiconductor material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting more increasingly complex and sophisticated functions. Thus, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, this demand has been met in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of the semiconductor manufacturing process. Thus, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Multi-gate devices have been introduced in an attempt to improve gate control, reduce off-state current, and reduce short-channel effect (SCE) by increasing gate-channel coupling. One such multi-gate device that has been introduced is the field-effect transistor (FinFET). FinFETs derive their name from the fin-like structure that extends from the substrate on which they are formed and is used to form the FET channel. Another multi-gate device that has been introduced, in part to address the performance challenges associated with FinFETs, is the gate-all-around (GAA) transistor. GAA devices derive their name from the gate structure that extends completely around the channel, providing better electrostatic control than FinFETs. FinFET devices and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. In addition, the three-dimensional structure of such devices allows them to be aggressively scaled down while maintaining gate control and mitigating SCE. Utility Model Content

[0004] In some embodiments, a semiconductor device includes an isolation layer disposed above a semiconductor material; a plurality of source / drain regions disposed above the isolation layer; and an isolation structure disposed in a trench of the semiconductor material.

[0005] In another embodiment, a semiconductor device is provided, and the semiconductor device includes: a multi-gate structure located above a semiconductor substrate; an isolation structure laterally separated from the multi-gate structure, wherein the isolation structure is located in a trench in the semiconductor substrate; and an isolation layer covering the semiconductor substrate and extending from the multi-gate structure to the isolation structure.

[0006] In another embodiment, a semiconductor device includes: a first gate structure and a second gate structure located above a semiconductor material; an isolation structure located between the first gate structure and the second gate structure; a first source / drain region located between the first gate structure and the isolation structure, wherein the first source / drain region is separated from the semiconductor material by a first isolation layer; and a second source / drain region located between the second gate structure and the isolation structure, wherein the second source / drain region is separated from the semiconductor material by a second isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a plan view of a layout of a multi-gate device according to some embodiments;

[0009] Figure 2 A flowchart illustrating a method according to some embodiments;

[0010] Figures 3 to 7 is a perspective view of a multi-gate device during successive manufacturing stages according to some embodiments;

[0011] Figures 8 to 19 During the continuous manufacturing phase according to some embodiments Figure 7 A cross-sectional view of a multi-gate device;

[0012] Figure 20 to Figure 21 According to some embodiments Fig.18 a focused cross-sectional view of a portion of a multi-gate device;

[0013] Fig. 22 is a cross-sectional view of a multi-film isolation layer according to some embodiments;

[0014] Figure 23 to Figure 25 During the continuous manufacturing phase according to some embodiments Fig. 9 Cross-sectional view of a multi-gate device.

[0015]

Explanation of symbols

[0016] 8-8: Line

[0017] 10. 202: Substrate

[0018] 11: Lattice unit

[0019] 20: Parallel active area

[0020] 30: Gate line

[0021] 40: Isolation

[0022] 100, 200: device

[0023] 201: Surface

[0024] 212: Epitaxial stacking

[0025] 214, 216: Layer

[0026] 217, 225, 226, 227: Mask layer

[0027] 218: First mask layer

[0028] 219: Second mask layer

[0029] 220: Fins

[0030] 220a: Part

[0031] 221: Shallow Trench Isolation Features

[0032] 222: Gate structure

[0033] 223: Sacrificial gate dielectric, sacrificial gate dielectric layer

[0034] 224: Sacrificial gate electrode layer

[0035] 230: Spacer

[0036] 231: Lining layer

[0037] 232: Main spacer layer

[0038] 233: Surface

[0039] 234: Grooves, gaps

[0040] 235: Fin fragment

[0041] 300: Isolation layer

[0042] 301: upper surface, top surface

[0043] 581, 583: upper surface

[0044] 302: Top surface

[0045] 310, 311, 312, 313, 314: sublayer

[0046] 400: Source / drain region

[0047] 401: Epitaxial Materials

[0048] 450: Dielectric

[0049] 499: Gate cavity

[0050] 500, 501, 502, 503: Gate structure

[0051] 540: gate dielectric layer, gate dielectric

[0052] 550: Gate electrode material

[0053] 560:Semiconductor Nanosheets

[0054] 561:Nanosheet

[0055] 562:Nanosheet

[0056] 563:Nanosheet

[0057] 570: Gate part

[0058] 571: Gate part

[0059] 572: Gate part

[0060] 573: Gate part

[0061] 590: Plane

[0062] 600: Patterned Hard Mask

[0063] 602: Opening

[0064] 700: Groove

[0065] 800: Isolation structure and materials

[0066] 810: Excess material

[0067] 820: Lowest point

[0068] 1000:Method

[0069] 2141: Bottom epitaxial layer

[0070] 2161: Slot

[0071] 2162:Internal spacer

[0072] 2169: Gap

[0073] H1, H2, H9, H10: Height

[0074] H3, H4, H5, H6, H7, H8: vertical height

[0075] L1, L2: Horizontal length

[0076] S1010, S1020, S1030, S1040, S1050, S1060, S1070, S1080, S1090, S1100, S1110, S1120, S1130, S1140, S1150, S1160, S1170, S1180, S1190, S1200: Operation

[0077] W1, W2, W3, W4, W5, W6, W7, W8: Width DETAILED DESCRIPTION

[0078] The following disclosure provides many different embodiments or examples for realizing the different features of the subject matter. The specific examples of the components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0079] Additionally, for ease of description, spatially relative terms such as "above," "overlying," "above," "upper," "top," "below," "underlying," "under," "beneath," "lower," "bottom," "side," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0080] In certain embodiments herein, a "material layer" is a layer comprising at least 50% by weight of the identified material (e.g., at least 60% by weight of the identified material, at least 75% by weight of the identified material, or at least 90% by weight of the identified material) or substantially 100% by weight of the identified material; and is a layer that is a "material" comprising at least 50% by weight of the identified material (e.g., at least 60% by weight of the identified material, at least 75% by weight of the identified material, or at least 90% by weight of the identified material) or substantially 100% by weight of the identified material. For example, in certain embodiments, each of the titanium nitride layer and the layer that is titanium nitride is a layer that is at least 50% by weight, at least 60% by weight, at least 75% by weight of titanium nitride, or at least 90% by weight, or substantially 100% by weight of titanium nitride.

[0081] For the sake of brevity, conventional techniques related to conventional semiconductor device manufacturing may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into a more comprehensive program or process with additional functionality not described in detail herein. In particular, the various processes for manufacturing semiconductor devices are well known, and therefore, for the sake of brevity, many conventional processes will only be briefly mentioned herein or will be omitted entirely without providing familiar process details. As will be readily apparent to those familiar with the art after a complete reading of this disclosure, the structures disclosed herein may be employed with various techniques and may be incorporated into various semiconductor devices and products. In addition, it should be noted that semiconductor device structures include different numbers of elements, and a single element shown in the description may represent multiple elements.

[0082] It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include P-type metal oxide semiconductor devices or N-type metal oxide semiconductor multi-gate devices. Specific examples may be presented herein and are referred to as FinFET devices due to their fin-like structures. An embodiment of a multi-gate transistor referred to as a gate-all-around (GAA) device is also presented herein. A GAA device includes any device having its gate structure or a portion thereof formed on four sides of a channel region (e.g., surrounding a portion of a channel region). The devices presented herein also include embodiments having a channel region disposed in a nanosheet channel, a nanowire channel, a strip channel, and / or other suitable channel configurations. In this article, the term "nanosheet channel" is intended to include nanowire channels and strip channel configurations.

[0083] Embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure are presented herein. However, one of ordinary skill in the art will recognize that the present teachings may be applied to a single channel (e.g., a single nanosheet) or any number of channels. One of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

[0084] As described herein, processes are performed to isolate adjacent devices. For example, vertically extending isolation structures are formed between adjacent devices and have a relatively shallow depth to provide reduced parasitic capacitance compared to vertically extending isolation structures that extend to a deeper depth. In addition, laterally extending isolation layers are formed between source / drain regions and underlying semiconductor material. Such laterally extending isolation layers reduce leakage current passing under the shallow vertically extending isolation structures. As used herein, "source / drain region" may refer to either a source region or a drain region, either alone or together, depending on the context.

[0085] In some embodiments, a continuous poly on diffusion edge (CPODE) process is used to provide an isolation structure between adjacent devices. For the purposes of the present disclosure, a "diffusion edge" may be equivalently referred to as an active edge, where, for example, the active edge is adjacent to an adjacent active region. In addition, the active region includes a region where a transistor structure (e.g., including a source, a drain, and a gate / channel structure) is formed. In some instances, the active region may be disposed between insulating regions. The CPODE process may provide an isolation structure between adjacent active regions by performing a dry etching process along the active edge (e.g., at the boundary of adjacent active regions) to form a cut region and by filling the cut region with a dielectric such as silicon nitride (SiN), and thereby providing adjacent transistors.

[0086] Prior to the CPODE process, the active edge may include a GAA dummy structure having a gate stack and a plurality of channels (e.g., nanosheet channels). The plurality of channels may each include a chemical oxide layer formed thereon, and a high-K dielectric / metal gate layer may be formed above the chemical oxide layer and between adjacent channels in the plurality of channels. In addition, internal spacers may be disposed between adjacent channels at lateral ends of the plurality of channels. In various examples, source / drain epitaxial (epi) layers of adjacent active regions are disposed on either side of the GAA dummy structure (formed at the active edge) such that the adjacent source / drain epi layers are in contact with the internal spacers and the plurality of channels of the GAA dummy structure.

[0087] In an exemplary embodiment, an isolation layer is formed before forming a source / drain epitaxial (epi) layer. Thus, each source / drain epi region is isolated from the underlying semiconductor material by a respective portion of the isolation layer. With the isolation provided by the isolation layer, the vertically extended isolation structure can be provided with a shallow depth to reduce parasitic capacitance while substantially reducing leakage current through the semiconductor material below the isolation structure.

[0088] The embodiments of the present disclosure provide advantages over existing technologies, but it should be understood that other embodiments may provide different advantages, but not all advantages must be discussed herein, and not all embodiments require specific advantages. For example, the embodiments discussed herein include structures and related methods for performing CPODE processes.

[0089] In various embodiments, as described above, a GAA dummy structure may be formed at an active edge (eg, at a boundary of adjacent active regions) with isolation layers and overlying source / drain epi layers of adjacent active regions disposed on either side of the GAA dummy structure.

[0090] For the purpose of the following discussion, Figure 1 A simplified top-down layout diagram of a semiconductor device 100, such as a multi-gate device 100, is provided. In various embodiments, the multi-gate device 100 may include a FinFET device, a GAA transistor, or other types of multi-gate devices. The multi-gate device 100 is formed above a substrate 10. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate. The substrate 10 may include various layers formed on the semiconductor substrate, including conductive or insulating layers. As is known in the art, the substrate 10 may include various doping configurations depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 10 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 10 may optionally include an epi layer, may be strained to achieve performance enhancement, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0091] Figure 1 A lattice cell 11 is illustrated, i.e., a portion of a semiconductor substrate 10. As shown, parallel active regions 20 are spaced apart from each other and extend in the X direction. Additionally, parallel gate lines 30 are spaced apart from each other and extend in the Y direction perpendicular to the X direction. Exemplary gate lines 30 are formed of a conductive material such as a metal and form a gate structure of the multi-gate device 100.

[0092] like Figure 1As further shown in FIG. 4 , a cut region or trench is formed in one gate line 30 and filled with an isolation 40. As described below, this isolation 40 can isolate adjacent devices from each other.

[0093] refer to Figure 2 , which describes a method 1000 for fabricating a semiconductor device 200 (such as a multi-gate device) using a CPODE process according to various embodiments. The method 1000 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, bar-shaped) and sizes. However, it should be understood that various aspects of the method 1000 (including the disclosed CPODE process) may be equally applied to other types of multi-gate devices without departing from the scope of the present disclosure. In some embodiments, the method 1000 may be used to fabricate the GAA device described above with reference to the CPODE process. Figure 1 The multi-gate device 100 is described. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 may also be applied to the method 1000. It should be understood that the method 1000 includes steps that are characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus will only be briefly described herein. In addition, additional steps may be performed before, after, and / or during the method 1000.

[0094] Reference below Figures 3 to 7 and Figure 8 The following figures describe method 1000. Figures 3 to 7 A perspective view of a multi-gate device 200 is provided. Figure 8 The following figures provide a multi-gate device 200 along with Figure 1 A cross-sectional view taken along a plane substantially parallel to the plane defined by the x-axis in FIG. 1 , illustrating various manufacturing stages according to method 1000 .

[0095] In addition, the semiconductor device 200 may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM) and / or other logic circuits, etc., but are simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the semiconductor device 200 includes a plurality of semiconductor devices (e.g., transistors) that may be interconnected, including PFETs, NFETs, etc. In addition, it should be noted that the process steps of the method 1000 (including any description given with reference to the various figures) are merely exemplary and are not intended to be limited beyond the content specifically described in the attached claims.

[0096] In operation S1010, the method 1000 provides a substrate 202 such as Figure 3 . In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various layers formed on the semiconductor substrate, including conductive or insulating layers. As is known in the art, substrate 202 may include various doping configurations depending on design requirements. For example, different doping profiles (e.g., p-well, n-well) may be formed on substrate 202 in regions designed for different device types (e.g., n-type field effect transistor (NFET), p-type field effect transistor (PFET)). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for the p-well and phosphorus (P) for the n-well. In some embodiments, substrate 202 includes a single crystalline semiconductor layer at least on a portion of its surface. Substrate 202 may include single crystalline semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In the illustrated embodiment, the substrate 202 is made of crystalline Si.

[0097] like Figure 3 As shown in FIG. 1 , in operation S1020, method 1000 ( Figure 2 ) forms one or more epitaxial layers over substrate 202. In some embodiments, an epitaxial stack 212 is formed over substrate 202. Epitaxial stack 212 includes an epitaxial layer 214 of a first component interposed by an epitaxial layer 216 of a second component. The first component and the second component may be different. Embodiments are possible, including those providing first and second components with different oxidation rates and / or etch selectivities. In an embodiment, epitaxial layer 214 is SiGe and epitaxial layer 216 is silicon. In embodiments where epitaxial layer 214 includes SiGe and epitaxial layer 216 includes silicon, the silicon oxidation rate is less than the SiGe oxidation rate. It should be noted that in Figure 3 2. The three epitaxial layers 214 and the three epitaxial layers 216 are illustrated in FIG. 2 for illustrative purposes only and are not intended to be limiting beyond the specific description in the claims. It is understood that any number of epitaxial layers may be formed in the epitaxial stack 212; the number of layers depends on the desired number of channel regions of the GAA device 200. In some embodiments, the number of epitaxial layers 216 is between two and ten, such as six or seven.

[0098] In some embodiments, the epitaxial layer 214 has a thickness ranging from about 5 nm to about 15 nm. The epitaxial layer 214 can be substantially uniform in thickness. In some embodiments, the epitaxial layer 216 has a thickness ranging from about 5 nm to about 15 nm. In some embodiments, the stacked epitaxial layer 216 is substantially uniform in thickness. As described in more detail below, the epitaxial layer 216 can be used as a channel region of a subsequently formed multi-gate device and has a thickness selected based on device performance considerations. The epitaxial layer 214 can be used to define a gap between adjacent channel regions for a subsequently formed multi-gate device and has a thickness selected based on device performance considerations.

[0099] As an example, epitaxial growth of epitaxial stack 212 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth process. In some embodiments, epitaxial growth layers such as epitaxial layer 216 include the same material as substrate 202. In some embodiments, epitaxial growth layers 214 and 216 include a different material than substrate 202. As described above, in at least some embodiments, epitaxial layer 214 includes epitaxially grown Si 1-x Ge x The epitaxial layers 214 and 216 may include epitaxially grown silicon (Si) layers (where x is from about 10% to about 55%). Alternatively, in some embodiments, any of the epitaxial layers 214 and 216 may include other materials such as germanium, compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed, the materials of the epitaxial layers 214 and 216 may be selected based on providing different oxidation and etching selectivity characteristics. In various embodiments, the epitaxial layers 214 and 216 are substantially free of dopants (i.e., have a dopant content of from about 0 cm -3 About 1×10 17 cm -3 In some embodiments, the epitaxial stack 212 has a Si layer and a SiGe layer (not shown). In an alternative embodiment, the epitaxial stack 212 has a Si layer and a SiGe layer (not shown).

[0100] like Figure 3 to Figure 4 As shown in FIG. 10 , in operation S1030 , method 1000 ( Figure 2) patterning the epitaxial stack 212 to form the semiconductor fin 220. In some embodiments, operation S1030 includes forming a mask layer 217 above the epitaxial stack 212, such as Figure 3 . The mask layer 217 includes a first mask layer 218 and a second mask layer 219. The exemplary first mask layer 218 is a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The exemplary second mask layer 219 is made of silicon nitride (SiN), which can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, wherein the chemical vapor deposition includes low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD). The mask layer 217 is patterned into a mask pattern by using a patterning operation including photolithography and etching. Operation S1030 then patterns the epitaxial stack 212 in an etching process such as dry etching (eg, reactive ion etching), wet etching, and / or other suitable processes through the openings defined in the patterned mask layer 217. The stacked epitaxial layers 214 and 216 are thereby patterned into the fins 220. Figure 4 One fin 220 is illustrated as being formed, but any suitable number of fins may be formed. Trench 220 is etched between adjacent fins 220 .

[0101] In various embodiments, each fin 220 includes an upper portion of the interleaved epitaxial layers 214 and 216 and a bottom portion formed by etching the substrate 202. Each fin 220 protrudes upward from the substrate 202 in the z-direction and extends longitudinally in the y-direction. The sidewalls of each fin 220 may be straight or sloped (not shown). Figure 4 In the embodiment of the present invention, the additional fins will be spaced apart along the x-direction. The fins 220 may have the same width or different widths.

[0102] like Figure 5 As shown in FIG. 1 , in operation S1040, method 1000 ( Figure 2) forms a shallow trench isolation (STI) feature (also referred to as STI feature) 221 in a trench adjacent to each fin 220 having a dielectric layer. The STI feature 221 may be formed by first filling the trench around each fin 220 with a dielectric material layer to cover the top surface and sidewalls of the fin 220 (not shown). The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-K dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating techniques. The dielectric material layer is then planarized by using, for example, chemical mechanical planarization (CMP) until the top surface of the mask layer 217 is exposed and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (also referred to as STI feature) 221, as shown in FIG. Figure 5 In the illustrated embodiment, STI features 221 are formed on substrate 202. Any suitable etching technique may be used to recess the isolation features 221, including dry etching, wet etching, RIE, and / or other etching methods, and in an exemplary embodiment, an anisotropic dry etch is used to selectively remove the dielectric material of the isolation features 221 without etching the fins 220. Mask layer 217 ( Figure 4 ) may also be removed before, during, and / or after recessing the isolation feature 221. In some embodiments, the mask layer 217 is removed by a CMP process performed before recessing the isolation feature 221. In some embodiments, the mask layer 217 is removed by an etchant used to recess the isolation feature 221.

[0103] like Figure 6 As shown in FIG. 1 , in operation S1050, method 1000 ( Figure 2 ) to form a sacrificial (dummy) gate structure 222. The sacrificial gate structure 222 is formed over a portion of the fin 220 that will become the channel region. The sacrificial gate structure 222 may extend over a plurality of adjacent fins (not shown). The sacrificial gate structure 222 is directly over and defines the channel regions of the GAA device to be formed. Each of the sacrificial gate structures 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 over the sacrificial gate dielectric 223. As shown, the gate structures 222 extend longitudinally in the x-direction and are spaced apart in the y-direction.

[0104] The sacrificial gate structure 222 is formed by first blanket depositing a sacrificial gate dielectric layer over the fin 220. A sacrificial gate electrode layer is then blanket deposited over the sacrificial gate dielectric layer and over the fin 220. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer is in a range of about 100 nm to about 200 nm. The sacrificial gate electrode layer 224 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in a range of about 1 nm to about 5 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable processes, the CVD including LPCVD and PECVD. A mask layer 225 is formed over the sacrificial gate electrode layer. The mask layer 225 may include a mask layer 226 such as silicon oxide and a mask layer 227 such as silicon nitride. Subsequently, the mask layer 225 is patterned to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into a sacrificial gate structure 222 . The sacrificial gate structure 222 includes a sacrificial gate dielectric layer 223 and a sacrificial gate electrode 224 .

[0105] As shown, the fin 220 is partially exposed between the sacrificial gate structure 222 and on opposite sides thereof, thereby defining a source / drain (S / D) region. In the present disclosure, source and drain are used interchangeably and their structures are substantially the same.

[0106] Still refer to Figure 6 In operation S1060, method 1000 ( Figure 2 ) Spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and the sidewalls of the fin 220 by depositing a spacer material and then etching. The spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each of the spacers 230 includes a plurality of layers, such as a liner layer 231 and a main spacer layer 232 located on the sidewalls of the liner layer 231.

[0107] As an example, the spacer 230 may be formed by depositing a spacer material including a liner material layer and a dielectric material layer over the sacrificial gate structure 222 using a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes.

[0108] like Figure 7As shown in FIG. 1 , after depositing the liner material layer and the dielectric material layer, in operation S1070, etching back (e.g., anisotropically) to expose and remove a portion 220a (e.g., S / D region) of the fin 220 adjacent to the sacrificial gate structure 222 and not covered by the sacrificial gate structure 222. The liner material layer and the dielectric material layer may be retained on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230, and retained on the sidewalls of the fins as fin sidewall spacers 230. In some embodiments, the etching back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The spacer 230 may have a thickness ranging from about 5 nm to about 20 nm.

[0109] Cross Reference Figure 7 and Figure 8 , along Figure 7 The cross-sectional view is taken along line 8-8 in FIG. 1 . In operation S1070 , method 1000 ( Figure 2 ) The portion of the fin 220 not covered by the sacrificial gate structure 222 is recessed to form a gap or groove 234 in the S / D region. It should be noted that Figure 7 Only one sacrificial gate structure 222 and the adjacent portion of the fin 220 are shown so that the structure can be more clearly seen. Figure 6 The S / D regions between the sacrificial gate structures 222 are etched. Figure 8 Along the Figure 7 8 , but illustrates three sacrificial gate structures 222 and the fins 220 located below the sacrificial gate structures 222 .

[0110] like Figure 8 As more clearly shown in FIG. 1 , the stacked epitaxial layers 214 and 216 are etched to the bottom gap surface 233 formed by the fin 220. In many embodiments, operation S1070 forms the gap 234 by a suitable etching process such as a dry etching process, a wet etching process, or a combination thereof. As a result of the etching process, the fin segments 235 of the upper portion of the fin 220 are defined and separated from each other by the gap 234.

[0111] like Figure 8 As further shown in the method 1000 ( Figure 2 ) includes laterally etching the epitaxial layer 216 of the second composition in operation S1080. In an exemplary embodiment, the SiGe etch-back process is removed to laterally recess the layer 216. Thus, the groove cavity 2161 is formed to be laterally adjacent to the layer 216 and vertically adjacent to the layer 214.

[0112] like Fig. 9 As shown in , method 1000( Figure 2) includes forming an inner spacer 2162 in a groove cavity 2161 laterally adjacent to the epitaxial layer 216 in operation S1090. In an exemplary embodiment, the inner spacer 2162 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbide oxynitride, and / or other suitable dielectric materials. The inner spacer 2162 may be formed by ALD or any other suitable method. As shown, after the material forming the inner spacer 2162 is deposited, the material may be trimmed from the sidewalls of the epitaxial layer 214.

[0113] refer to Fig.10 As shown in , method 1000( Figure 2 ) In operation S1100, an isolation layer 300 is continuously formed over the semiconductor substrate 202. Specifically, the isolation layer 300 is formed on the bottom surface 233 of the gap 234. In an exemplary embodiment, the isolation layer 300 is formed by an atomic layer deposition (ALD) process.

[0114] As shown, the isolation layer 300 may completely cover the bottom gap surface 233 , leaving portions of the semiconductor substrate 202 between the bottom inner spacers 2162 uncovered. Thus, each portion of the isolation layer 300 extends from one gate structure 222 to an adjacent gate structure 222 .

[0115] In an exemplary embodiment, the isolation layer 300 is a dielectric material having a large energy band gap. For example, the isolation layer 300 may be formed of a material having an energy band gap of at least 4 eV, such as at least 4.5 eV, at least 5 eV, at least 5.5 eV, at least 6 eV, at least 6.5 eV, at least 7 eV, at least 7.5 eV, at least 8 eV, at least 8.5 eV, or at least 8.9 eV.

[0116] In some embodiments, the isolation layer 300 is formed of silicon nitride (SiN) and has an energy band gap of about 5 eV. In some embodiments, the isolation layer 300 is formed of silicon oxide (SiO) and has an energy band gap of about 8.9 eV. In an exemplary embodiment, the isolation layer 300 is formed of silicon oxide, silicon nitride, or a combination thereof.

[0117] In an exemplary embodiment, the isolation layer includes multiple sub-layers, so that the isolation layer is a multi-film structure. Such sub-layers can be deposited separately. As described below, the thickness and order of the sub-layers within the multi-film structure can be designed to provide a desired band gap, a desired dielectric constant, and promote epitaxial growth of materials used to form source / drain regions above the isolation layer.

[0118] In an exemplary embodiment, the isolation layer 300 has a small dielectric constant (or relative permittivity). In an exemplary embodiment, the isolation layer has a dielectric constant less than 10 (such as less than 7.5, less than 5, or less than 4).

[0119] In an exemplary embodiment, the upper surface 301 of the isolation layer 300 is located at a height H1 above the groove or lowest point of the bottom surface 233 of the semiconductor substrate 202. In certain embodiments, the isolation layer 300 may have a vertical thickness in the z-direction equal to the height H1.

[0120] In exemplary embodiments, height H1 is less than 10 nanometers, such as less than 9 nm, less than 8 nm, less than 7 nm, less than 6 nm, less than 5 nm, or less than 4 nm. Height H1 may be at least 3 nm, such as at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, or at least 9 nm.

[0121] As shown, the lowest or bottom epitaxial layer 2141 of the first composition has an uppermost or top surface 302 that is located at a height H2 above the groove or lowest point of the bottom surface 233 of the semiconductor substrate 202. In an exemplary embodiment, the height H1 of the top surface 301 of the isolation layer 300 is less than the height H2 of the top surface 302 of the bottom epitaxial layer 2141.

[0122] Although Figures 9 and 10 The isolation layer 300 is described as being formed after forming the inner spacer 2162, but it should be carefully considered that this layer is formed simultaneously with the inner spacer 2162. For example, Fig.11 It is explained that the inner spacer 2162 is formed in the groove cavity 2161 laterally adjacent to the epitaxial layer 216 in operation S1090 and the isolation layer 300 is formed on the semiconductor substrate 202 in operation S1100. Specifically, the layer for forming the isolation layer 300 is formed on the bottom surface 233 of the gap 234, and the same layer is formed in the groove cavity 2161 laterally adjacent to the epitaxial layer 216. In an exemplary embodiment, the inner spacer 2162 and the isolation layer 300 are formed as a continuous layer by an atomic layer deposition (ALD) process. In an exemplary embodiment, the material forming the inner spacer 2162 and the isolation layer 300 can be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbide oxynitride, and / or other suitable dielectric materials. As shown, after the material forming the layer 300 and the inner spacer 2162 is deposited, the material can be trimmed from the sidewall of the epitaxial layer 214.

[0123] Similar to Fig.10 In the embodiment of Fig.11, the isolation layer 300 may completely cover the bottom gap surface 233, so that the portion of the semiconductor substrate 202 between the bottom internal spacers 2162 is not covered. Therefore, each portion of the isolation layer 300 extends from one gate structure 222 to an adjacent gate structure 222. In an exemplary embodiment, the isolation layer 300 is a dielectric material having a large energy band gap. For example, the isolation layer 300 may be formed of a material having an energy band gap of at least 4 eV (such as at least 4.5 eV, at least 5 eV, at least 5.5 eV, at least 6 eV, at least 6.5 eV, at least 7 eV, at least 7.5 eV, at least 8 eV, at least 8.5 eV, or at least 8.9 eV). In some embodiments, the isolation layer 300 is formed of silicon nitride (SiN) and has an energy band gap of about 5 eV. In some embodiments, the isolation layer 300 is formed of silicon oxide (SiO) and has an energy band gap of about 8.9 eV. In an exemplary embodiment, the isolation layer 300 is formed of silicon oxide, silicon nitride, or a combination thereof. In an exemplary embodiment, the isolation layer 300 has a small dielectric constant (or relative dielectric constant). In an exemplary embodiment, the isolation layer has a dielectric constant of less than 10 (such as less than 7.5, less than 5, or less than 4). In an exemplary embodiment, the upper surface of the isolation layer 300 is located at a height above the groove or the lowest point of the bottom surface 233 of the semiconductor substrate 202, and the isolation layer 300 may have a vertical thickness equal to the height in the z direction. In an exemplary embodiment, the height of the layer 300 is less than 10 nanometers, such as less than 9nm, less than 8nm, less than 7nm, less than 6nm, less than 5nm, or less than 4nm. The height of the layer 300 may be at least 3nm, such as at least 4nm, at least 5nm, at least 6nm, at least 7nm, at least 8nm, or at least 9nm. In an exemplary embodiment, the height of the top surface of the isolation layer 300 is less than the height of the top surface of the bottom epitaxial layer.

[0124] Regardless of whether the inner spacer 2162 and the isolation layer 300 are formed by two different deposition processes or the inner spacer 2162 and the isolation layer 300 are formed simultaneously, the method may continue to form the source / drain region 400 in operation S1110, such as Fig.12 In an exemplary embodiment, the source / drain region 400 is formed by epitaxial growth. For example, operation S1110 may include selectively growing an epitaxial material over the isolation layer 300 to form the source / drain region 400. In an exemplary embodiment, the source / drain region 400 is a strained source / drain region 400.

[0125] The epitaxial material may include one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or one or more layers of Si, SiGe, Ge for p-channel FETs. For p-channel FETs, boron (B) may also be included in the source / drain. The source / drain epitaxial layer may be formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE).

[0126] exist Fig.13 In the embodiment of the present invention, the method 1000 includes forming a dielectric 450 over the source / drain region 400 in operation S1120. Specifically, the gap 234 is filled with the dielectric 450.

[0127] like Fig.13 As further shown in FIG. 1 , the method 1000 includes opening the sacrificial gate structure 222 in operation S1130 . Specifically, a chemical mechanical planarization (CMP) process may be performed to remove the mask layer 225 and expose the sacrificial gate electrode 224 .

[0128] like Fig.14 As shown in FIG. 1 , the method 1000 continues in operation S1140 by removing the sacrificial gate electrode 224 to form a gate cavity 499 . As shown, the gate cavity 499 is defined by the sidewall spacers 230 and the uppermost epitaxial layer 214 .

[0129] exist Fig.15 In operation S1150, the method 1000 removes the epitaxial layer 216 of the second composition. Thus, gaps 2169 are formed between the epitaxial layers 214 of the first composition. In this way, the epitaxial layers 214 of the first composition are formed into semiconductor nanosheets 560 that are vertically spaced apart.

[0130] exist Fig.16 In the method 1000 , in operation S1160 , a replacement metal gate process is performed to form gate structures 500 , such as gate structure 501 , gate structure 502 , and gate structure 503 .

[0131] In an exemplary embodiment, the replacement metal gate process includes forming a gate dielectric layer 540 in the gate cavity 499 and the gap 2169 and forming a gate electrode material 550 over the gate dielectric layer 540 to fill the gate cavity 499 and fill the gap 2169 .

[0132] An exemplary gate dielectric layer 540 is conformally deposited in the gate cavity 499 and the gap 2169. The gate dielectric 540 may be formed on the semiconductor nanosheets 560, and the gate electrode material 550 may be formed on the gate dielectric layer 540. Thus, each semiconductor nanosheet 560 is wrapped in the gate dielectric 540 and surrounded by the gate electrode material 550.

[0133] According to some embodiments, gate dielectric layer 540 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, gate dielectric layer 540 is a high-k dielectric material, and in these embodiments, gate dielectric layer 540 may have a k value greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of gate dielectric layer 540 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0134] A gate electrode material 550 is deposited over the gate dielectric layer 540 and fills the remainder of the gate cavity. The gate electrode material 550 may be a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof. For example, although a single gate electrode material is described, any number of work function regulating layers may be deposited.

[0135] like Fig.16 , the replacement metal gate process further includes removing excess portions of the gate dielectric layer 540 and the gate electrode material 550 located above the top surface of the ILD 450. For example, a planarization process such as a CMP process may be performed to remove excess portions of the gate dielectric layer 540 and the gate electrode material 550. The material of the gate dielectric layer 540 and the remaining portions of the gate electrode material 550 thus form a replacement gate structure 500 of the resulting device 200. The gate dielectric layer 540 and the gate electrode material 550 may be collectively referred to as a "gate", a "gate stack" or a "gate structure". Each gate structure 500 may extend along the sidewalls of the channel region of the fin structure.

[0136] After completing the replacement metal gate process, the method 1000 may continue to form an isolation structure to isolate adjacent devices.

[0137] For example, in Fig.17In the method 1000, operation S1170 is included, which includes forming a patterned mask covering the unselected structure. As an example, a photolithography and etching process can be performed to form a patterned hard mask 600 located above the gate structures 501 and 503, while the gate structure 502 is not covered by the patterned mask 600. Specifically, the patterned hard mask 600 defines an opening 602 covering the gate structure 502 that is selected to be removed.

[0138] Thereafter, the method 1000 includes, in operation S1180, performing a selective etching process to remove the selected gate structure 502, such as Fig.18 During the etching process, the metal gate material 550, the high-k gate dielectric 540, the semiconductor nanosheet 560, and a portion of the substrate 202 below the gate structure 502 are etched to form a trench 700 in the cut metal gate region. In various examples, the trench 700 can be etched using dry etching (e.g., reactive ion or plasma etching).

[0139] The etching process may include an initial selective deposition of a liner (not shown) over the hard mask 600. For example, a CH4 deposition process may be performed to selectively deposit a liner on the hard mask 600.

[0140] The exemplary etching process may be performed by any highly directional etching process that selectively etches silicon over silicon oxide or silicon nitride.

[0141] Exemplary etching processes include Si etching steps using highly selective etchants such as HBr-based plasmas, which can efficiently remove Si with less damage to internal spacers, which can be composed of silicon, carbon, nitrogen, and oxygen. The etching rate and selectivity can be adjusted by adding O2 or CO2 to the HBr plasma. During the etching process, a sidewall passivation step can be used to maintain the CD of the trench without being widened by the Si etching step. For example, a sidewall passivation step using SiCl4, HBr, and O2 precursors can be used to form a sidewall oxide for this purpose. In addition, to avoid etching being stopped by etching byproducts or oxide passivation layers, a penetration step using a low-selectivity etchant such as CF4 can be used to remove them.

[0142] like Fig.19 As shown in , the method 1000 continues with operation S1190 , which includes forming an isolation structure 800 in the trench 700 .

[0143] In an exemplary embodiment, a refill process is used to form an isolation material 800 over the structure 200. An exemplary material 800 is silicon nitride. The material 800 fills the previously formed trench 700 and electrically isolates the now adjacent gate structures 501 and 503 from each other. In some embodiments, the material 800 includes SiN. Alternatively, in some cases, the material 800 may include SiO2, silicon oxynitride, FSG, low-k dielectrics, combinations thereof, and / or other suitable materials known in the art. In various examples, the material 800 may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes. In some cases, after depositing the material 800, a chemical mechanical polishing (CMP) process may be performed to remove excess material 810 and planarize the top surface of the device 200.

[0144] Method 1000 may continue in operation S1200, where further processing may be performed. In general, further processing may form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) over substrate 202, which are used to connect various features to form functional circuits that may include one or more multi-gate devices. To facilitate the example, the multi-layer interconnect may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal lines. Various interconnect features may employ various conductive materials including copper, tungsten and / or silicide. In one example, a damascene and / or dual damascene process is used to form a copper-related multi-layer interconnect structure. In addition, additional process steps may be implemented before, during, and after method 1000, and some of the process steps described above may be replaced or eliminated according to various embodiments of method 1000.

[0145] Fig. 20 FIG. 8 is a focused view of the isolation structure 800 and the adjacent gate structure 503 in the trench 700. Fig. 20 , the device 200 has been planarized to remove Fig.19 Excess material 810 is shown in FIG.

[0146] As shown, the gate structure 503 is formed with three semiconductor nanosheets 560, a bottom or lowermost nanosheet 561, a middle nanosheet 562, and a top or uppermost nanosheet 563. Thus, the gate structure 503 includes a gate portion 570 located below the nanosheets 561, 562, and 563, respectively, and below the removed layer 214 ( Fig.14Specifically, the lowest or bottom gate portion 571 is directly below the lowest nanosheet 561 and contacts the semiconductor substrate 202 at the uppermost surface 201 of the semiconductor substrate 202; the middle gate portion 572 is directly below the middle nanosheet 562 and directly above the lowest nanosheet 561; and the uppermost or top gate portion 573 is directly below the uppermost nanosheet 563 and directly above the middle nanosheet 562.

[0147] As shown, the lowest gate portion 571 has an upper surface 581 located at a vertical height H3 above the uppermost surface 201 of the semiconductor substrate 202. In addition, the upper surface 581 of the lowest gate portion 571 is located at a height H2 above the bottom surface 233 of the isolation layer 300. In addition, the isolation layer 300 has a top surface 301 located at a height H1 above the bottom surface 233. As shown, the height H1 is less than the vertical height H2 of the upper surface 581 of the lowest gate portion 571. Disposing the upper surface 581 of the lowest gate portion 571 at a higher height than the top surface 301 of the isolation layer 300 avoids affecting the conductivity of epi.

[0148] As shown, uppermost nanosheet 563 has an upper surface 583 defining plane 590 and located at a vertical height H4 above uppermost surface 201 of semiconductor substrate 202. In an exemplary embodiment, vertical height H4 is 42nm to 46nm, such as 43.4nm to 44.9nm, with an average of 44.2nm.

[0149] As shown, uppermost nanosheet 563 and upper surface 583 of plane 590 are located at a vertical height H5 above upper surface 301 of isolation layer 300. In an exemplary embodiment, vertical height H5 is 38 nm to 43 nm, such as 39.3 nm to 41.3 nm, with an average of 40.3 nm.

[0150] exist Fig. 20 8, the trench 700 and the isolation structure 800 have a lowest point 820 or a lowest point 820 in the vertical or z-direction. The uppermost surface 201 of the semiconductor substrate 202 is located at a vertical height H6 above the lowest point 820.

[0151] In an exemplary embodiment, the vertical height H4 is greater than the vertical height H6. For example, the vertical height H6 may be less than 95% of the vertical height H4, such as less than 90% of the vertical height H4, less than 85% of the vertical height H4, less than 80% of the vertical height H4, less than 75% of the vertical height H4, less than 70% of the vertical height H4, less than 65% of the vertical height H4, less than 60% of the vertical height H4, less than 55% of the vertical height H4, or less than 50% of the vertical height H4.

[0152] Additionally, the upper surface 583 of the uppermost nanosheet 563 is located at a vertical height H7 above the lowest point 820. The vertical height H7 may be considered as the depth of the trench 700 as measured from the upper surface 583 of the uppermost nanosheet 563.

[0153] In exemplary embodiments, the vertical height H7 may be at least 60 nanometers (nm), such as at least 62 nm, at least 64 nm, at least 66 nm, at least 68 nm, at least 70 nm, at least 71 nm, at least 72 nm, at least 74 nm, at least 76 nm, at least 78 nm, at least 80 nm, at least 82 nm, at least 84 nm, or at least 86 nm.

[0154] In an exemplary embodiment, the vertical height H7 may be no greater than 120 nanometers (nm), such as no greater than 110 nm, no greater than 100 nm, no greater than 90 nm, such as no greater than 88 nm, no greater than 86 nm, no greater than 84 nm, no greater than 82 nm, no greater than 80 nm, no greater than 78 nm, no greater than 76 nm, no greater than 74 nm, no greater than 72 nm or no greater than 70 nm.

[0155] like Fig. 20 As shown in FIG. 1 , each source / drain region 400 is formed with a vertical height H8 extending from the bottommost surface and the uppermost surface of the source / drain region 400. In some exemplary embodiments, the vertical height H8 is less than the vertical height H7. In some exemplary embodiments, the vertical height H7 is less than the vertical height H8.

[0156] Similar to Fig. 20 , Fig.21 for Fig.19 A focused view of the isolation structure 800 and the adjacent gate structure 503 in the trench 700.

[0157] like Fig.21 As shown in FIG, the lowest or bottom gate portion 571 has a lateral width W1 in the Y direction. In an exemplary embodiment, the lateral width W1 is 14 nm to 19 nm, such as 14.5 nm to 17.9 nm, with an average of 16.4 nm.

[0158] like Fig.21 As shown in FIG. 5 , the middle gate portion 572 has a lateral width W2 in the Y direction. In an exemplary embodiment, the lateral width W2 is 12 nm to 18 nm, such as 12.8 nm to 17.0 nm, with an average value of 15.1 nm.

[0159] like Fig.21As shown in , the uppermost or top gate portion 573 has a lateral width W3 in the Y direction. In an exemplary embodiment, the lateral width W3 is 13 nm to 17 nm, such as 14.0 nm to 16.2 nm, with an average of 15.2 nm.

[0160] like Fig.21 As shown in FIG. 5 , the gate structure 503 above the uppermost nanosheet 563 has a lateral width W4 in the Y direction. In an exemplary embodiment, the lateral width W4 is 13 nm to 16 nm, such as 14.2 nm to 15.0 nm, with an average value of 14.6 nm.

[0161] Cross Reference Fig. 20 and Fig.21 , the device 200 may be formed with a gate structure 500 having a desired ratio of vertical height H4 to lateral widths W1, W2, W3, and W4, which are collectively referred to as gate widths GW. For example, the ratio of vertical height H4 to gate width GW may be (43.4 / 17.9=2.42) to (44.9 / 12.8=3.51).

[0162] In some embodiments, the ratio of the vertical height H4 to the gate width GW may be at least 2:1, at least 2.1:1, at least 2.2:1, at least 2.3:1, at least 2.4:1, at least 2.5:1, at least 2.6:1, at least 2.7:1, at least 2.8:1, at least 2.9:1, at least 3.1:1, at least 3.2:1, at least 3.3:1, at least 3.4:1, at least 3.5:1, at least 3.6:1, at least 3.7:1, at least 3.8:1, at least 3.9:1 or at least 4:1. In some embodiments, the ratio of the vertical height H4 to the gate width GW may be at most 2:1, at most 2.1:1, at most 2.2:1, at most 2.3:1, at most 2.4:1, at most 2.5:1, at most 2.6:1, at most 2.7:1, at most 2.8:1, at most 2.9:1, at most 3.1:1, at most 3.2:1, at most 3.3:1, at most 3.4:1, at most 3.5:1, at most 3.6:1, at most 3.7:1, at most 3.8:1, at most 3.9:1 or at most 4:1.

[0163] Return to reference Fig.21 , the trench 700 and the isolation structure 800 are formed with a lateral width W5 in the Y direction at the plane defined by the lowest nanosheet 561. In an exemplary embodiment, the lateral width W5 is 16 nm to 20 nm, such as 16.2 nm to 19.1 nm, with an average value of 17.7 nm.

[0164] Furthermore, the trench 700 and the isolation structure 800 are formed with a lateral width W6 in the Y direction at a plane defined by the middle nanosheet 562. In an exemplary embodiment, the lateral width W6 is 16 nm to 19 nm, such as 16.6 nm to 18.3 nm, with an average value of 17.5 nm.

[0165] Furthermore, the trench 700 and the isolation structure 800 are formed with a lateral width W7 in the Y direction at a plane defined by the uppermost nanosheet 563. In an exemplary embodiment, the lateral width W7 is 19 nm to 22 nm, such as 19.1 nm to 21.5 nm, with an average value of 20.2 nm.

[0166] Cross Reference Fig. 20 and Fig.21 , the device 200 may be formed with a desired ratio of the depth or vertical height H7 of the isolation structure 800 to the lateral widths W5, W6, W7, and W8, which are collectively referred to as the isolation width IW. For example, the ratio of the vertical height H7 to the isolation width IW may be (71.8 / 21.5=3.3) to (86.1 / 16.2=5.3). In some embodiments, the ratio of the vertical height H7 to the isolation width IW may be at least 2:1, at least 2.5:1, at least 2.75:1, at least 3:1, at least 3.1:1, at least 3.2:1, at least 3.3:1, at least 3.4:1, at least 3.5:1, at least 3.6:1, at least 3.7:1, at least 3.8:1, at least 3.9:1, at least 4:1, at least 4.1:1, at least 4.2:1, at least 4.3:1, at least 4.4:1, at least 4.5:1, at least 4.6:1, at least 4.7:1, at least 4.8:1, at least 4.9:1 or at least 5:1. In some embodiments, the ratio of the vertical height H7 to the isolation width IW may be at most 2:1, at most 2.5:1, at most 2.75:1, at most 3:1, at most 3.1:1, at most 3.2:1, at most 3.3:1, at most 3.4:1, at most 3.5:1, at most 3.6:1, at most 3.7:1, at most 3.8:1, at most 3.9:1, at most 4:1, at most 4.1:1, at most 4.2:1, at most 4.3:1, at most 4.4:1, at most 4.5:1, at most 4.6:1, at most 4.7:1, at most 4.8:1, at most 4.9:1 or at most 5:1.

[0167] like Fig.21, at the interface of the isolation layer 300 and the uppermost surface 201 of the semiconductor substrate 202, the isolation layer has a lateral length L1 in the Y direction. Specifically, the isolation layer 300 extends between the inner spacer 2162 of the gate structure 503 and the removed gate structure 502, thereby completely covering the surface 201 of the semiconductor substrate 202. In an exemplary embodiment, the lateral length L1 is 19 nm to 24 nm, such as 19.9 nm to 23.3 nm, with an average value of 21.4 nm.

[0168] like Fig.21 As shown in FIG, at the interface of the isolation layer 300 and the uppermost surface 201 of the semiconductor substrate 202, the trench 700 and the isolation structure 800 are separated from the conductive gate (i.e., the high-K / metal gate stack (gate dielectric layer 540 / gate electrode material 550)) of the gate structure 503 by a lateral length L2 in the Y direction. In an exemplary embodiment, the lateral length L2 is 22 nm to 34 nm, such as 25 nm to 32 nm, such as 26.8 nm to 30.7 nm, with an average value of 28.9 nm.

[0169] In an exemplary embodiment, the width W8 of the isolation structure 800 at the uppermost surface 201 of the semiconductor substrate 202 is smaller than the length L2 .

[0170] refer to Fig. 22 , a multi-film isolation layer 300 is shown. The isolation layer 300 illustrated includes four sub-layers 310, including sub-layers 311, 312, 313, and 314, but any suitable number may be used. As shown, the isolation layer 300 has a lateral length L1, and each sub-layer 310 has a lateral length L1. The material of each sub-layer 310 may be selected for a desired dielectric constant (or relative dielectric constant ε). In addition, the vertical thickness d of each sub-layer 310 may be selected. As shown, the sub-layers 310 may have different thicknesses, but it is contemplated that the sub-layers may have the same thickness.

[0171] The parasitic capacitance C is calculated using the equation C = εε0A / d, where ε is the relative dielectric constant of the material, ε0 is the relative dielectric constant of vacuum or free space, A is the area of ​​the material layer, and d is the thickness of the material layer. Therefore, given the same area A, reducing ε and increasing d will result in a reduction in parasitic capacitance. As can be appreciated, selecting a thickness and material of a particular relative dielectric constant can allow the parasitic capacitance of each sub-layer and the parasitic capacitance of the isolation layer 300 as a whole to be adjusted.

[0172] Although Figures 9 to 21 A method in which the isolation layer 300 is formed on the bottom surface 233 of the gap 234 is considered, but in some methods, an intermediate layer may be formed on the bottom surface 233 of the gap 234 .

[0173] For example, refer to Figure 23 to Figure 25 , such as in an operation after operation S1090, by forming an epitaxial material 401 on the bottom surface 233 of the gap 234 to process Fig. 9 structure. For example, the operation may include selectively growing epitaxial material over the bottom gap surface 233 formed by the fin 220. In an exemplary embodiment, the epitaxial material 401 may be considered as the lower portion of the source / drain region 400 formed later. The epitaxial material may include one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or one or more layers of Si, SiGe, Ge for p-channel FETs. For p-channel FETs, boron (B) may also be contained in the epitaxial material. The epitaxial material may be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE).

[0174] like Fig.23 As shown in FIG. 4 , the epitaxial material 401 covers the bottom gap surface 233 formed by the fins 220 and extends between the bottom internal spacers 2162 .

[0175] like Fig.23 As shown in FIG. 1 , after forming the epitaxial material 401, the method may continue to form the isolation layer 300 in operation S1100. Specifically, the isolation layer 300 is formed on the epitaxial material 401. In an exemplary embodiment, the isolation layer 300 is formed by an atomic layer deposition (ALD) process.

[0176] like Fig.24 As shown in FIG. 1 , forming the isolation layer 300 in operation S1100 includes trimming a portion of the deposited isolation layer 300 from the sidewall of the recess 234 and recessing the top surface 301. As shown, the isolation layer 300 may completely cover the epitaxial material 401. Specifically, the isolation layer 300 extends between the bottom inner spacers 2162.

[0177] exist Fig.24 , the upper surface 301 of the isolation layer 300 is located at a height H9 above the epitaxial material 401. In some embodiments, the isolation layer 300 may have a vertical thickness in the z-direction equal to the height H9.

[0178] In exemplary embodiments, height H9 is less than 10 nanometers, such as less than 9 nm, less than 8 nm, less than 7 nm, less than 6 nm, less than 5 nm, or less than 4 nm. Height H9 may be at least 3 nm, such as at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, or at least 9 nm.

[0179] As shown, the lowest or bottom epitaxial layer 2141 of the first composition has an uppermost or top surface 302 that is located at a height H10 above the epitaxial material 401. In an exemplary embodiment, the height H9 of the top surface 301 of the isolation layer 300 is less than the height H10 of the top surface 302 of the bottom epitaxial layer 2141.

[0180] Fig.25 The structure of the processing can be based on Figure 2 For example, the method may continue to form the source / drain region 400 in operation S1110, as described above with respect to Fig.12 Described in .

[0181] Through the combination of the laterally extending (in the Y direction) isolation layer 300 and the vertically extending (in the Z direction) isolation structure 800, the device 200 is provided with reduced parasitic capacitance while still preventing or reducing leakage current under the isolation structure 800 between adjacent active regions. Specifically, the isolation structure 800 can be formed in a shallower trench, resulting in a small parasitic capacitance, and the isolation layer 300 can prevent or reduce leakage current between source / drain regions.

[0182] By adopting the disclosed process, the process window can be increased, and the device performance and reliability of transistors formed in adjacent active regions will be enhanced. It should be readily understood by those skilled in the art that the methods and structures described herein can be applied to a variety of other semiconductor devices to advantageously achieve similar benefits from such other devices without departing from the scope of the present disclosure.

[0183] Therefore, one of the embodiments of the present disclosure describes a method comprising the following steps: forming an isolation layer above a semiconductor material; forming a source / drain region above the isolation layer; removing a selected gate structure, wherein removing the selected gate structure forms a trench in the semiconductor material; and forming an isolation structure in the trench.

[0184] In certain embodiments of the method, after removing the selected gate structure, an unselected gate structure remains above the semiconductor material; the unselected gate structure comprises a stack of vertically spaced nanosheets, the stack including a bottom nanosheet having a top surface at a first height above the semiconductor material; the isolation layer having a top surface at a second height above the semiconductor material; and the first height is greater than the second height.

[0185] In certain embodiments of the method, after removing the selected gate structure, an unselected gate structure remains above the semiconductor material; the unselected gate structure includes a stack of vertically spaced nanosheets, the stack including a top nanosheet having a top surface; the trench has a lowest point; the top surface is separated from the lowest point by a vertical distance H; the trench has a width W; and the ratio of the vertical distance H to the width W is at least 2:1 and at most 5:1.

[0186] In certain embodiments of the method, the isolation layer includes silicon oxide, silicon nitride, or a combination thereof.

[0187] In certain embodiments of the method, the isolation layer includes a plurality of sub-layers.

[0188] In certain embodiments of the method, the isolation layer has a vertical thickness of less than 6 nanometers.

[0189] In certain embodiments of the method, the isolation layer has an energy band gap of at least 4 eV.

[0190] In certain embodiments of the method, the isolation layer has a dielectric constant less than 7.5.

[0191] In some embodiments of the method, the isolation structure is laterally separated from the nearest adjacent gate structure by a distance of 22 nanometers (nm) to 34 nanometers.

[0192] In another embodiment, a semiconductor device is provided, and the semiconductor device includes: a multi-gate structure located above a semiconductor substrate; an isolation structure laterally separated from the multi-gate structure, wherein the isolation structure is located in a trench in the semiconductor substrate; and an isolation layer covering the semiconductor substrate and extending from the multi-gate structure to the isolation structure.

[0193] In an exemplary embodiment of the semiconductor device, the multi-gate structure includes a stack of spaced-apart nanosheets, the stack comprising a bottom nanosheet; the bottom nanosheet having a top surface at a first height above a semiconductor substrate; an isolation layer having a top surface at a second height above the semiconductor substrate; and the first height is greater than the second height.

[0194] In an exemplary embodiment of the semiconductor device, the multi-gate structure includes a stack of spaced-apart nanosheets, the stack including a top nanosheet; the top nanosheet having a top surface at a first height above a semiconductor substrate; the trench having a lowest point; and a vertical distance from the top surface to the lowest point is less than 120 nanometers (nm).

[0195] In an exemplary embodiment of the semiconductor device, the multi-gate structure includes a stack of spaced-apart nanosheets, the stack comprising a top nanosheet; the top nanosheet having a top surface at a first vertical distance from an upper surface of a semiconductor material; the trench having a lowest point; wherein the upper surface of the semiconductor material is located at a second vertical distance from the lowest point; the first vertical distance is greater than the second vertical distance.

[0196] In an exemplary embodiment of the semiconductor device, the semiconductor device includes a source / drain region covered on an isolation layer; the trench has a lowest point; the top surface is located at a third vertical distance from the lowest point; the source / drain region has a bottommost surface and an uppermost surface, wherein the uppermost surface is located at a fourth vertical distance from the bottommost surface; and the third vertical distance is less than the fourth vertical distance.

[0197] In an exemplary embodiment of the semiconductor device, the isolation layer has a vertical thickness of less than 6 nanometers (nm), and the isolation structure is laterally spaced apart from the multi-gate structure by a distance of 22 nanometers (nm) to 34 nanometers.

[0198] In another embodiment, a semiconductor device includes: a first gate structure and a second gate structure located above a semiconductor material; an isolation structure located between the first gate structure and the second gate structure; a first source / drain region located between the first gate structure and the isolation structure, wherein the first source / drain region is separated from the semiconductor material by a first isolation layer; and a second source / drain region located between the second gate structure and the isolation structure, wherein the second source / drain region is separated from the semiconductor material by a second isolation layer.

[0199] In an exemplary embodiment of the semiconductor device, the first isolation layer and the second isolation layer include a plurality of sub-layers, and the first isolation layer and the second isolation layer include silicon oxide, silicon nitride, or a combination thereof.

[0200] In an exemplary embodiment of the semiconductor device, the first isolation layer and the second isolation layer each have a vertical thickness less than 6 nanometers (nm).

[0201] In an exemplary embodiment of the semiconductor device, each gate structure contacts the semiconductor material along an interface plane; each gate structure has an uppermost surface located at a first vertical distance above the interface plane; the isolation structure has a lowest point; the interface plane is located at a second vertical distance above the lowest point; and the first vertical distance is greater than the second vertical distance.

[0202] In an exemplary embodiment of the semiconductor device, each gate structure contacts the semiconductor material along an interface plane; at the interface plane, each gate structure is separated from the isolation structure by a lateral distance; at the interface plane, the isolation structure has a lateral width; and the lateral distance is greater than the lateral width.

[0203] In some embodiments, a semiconductor device includes an isolation layer disposed above a semiconductor material; a plurality of source / drain regions disposed above the isolation layer; and an isolation structure disposed in a trench of the semiconductor material.

[0204] In an exemplary embodiment of the semiconductor device, the semiconductor device also includes a plurality of nanosheets spaced apart vertically, wherein a bottommost one of the plurality of nanosheets includes a bottom surface at a first height above the semiconductor material, and the isolation layer has a top surface at a second height above the semiconductor material, the first height being greater than the second height.

[0205] In an exemplary embodiment of the semiconductor device, the semiconductor device further comprises a plurality of nanosheets spaced apart vertically, wherein a topmost one of the plurality of nanosheets has a top surface, the trench has a lowest point, the top surface is spaced apart from the lowest point by a vertical distance, the trench has a width, and a ratio of the vertical distance to the width is at least 2:1 and at most 5:1.

[0206] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: an isolation layer located above a semiconductor material; A plurality of source / drain regions are located above the isolation layer; as well as An isolation structure is located in a trench of the semiconductor material.

2. The semiconductor device according to claim 1, wherein Also includes: A plurality of nanosheets are vertically spaced apart, wherein a bottommost one of the plurality of nanosheets comprises a bottom surface at a first height above the semiconductor material, and the isolation layer has a top surface at a second height above the semiconductor material, the first height being greater than the second height.

3. The semiconductor device according to claim 1, wherein: Also includes: A plurality of vertically spaced nanosheets, wherein a topmost one of the plurality of nanosheets has a top surface and the trench has a lowest point, The top surface is spaced a vertical distance from the lowest point, The groove has a width, and A ratio of the vertical distance to the width is at least 2:1 and at most 5:

1.

4. A semiconductor device, characterized in that: include: a multi-gate structure located above a semiconductor substrate; an isolation structure laterally spaced apart from the multi-gate structure, wherein the isolation structure is located in a trench in the semiconductor substrate; and An isolation layer covers the semiconductor substrate and extends from the multi-gate structure to the isolation structure.

5. The semiconductor device according to claim 4, wherein: in: The multi-gate structure includes a stack of a plurality of spaced-apart nanosheets, the stack including a bottom nanosheet; The bottom nanosheet has a top surface at a first height above the semiconductor substrate; The isolation layer has a top surface at a second height above the semiconductor substrate; and The first height is greater than the second height.

6. The semiconductor device according to claim 4, wherein: in: The multi-gate structure includes a stack of a plurality of spaced-apart nanosheets, the stack including a top nanosheet; The top nanosheet has a top surface at a first vertical distance from an upper surface of the semiconductor substrate; The groove has a lowest point; The upper surface of the semiconductor substrate is located at a second vertical distance from the lowest point; and The first vertical distance is greater than the second vertical distance.

7. The semiconductor device according to any one of claims 4 to 6, wherein: in: The semiconductor device further includes a source / drain region overlying the isolation layer; The groove has a lowest point; A top surface of the semiconductor substrate is located at a third vertical distance from the lowest point; The source / drain region has a bottommost surface and an uppermost surface; The uppermost surface is located a fourth vertical distance from the bottommost surface; and The third vertical distance is smaller than the fourth vertical distance.

8. A semiconductor device, characterized in that: include: A first gate structure and a second gate structure are located above a semiconductor material; an isolation structure located between the first gate structure and the second gate structure; a first source / drain region located between the first gate structure and the isolation structure, wherein the first source / drain region is separated from the semiconductor material by a first isolation layer; and A second source / drain region is located between the second gate structure and the isolation structure, wherein the second source / drain region is separated from the semiconductor material by a second isolation layer.

9. The semiconductor device according to claim 8, wherein: The first isolation layer and the second isolation layer include a plurality of sub-layers.

10. The semiconductor device according to claim 8 or 9, wherein: in: Each gate structure contacts the semiconductor material along an interface plane; At the interface plane, each gate structure is separated from the isolation structure by a lateral distance; At the interface plane, the isolation structure has a lateral width; and The lateral distance is greater than the lateral width.

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