Metal interconnect

Abstract

The disclosure provides a metal interconnect. The metal interconnect includes a metal plug and a cap. The metal plug is provided with an upper surface, and the upper surface is provided with a seam. A cover at least partially fills the seam. Wherein a lower surface of the cover body is lower than the upper surface of the metal plug.

Description

Technical Field

[0001] The present disclosure relates to metal interconnects. Background Art

[0002] The electronics industry is experiencing an increasing demand for smaller, faster electronic devices that are simultaneously capable of supporting more and more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with lower cost, higher performance, and lower power consumption. To date, these goals have been achieved in large part by reducing the size (e.g., minimum feature size) of semiconductor ICs, thereby increasing production efficiency and reducing associated costs. However, this reduction in size also increases the complexity of the semiconductor manufacturing process. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies. Utility Model Content

[0003] In some embodiments of the present disclosure, the metal interconnection includes a metal plug and a cover. The metal plug has an upper surface, and the upper surface has a seam. The cover at least partially fills the seam. The lower surface of the cover is lower than the upper surface of the metal plug.

[0004] In some embodiments disclosed herein, the metal interconnection further comprises a metal structure, a cover, and a conductive interconnection. The metal structure has an upper surface, and the upper surface has a seam. The cover seals the seam. The conductive interconnection is on the metal structure.

[0005] In some embodiments of the present disclosure, the metal interconnection includes a metal structure, a cover, and a conductive interconnection. The metal structure has an upper surface and a seam extending from the upper surface to the metal structure. The cover is located in the seam. The conductive interconnection is located above the metal structure and the cover. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a flow chart illustrating a method according to some embodiments;

[0008] Figures 2 to 9 According to some embodiments Figure 1 a cross-sectional view of a device during a continuous manufacturing stage of a method;

[0009] Fig.10is a flow chart illustrating a method according to some embodiments;

[0010] Figures 11 to 15 According to some embodiments Fig.10 Cross-sectional view of a device during successive manufacturing stages of the method.

[0011]

Explanation of symbols

[0012] 10: Semiconductor devices, semiconductor device structures, conductive interconnect structures

[0013] 12:Substrate

[0014] 14: Conductive structure

[0015] 20:ILD Materials

[0016] 21:Top surface

[0017] 24: Hole

[0018] 29: Bottom surface

[0019] 30:Metal Structure

[0020] 31: Upper surface

[0021] 32: Side wall

[0022] 33: Exposed part

[0023] 34: Inner wall

[0024] 35: Seam

[0025] 36: Opening

[0026] 38: Air Gap

[0027] 40:Film

[0028] 41: Cover

[0029] 43: Vertical side wall section

[0030] 50: Etching stop layer

[0031] 60: Dielectric material

[0032] 65: Groove

[0033] 70: Barrier layer

[0034] 80: Conductive material

[0035] 85: Conductive Interconnect

[0036] 100: Method

[0037] 141:Metal contacts

[0038] 142:Metal gate

[0039] 200: Method

[0040] S11~S33: Steps

[0041] H1~H9: Height

[0042] W1~W3: Width DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments, or examples, for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is directly contacted with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0044] Additionally, for ease of description, spatially relative terms, such as "over," "overlying," "above," "upper," "top," "below," "underlying," "below," "beneath," "lower," "bottom," "side," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature(s). The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0045] In certain embodiments herein, a "material structure" is a structure comprising at least 50 wt.% of a confirmed material, for example, at least 60 wt.% of a confirmed material, at least 75 wt.% of a confirmed material, 90 wt.% of a confirmed material, at least 95 wt.% of a confirmed material, or at least 99 wt.% of a confirmed material; and a structure formed of a "material" comprises at least 50 wt.% of a confirmed material, for example, at least 60 wt.% of a confirmed material, at least 75 wt.% of a confirmed material, at least 90 wt.% of a confirmed material, at least 95 wt.% of a confirmed material, or at least 99 wt.% of a confirmed material. For example, in certain embodiments, each of a tungsten structure and a structure formed of tungsten is a structure having at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of tungsten.

[0046] For the sake of brevity, typical techniques related to semiconductor device manufacturing may not be described in detail herein. In addition, the various tasks and processes described herein may be combined into a more comprehensive program or process with additional functions not described in detail herein. Specifically, the various processes in semiconductor device manufacturing are well known, and therefore, for the sake of brevity, many typical processes will only be briefly mentioned herein, or will be omitted entirely without providing well-known process details. As will be readily apparent to those skilled in the art after a complete reading of this disclosure, the structures disclosed herein may be employed with a variety of techniques and may be incorporated into a variety of semiconductor devices and products. In addition, it should be noted that semiconductor device structures include different numbers of components, and a single component shown in the figure may represent multiple components.

[0047] It should be noted that some embodiments of the present disclosure present metal structures in the form of conductive sockets, wires or through holes. However, the embodiments are not limited thereto.

[0048] Embodiments of metal structures and methods of making metal structures and / or making semiconductor devices using metal structures are provided herein. The methods described herein can be easily integrated into current process flows. In certain embodiments, the metal structure forms a seam or gap covered with a thin film. In an exemplary embodiment, the metal structure is tungsten and the thin film is an oxide, nitride, oxynitride or metal layer.

[0049] In advanced nodes, the holes can be filled with tungsten by a chemical vapor deposition (CVD) process to produce tungsten sockets. However, tungsten does not grow well on the surface of the hole. As a result, the tungsten sockets are formed with large seams. Tungsten sockets with seams are fragile and easily damaged by other processes, such as dry etching and wet cleaning processes, which can lead to tungsten loss and seam expansion. Since the barrier layer of the interconnect structure formed above the metal structure is discontinuous, the tungsten loss and seam expansion will lead to yield loss. Because the barrier layer above the metal structure is discontinuous, the material of the interconnect structure formed above the metal structure, for example, copper, can fill the seams.

[0050] In this article, embodiments can minimize metal loss and seam expansion. In addition, embodiments of this article can protect metal structures from damage by dry etching. Similarly, embodiments of this article can protect metal structures from dissolution or corrosion by wet etching or cleaning processes.

[0051] Embodiments of the present disclosure provide advantages over existing technologies, although it is understood that other embodiments may provide different advantages, not all of which are necessarily disclosed herein, and no particular advantages are required for all embodiments. Certain embodiments herein use a film to fill seams in metal structures to protect the metal structures from damage, dissolution, and / or corrosion by dry or wet processes. In an exemplary embodiment, the film fills the seams and forms a protective layer around the metal structure to prevent damage caused by dry etching and wet processes.

[0052] Certain embodiments herein use a wet process to etch back the film so that the film remains only in the seams and on the sidewalls of the metal structure. In certain embodiments, the film filling the seams prevents the overlying etch stop layer or conductive material from falling into the seams. Certain embodiments provide metal structures with resistance to dry etching damage. Certain embodiments provide reduced metal loss in metal structures and reduced seam expansion in metal structures with seams during subsequent processing. In certain embodiments, the film on the sidewalls of the metal structure prevents current leakage.

[0053] For the following discussion, Figure 1 A flow chart of a method 100 for manufacturing a semiconductor device 10 during a semiconductor manufacturing process is provided. Figures 2 to 9 Describing method 100, Figures 2 to 9 Semiconductor device 10 is illustrated at various stages of fabrication according to method 100 . Figures 2 to 91 is a cross-sectional view with the vertical direction defined by the Z axis and the lateral direction defined by the X axis. It should be understood that method 100 includes steps characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow and is therefore only briefly described herein. In addition, additional steps may be performed before, after, and / or during method 100.

[0054] Reference now Figure 1 and Figure 2 , a method 100 for fabricating a semiconductor device 10 includes depositing an interlayer dielectric (ILD) material 20 over a conductive structure 14 and / or over a substrate 12 at S11. As shown, the ILD material 20 has an uppermost surface 21. The method 100 also includes etching the ILD material 20 at S13 to form a hole 24 aligned with the structure 14. An exemplary ILD material 20 is SiO2. An exemplary conductive structure 14 includes a metal contact 141 to an active region and a metal gate 142.

[0055] In an exemplary embodiment, the ILD material 20 has a vertical height or thickness H9. In an exemplary embodiment, the ILD thickness H9 is 30 to 70 nanometers (nm).

[0056] In addition, the method 100 includes forming a metal structure 30 in the hole 24 at S15. The metal structure 30 may be a socket, a conductive via or other metal feature. In an exemplary embodiment, the metal structure 30 is formed with an upper surface 31 that terminates at an opposite sidewall 32. As shown, the upper surface 31 is formed at a vertical height H3 above the uppermost surface 21 of the ILD material 20. Therefore, a portion 33 of the sidewall 32 is located above the uppermost surface 21 of the ILD material 20. In an exemplary embodiment, the vertical height H3 of the portion 33 of the sidewall 32 is 0.1 to 3 nanometers (nm).

[0057] As shown, each metal structure 30 has a bottom surface 29 and a vertical height H1 extending from the upper surface 31 to the bottom surface 29. In an exemplary embodiment, the vertical height H1 may be 20 to 50 nanometers (nm) for the metal structure 30 located above the metal contact 141 to the active area, or the vertical depth H1 may be 30 to 50 nanometers for the metal structure 30 located above the metal gate 142. In an exemplary embodiment, the bottom surface 29 of each metal structure 30 has a lateral width W2. In an exemplary embodiment, the bottom width W2 is 5 to 20 nanometers (nm).

[0058] In an exemplary embodiment, the metal structure 30 is formed of a metal deposited over a barrier layer (not shown), such as a Ti / TiN barrier layer, by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In an exemplary embodiment, the barrier layer has a thickness of 0.1 to 3 nanometers (nm). As a result of the deposition process, in which the metal structure grows upward and inward from the open surface, the metal structure 30 is formed with a seam or central void 35 extending vertically (i.e., in the Z-axis direction) from the opening 36 in the upper surface 31 into the metal structure 30 to a vertical depth H2. As shown, each seam 35 is defined by one or more inner sidewalls 34 of the metal structure 30. In an exemplary embodiment, the seam depth H2 is 5 to 50 nanometers (nm). In an exemplary embodiment, the seam 35 has a lateral width W1, i.e., in the X-axis direction extending between opposing inner sidewalls 34. In an exemplary embodiment, the seam width W1 is 0.1 to 5 nanometers (nm).

[0059] The metal structure 30 may be composed of any suitable metal. In an exemplary embodiment, the metal structure 30 is composed of tungsten.

[0060] Cross Reference Figure 1 and Figure 3 , the method 100 includes, at S17, depositing a thin film 40 over the structure of the semiconductor device 10. For example, the thin film 40 may be deposited over the uppermost surface 21 of the ILD material 20. In addition, the thin film 40 may be deposited over the exposed portion 33 of the sidewall 32, over the upper surface 31, and in the seam 35 of the metal structure 30. Therefore, the thin film 40 includes a cap 41 filling the seam 35 and a sidewall portion 43 adjacent to the exposed portion 33 of the sidewall 32.

[0061] In some embodiments, the cover 41 completely fills the seam 35, such as the seam 35 shown in the metal structure 30 overlying the metal gate 142. In some embodiments, the cover 41 partially fills the seam 35 so that the air gap 38 is located in the seam 35 below the cover 41, such as the seam 35 shown in the metal structure 30 overlying the metal contact 141. In an exemplary embodiment, the air gap 38 has a vertical height H4 of 4 to 49 nanometers (nm). In an exemplary embodiment, regardless of whether the cover completely fills the seam 35 or whether there is an air gap 38 located below the cover 41, the cover 41 completely seals the opening 36. In particular, the cover 41 forms a complete and continuous contact with the inner sidewall 34 at the opening 36.

[0062] In an exemplary embodiment, the thin film 40 has a thickness H5. In an exemplary embodiment, the thickness H5 is 10 to 100 angstroms.

[0063] In an exemplary embodiment, the thin film 40 is composed of an oxide, a nitride, an oxynitride or a metal layer. In an exemplary embodiment, the thin film is Al2O3.

[0064] Cross Reference Figure 1 and Figure 4 , method 100 includes etching thin film 40 at S19. In particular, method 100 etches thin film 40 from above metal structure 30 to uncover upper surface 31. Upper surface 31 is uncovered to allow conductive contact with an overlying metal layer as described below.

[0065] In an exemplary embodiment, a cover 41 formed by the thin film 40 remains in the seam 35 after etching. In an exemplary embodiment, the cover 41 has a maximum vertical height H6 of 1 to 20 nanometers (nm). In some embodiments, the cover 41 fills the hole so that the maximum vertical height H6 is equal to the trench depth H2. Generally speaking, the sum of the cover height H6 and the air gap height H4 (which may be zero) is equal to the seam depth H2.

[0066] Furthermore, after etching, vertical sidewall portion 43 may remain adjacent to metal structure 30. Figure 4 In the illustrated embodiment of FIG. 4 , the thin film 40 on the ILD material 20 is removed by an etching process, but not the vertical sidewall portion 43. In an exemplary embodiment, the vertical sidewall portion 43 has a lateral thickness W3. In an exemplary embodiment, the sidewall portion thickness W3 is 0.1 to 1 nanometer (nm).

[0067] In an exemplary embodiment, the thin film 40 is etched by a wet etching process. The exemplary wet etching process is performed using HF, NH4F, H3PO4, H2O, or molecules containing F or P. In an exemplary embodiment, the wet etching process uses HF, NH4F, H3PO4, H2O, or molecules containing F or P as an etching medium; uses pure H2O, H2O and CO2, or H2O and dilute NH4OH as a cleaning medium; uses a drying process selected from spin drying with N2 gas or drying with isopropyl alcohol (IPA); and uses a process temperature of 20 to 80 degrees Celsius.

[0068] In method 100, S17 and S19 can be considered as sealing the seam 35 together with the cover 41 at S18. Therefore, action S18 includes depositing a thin film 40 over the upper surface 31 of the metal structure 30 and at least partially filling the seam 35, and etching the thin film 40 from above the metal structure 30, wherein the cover 41 of the thin film 40 remains in the seam 35.

[0069] It should be noted that the cover 41 and the sidewall portion 43 of the film 40 protect the non-intentionally uncovered surfaces of the metal structure 30 , ie, surfaces other than the upper surface 31 , from being damaged during the wet etching process.

[0070] Cross Reference Figure 1 and Figure 5 , the method 100 may continue at S21, where an etch stop layer 50 is deposited over the metal structure 30 and the cap 41. The exemplary etch stop layer 50 includes SiN, SiC, tetraethyl orthosilicate (TEOS), other insulating materials or combinations thereof. Alternatively, the etch stop layer 50 may include other materials.

[0071] In an exemplary embodiment, the etch stop layer 50 has a thickness H7. In an exemplary embodiment, the thickness H7 is 0.1 to 3 nanometers (nm).

[0072] Because the cap 41 seals the opening 36 of each metal structure 30 , the etch stop layer 50 can be continuously formed over the seam 35 and further completely cover the seam 35 .

[0073] Cross Reference Figure 1 and Figure 6 , the method 100 may continue at S23 to form a dielectric material 60 over the metal structure 30, the cap 41, and the etch stop layer 50. The exemplary dielectric material 60 is a low-k material. In an exemplary embodiment, the dielectric material 60 has a vertical height or thickness H8. In an exemplary embodiment, the dielectric thickness H8 is 20 to 50 nanometers (nm). In addition, the method 100 includes etching the dielectric material 60 over the metal structure 30 at S25 to form a trench 65. For example, the dielectric material 60 may be patterned and etched during back-end-of-line (BEOL) patterning. In an exemplary embodiment, a dry etching process is used to etch the dielectric material 60 to form the trench 65.

[0074] As shown, when the dielectric material 60 above the metal structure 30 is etched to form the trench 65, the etch stop layer 50 protects the ILD material 20 and the metal structure 30 from being damaged by the etchant. In particular, because the etch stop layer 50 completely and continuously covers the upper surface 31 of each metal structure 30 and the seam 35, the upper surface 31 of each metal structure 30 is protected from the dry etching process.

[0075] Likewise, the cover 41 and the sidewall portion 43 of the film 40 below the etch stop layer 50 protect the metal structure 30 from being damaged by the dry etchant. Specifically, the cover 41 and the sidewall portion 43 of the film 40 protect the surfaces of the metal structure 30 that are not intentionally uncovered, i.e., surfaces other than the upper surface 31, from being damaged during the wet etching process, including the portion 33 of the sidewall 32 that is above the uppermost surface 21 of the ILD material 20 and the inner sidewall 34 that constrains the seam 35.

[0076] Thus, by sealing the seams 35 of the respective metal structures 30, the method is able to provide an etch stop layer 50 that completely and continuously covers the upper surface 31 and the seams 35 of the respective metal structures 30. In this way, the respective metal structures 30 are protected from damage by wet and dry etchants during the etching process described previously.

[0077] Cross Reference Figure 1 and Figure 7 , the method 100 may continue at S27 by removing the etch stop layer 50 from above the metal structure 30. In particular, the portion of the etch stop layer 50 not covered by the dielectric material 60 is removed. Thus, the etch stop layer 50 is removed from the metal structure 30 and from the ILD material 20 below the trench 65. In an exemplary embodiment, a wet cleaning process is further performed to remove dry residues from the trench etching process and remove the etch stop layer. In an exemplary embodiment, the wet etching process is performed with a solution containing H2O and NH4F or other suitable chemicals.

[0078] Cross Reference Figure 1 and Figure 8 , method 100 may continue at S29, where a barrier layer 70 is deposited in trench 65. In particular, barrier layer 70 is conformally deposited over dielectric material 60, sidewalls of trench 65 defined by dielectric material 60 and etch stop layer 50, ILD material 20, sidewall portion 43, cap 41, and upper surface 31 of metal structure 30. Exemplary barrier layer 70 is TaN or TiN, although other suitable materials may also be used.

[0079] Cross Reference Figure 1 and Fig. 9 , method 100 may continue at S31, where a conductive material 80 is deposited in trench 65. In an exemplary embodiment, conductive material 80 is a metal, such as copper. In addition, method 100 may include planarizing semiconductor device structure 10 at S33 to define separate conductive interconnects 85 as shown, each of which contacts underlying metal structure 30.

[0080] As about Figures 1 to 9 The method 100 forms Fig. 9 A conductive interconnect structure 10 is provided.

[0081] Fig.10 A flow chart of a method 200 of manufacturing a semiconductor device 10 during a semiconductor manufacturing process is provided. In an embodiment of the method 200, after etching the thin film from over the metal structure, the thin film remains covering the dielectric layer.

[0082] The following references Figures 2 to 3 and Figures 11 to 15 Describing method 200, Figures 2 to 3 and Figures 11 to 15 Semiconductor device 10 is shown at various stages of fabrication according to method 200 . Figures 2 to 3 and Figures 11 to 15 2 is a cross-sectional view with the vertical direction defined by the Z axis and the lateral direction defined by the X axis. It should be understood that method 200 includes steps that are characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow and are therefore only briefly described herein. In addition, additional steps may be performed before, after, and / or during method 200.

[0083] As previously referenced in method 100 and Figures 2 to 3 The method 200 for manufacturing the semiconductor device 10 also includes depositing an interlayer dielectric (ILD) material 20 over the conductive structure 14 and / or the substrate 12 at S11; etching the ILD material 20 to form a hole 24 aligned with the structure 14 at S13; forming a metal structure 30 in the hole 24 at S15; and depositing a thin film 40 over the structure of the semiconductor device 10 at S17.

[0084] Cross Reference Fig.10 and Fig.11 The method 200 includes partially etching the thin film 40 at S19. In particular, the method 200 etches the thin film 40 from above the metal structure 30 to reveal the upper surface 31. Figures 1 to 9 Unlike the embodiment of the present invention, in the method 200, the film 40 is not removed from above the uppermost surface 21 of the ILD material 20. Instead, in the method 200, the film 40 is only removed from above the metal structure 30. The film 40 above the uppermost surface 21 of the ILD material 20 may be thinned. Therefore, the film 40 covers the ILD material 20 and the interface between the ILD material 20 and the metal structure 30.

[0085] In the method 200, S17 and S19 can be considered as sealing the seam 35 together with the cover 41 at S18. Therefore, action S18 includes depositing a thin film 40 over the upper surface 31 of the metal structure 30 and at least partially filling the seam 35, and etching the thin film 40 from the upper surface 31 of the metal structure 30, wherein the thin film 40 remains in the seam 35 (as the cover 41) and over the ILD material 20 between the metal structures 30.

[0086] Cross Reference Fig.10 and Fig.12 , the method 200 may continue at S23 to form a dielectric material 60 over the metal structure 30, the cap 41, and the thin film 40. In addition, the method 200 includes etching the dielectric material 60 over the metal structure 30 to form a trench 65 at S25. For example, the dielectric material 60 may be patterned and etched during back-end-of-line (BEOL) patterning. In an exemplary embodiment, a dry etching process is used to etch the dielectric material 60 to form the trench 65. As shown, when the dielectric material 60 over the metal structure 30 is etched to form the trench 65, the thin film 40 prevents the etching of the ILD material 20 and protects the metal structure 30 from being damaged by the etchant along the sidewall 32.

[0087] Cross Reference Fig.10 and Fig.13 , the method 200 may continue at S28 to perform a wet cleaning process, such as for removing dry residues from the dry etching process. The exemplary process removes the thin film 40 from the ILD material 20. The sidewall portion 43 may remain adjacent to the metal structure 30. In an exemplary embodiment, the wet etching process is performed with a solution containing H2O and NH4F or other suitable chemicals.

[0088] Cross Reference Fig.10 and Fig.14 , method 200 may continue at S29, where a barrier layer 70 is deposited in trench 65. Exemplary barrier layer 70 is conformally deposited over dielectric material 60, sidewalls of trench 65 defined by dielectric material 60 and thin film 40, over sidewall portion 43, over cap 41, and over upper surface 31 of metal structure 30. Exemplary barrier layer 70 is TaN or TiN, although other suitable materials may also be used.

[0089] Cross Reference Fig.10 and Fig.15 , method 200 may continue at S31, where a conductive material 80 is deposited in trench 65. In an exemplary embodiment, conductive material 80 is a metal, such as copper. In addition, method 200 may include planarizing semiconductor device structure 10 at S33 to define separate conductive interconnects 85 as shown, each of which is in electrical contact with underlying metal structure 30.

[0090] As about Figures 2 to 3 and Figures 11 to 15 The method 200 forms Fig.15 A conductive interconnect structure 10 is provided.

[0091] In an exemplary embodiment, metal structure 30 is formed during a middle-end-of-the-line (MEOL) process and conductive interconnect 85 is formed during a back-end-of-line (BEOL) process, wherein the interconnect is formed within semiconductor device 10 .

[0092] A method for manufacturing a semiconductor device is also provided, comprising forming a metal plug having an upper surface formed with a seam; depositing a thin film over the upper surface of the metal plug and at least partially filling the seam; and etching the thin film from above the metal plug, wherein the thin film remains in the seam.

[0093] In some embodiments, the method includes depositing an etch stop layer over the metal plug after etching a thin film over the metal plug; forming a dielectric material layer over the metal plug; etching the dielectric material layer over the metal plug to form a trench; removing the etch stop layer over the metal plug; and depositing a conductive material in the trench to form a conductive interconnect in contact with the metal plug.

[0094] In certain embodiments of the method, the thin film is an oxide, nitride, oxynitride, or metal layer.

[0095] In certain embodiments of the method, the thin film has a thickness of 10 to 100 angstroms.

[0096] In some embodiments of the method, the metal plug is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0097] In some embodiments of the method, etching the thin film from above the metal plug includes performing a wet etching process.

[0098] In certain embodiments of the method, the wet etching process is performed using HF, NH4F, H3PO4, H2O, or molecules containing F or P.

[0099] In certain embodiments of the method, a wet etching process is performed using HF, NH4F, H3PO4, H2O, or molecules containing F or P as an etching medium; using pure H2O, H2O and CO2, or H2O and dilute NH4OH as a cleaning medium; using a drying process selected from spin drying with N2 gas or IPA drying; and using a process temperature of 20 to 80 degrees Celsius.

[0100] In certain embodiments of the method, forming a metal plug includes forming a metal plug in a dielectric layer; depositing a thin film over an upper surface of the metal plug and at least partially filling the seam includes depositing a thin film over the dielectric layer; and, after etching the thin film from over the metal plug, the thin film remains over the dielectric layer. In such embodiments, a dielectric material layer is formed over the metal plug and the dielectric layer; the dielectric material layer over the metal plug is etched to form a trench, wherein the thin film prevents etching of the dielectric layer; and a conductive material is deposited in the trench to form a conductive interconnect in contact with the metal plug.

[0101] In another embodiment, a method is provided that includes forming a metal structure having an upper surface having a seam formed thereon; sealing the seam with a cover; and forming a conductive interconnect over the metal structure.

[0102] In certain embodiments of the method, the metal structure is tungsten.

[0103] In certain embodiments of the method, the cap is an oxide, a nitride, an oxynitride, or a metal.

[0104] In certain embodiments, the method includes depositing an etch stop layer over a metal structure and a cover; forming a dielectric material layer over the etch stop layer; etching the dielectric material layer over the etch stop layer to form a trench; and removing the etch stop layer from over the metal structure and the cover; wherein forming a conductive interconnect over the metal structure includes depositing a conductive material in the trench.

[0105] In certain embodiments of the method, sealing the seam with the cover includes: depositing a thin film over an upper surface of the metal structure and at least partially filling the seam; and etching the thin film from over the metal plug, wherein the thin film remains in the seam.

[0106] In certain embodiments of the method, forming a metal structure includes forming a metal structure in a dielectric layer; and sealing the seam with a cover includes depositing a thin film above the dielectric layer, above the upper surface of the metal structure, and at least partially filling the seam, and etching the thin film from above the metal plug, wherein the thin film remains in the seam and above the dielectric layer.

[0107] In another embodiment, a metal interconnect is provided. The metal interconnect includes a metal structure having an upper surface and a joint extending from the upper surface to the metal structure; a cover located in the joint; and a conductive interconnect located above the metal structure and the cover.

[0108] In certain embodiments of the metal interconnect, the metal structure comprises tungsten, the cap comprises Al2O3, and the conductive interconnect comprises copper.

[0109] In certain embodiments of the metal interconnect, the upper surface of the metal structure terminates at the sidewalls, the liner is located on the lateral sidewalls, and the liner and the cover are formed of the same material.

[0110] In certain embodiments of the metal interconnect, an air gap is located in the seam beneath the cover.

[0111] In some embodiments of the present disclosure, the metal interconnection includes a metal plug and a cover. The metal plug has an upper surface with a seam on the upper surface. The cover at least partially fills the seam.

[0112] In some embodiments, the metal interconnection further includes an etch stop layer, a dielectric material layer, and a conductive interconnection. The etch stop layer is on the metal plug. The dielectric material layer is on the etch stop layer. The conductive interconnection is on the metal plug and the etch stop layer and contacts the metal plug.

[0113] In some embodiments, the metal interconnection further includes an interlayer dielectric layer surrounding the metal plug, wherein the upper surface of the metal plug is higher than an upper surface of the interlayer dielectric layer.

[0114] In some embodiments, the cover has a maximum vertical height of 1 to 20 nanometers.

[0115] In some embodiments disclosed herein, the metal interconnection further comprises a metal structure, a cover, and a conductive interconnection. The metal structure has an upper surface, and the upper surface has a seam. The cover seals the seam. The conductive interconnection is on the metal structure.

[0116] In some embodiments, a bottommost portion of the conductive interconnect is lower than the upper surface of the metal plug.

[0117] In some embodiments of the present disclosure, the metal interconnection includes a metal structure, a cover, and a conductive interconnection. The metal structure has an upper surface and a seam extending from the upper surface to the metal structure. The cover is located in the seam. The conductive interconnection is located above the metal structure and the cover.

[0118] In some embodiments, a lower surface of the conductive interconnect contacts the cover and the upper surface of the metal structure.

[0119] In some embodiments, the metal interconnect further includes a liner, wherein the upper surface of the metal structure terminates at a lateral sidewall, and the liner is located on the lateral sidewall.

[0120] In some embodiments, the air gap is located in the seam below the cover.

[0121] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A metal interconnection, characterized in that: Include: a metal plug having an upper surface with a seam; and A cover at least partially fills the seam, wherein a lower surface of the cover is lower than the upper surface of the metal plug.

2. The metal interconnection according to claim 1, characterized in that Also includes: an etch stop layer on the metal plug; a dielectric material layer on the etch stop layer; and A conductive interconnection is on the metal plug and the etch stop layer and is in contact with the metal plug.

3. The metal interconnection according to claim 1 or 2, characterized in that: Also includes: An interlayer dielectric layer surrounds the metal plug, wherein the upper surface of the metal plug is higher than an upper surface of the interlayer dielectric layer.

4. The metal interconnection according to claim 3, characterized in that The cover has a maximum vertical height of 1 to 20 nanometers.

5. A metal interconnection, characterized in that: Include: A metal structure having an upper surface with a joint; a cover to seal the seam; and A conductive interconnect is on the metal structure.

6. The metal interconnection according to claim 5, characterized in that A bottom of the conductive interconnection is lower than the upper surface of the metal structure.

7. A metal interconnection, characterized in that: Include: A metal structure having an upper surface and a seam extending from the upper surface into the metal structure; a cover located in the seam; and A conductive interconnect is located above the metal structure and the cover.

8. The metal interconnection according to claim 7, characterized in that A lower surface of the conductive interconnect contacts the cover and the upper surface of the metal structure.

9. The metal interconnection according to claim 7 or 8, characterized in that: Also includes: A liner, wherein the upper surface of the metal structure terminates at a lateral sidewall, the liner being located on the lateral sidewall.

10. The metal interconnection according to claim 7 or 8, characterized in that: One of the air gaps is located in the seam below the cover.

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