Transistor device
By using a P-type cap layer structure with high and low activation concentrations in gallium nitride high electron mobility transistors, the problem of high leakage current caused by high electric field in traditional devices is solved, achieving higher reliability and efficiency.
Patent Information
- Application Number
- CN202421143892.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-24
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2034-05-24
AI Technical Summary
In traditional gallium nitride high electron mobility transistors, the higher concentration of P-type cap layer will form a higher electric field when the gate is positively compressed, resulting in lower gate breakdown voltage and higher gate leakage. Current affects the reliability and performance of the device.
A structure of a first P-type cover layer with a higher activation concentration and a second P-type cover layer with a lower activation concentration is adopted. The first P-type cover layer exhausts two-dimensional electron gas to form an enhanced device, and the second P-type cover layer The layer forms Schottky contact with the gate metal layer, adjusting the electric field to increase the threshold voltage and reduce leakage current.
By increasing the threshold voltage of the device, the chance of the enhancement mode device being accidentally turned on is reduced, the gate breakdown voltage is increased, the gate leakage current is reduced, and the reliability and performance of the device are improved.
Smart Images
Figure CN222382028U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a power semiconductor device, in particular to a manufacturing method of a gallium nitride transistor power device. Background Art
[0002] Compared with silicon materials, gallium nitride materials have larger energy band gaps, higher electron mobility, saturated electron velocity and breakdown electric field. Gallium nitride high electron mobility transistors are common gallium nitride power devices and are widely used in high-frequency applications such as radio frequency and microwave.
[0003] An existing GaN high electron mobility transistor structure is as follows Figure 1 As shown, the device is provided with a buffer layer located above the substrate layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a traditional P-type cap layer 104 located above the barrier layer, a dielectric layer, and a gate metal layer located above the traditional P-type cap layer 104. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer below the heterojunction. One of the main functions of the traditional P-type cap layer 104 is to form a Schottky contact with the gate metal layer above to reduce the gate current when the gate is positively pressurized, and another main function is to deplete the electron gas located below the traditional P-type cap layer 104 to form an enhancement device. In order to reduce the chance of the enhancement device being turned on by mistake, the threshold voltage needs to reach a sufficiently high value. In order to achieve a higher threshold voltage, the traditional P-type cap layer 104 generally needs a higher concentration to enhance the ability to deplete the electron gas located below it. However, the higher concentration of the conventional P-type cap layer 104 will form a higher electric field when the gate is positively pressed, resulting in a lower gate breakdown voltage and a higher gate leakage current, which affects the reliability and performance of the device. Utility Model Content
[0004] In order to solve the above-mentioned problems, the utility model provides the following technical solutions:
[0005] A transistor device, the device comprises a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer, a source metal layer and a drain metal layer respectively located on both sides of the gate metal layer, the channel layer and the barrier layer form a heterojunction and form a two-dimensional electron gas on the surface of the channel layer below the heterojunction; the P-type cap layer at least comprises a first P-type cap layer with a higher activation concentration located above the barrier layer and a second P-type cap layer with a lower activation concentration located above the first P-type cap layer, the first P-type cap layer depletes the two-dimensional electron gas to form an enhancement-type device, and the second P-type cap layer forms a Schottky contact with the gate metal layer; wherein the activation concentration ranges from 1x10 17– 1x10 21 cm -3 , the higher activation concentration is at least twice as high as the lower activation concentration.
[0006] Furthermore, the width of the gate metal layer is the same as the width of the first P-type cap layer and the second P-type cap layer located thereunder, and the gate metal layer is connected to the side wall of the second P-type cap layer; or
[0007] The width of the gate metal layer is smaller than the width of the first P-type cap layer and the second P-type cap layer.
[0008] Furthermore, the side walls of the first P-type cap layer and the second P-type cap layer are inclined side walls to increase the length of the side walls.
[0009] Furthermore, the higher activation concentration range is 1×10 19 – 1×10 20 cm -3 , the lower activation concentration range is 1×10 18 – 1×10 19 cm -3 .
[0010] Furthermore, a dielectric layer is disposed above the barrier layer, and the dielectric layer extends toward the P-type cap layer, so that the gate metal layer is separated from the side wall of the second P-type cap layer.
[0011] The P-type cap layer of the utility model is provided with two layers, the lower P-type cap layer has a higher activation concentration, which ensures that the threshold voltage of the device can reach a higher value, reducing the chance of the enhancement type device being mistakenly turned on; the activation concentration of the upper P-type cap layer is lower, and when the gate is positively pressurized, the depletion in the P-type cap layer is deeper and the electric field is lower. Therefore, the gate breakdown voltage of the device is higher and the gate leakage current is also lower, which improves the reliability and performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 is a cross-sectional schematic diagram of an existing high electron mobility transistor structure;
[0013] Figure 2 A schematic cross-sectional view of a device structure of an embodiment of the utility model;
[0014] Figure 3 A schematic cross-sectional view of a device structure of an embodiment of the utility model;
[0015] Figure 4 A cross-sectional schematic diagram of a device structure of another embodiment of the utility model;
[0016] Figure 5 A schematic cross-sectional view of a device structure of another embodiment of the utility model;
[0017] Figure 6 A schematic cross-sectional view of a device structure of another embodiment of the utility model;
[0018] Figure 7 A-7H is an embodiment of a method for forming a device structure of the present invention. DETAILED DESCRIPTION
[0019] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. The specific implementation does not limit the fixed direction. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and grooves in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.
[0020] Example 1
[0021] Please refer to Figure 2 , Figure 2 This is a cross-sectional schematic diagram of a device structure of a first embodiment of the utility model, the structure comprising:
[0022] a substrate layer 200 at the bottom;
[0023] a buffer layer 201 located above the substrate layer 200;
[0024] A channel layer 202 located above the buffer layer 201;
[0025] a barrier layer 203 located above the channel layer 202;
[0026] A first P-type cap layer 204a with a relatively high activation concentration located above the barrier layer 203;
[0027] A second P-type cap layer 204 b with a lower activation concentration located above the first P-type cap layer 204 a with a higher activation concentration;
[0028] The activation concentration range is 1×10 17 – 1×10 21 cm -3 The higher activation concentration is at least twice as high as the lower activation concentration; a typical range for the higher activation concentration is 1×10 19 – 1×10 20 cm -3 A typical range for lower activation concentrations is 1x10 18 – 1x10 19 cm -3 ;
[0029] The dielectric layer 205 located above the barrier layer 203 and the second P-type cap layer 204b with a lower activation concentration serves as an etching stop layer for the gate metal layer, which can prevent the second P-type cap layer 204b with a lower activation concentration from being exposed during etching of the gate metal layer, thereby reducing surface defects.
[0030] A gate metal layer 206 located above the second P-type cap layer 204 b with a lower activation concentration;
[0031] A source metal layer 207 located on the left of the gate metal layer 206 and a drain metal layer 208 located on the right;
[0032] In the above structure, the channel layer 202 and the barrier layer 203 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer 202 located below the heterojunction, forming a current channel between the source metal layer 207 and the drain metal layer 208 when the device is turned on.
[0033] In the above structure, if Figure 3 As shown, the first P-type cap layer 204a with a relatively high activation concentration depletes the electron gas 209 on the surface of the channel layer 202 thereunder, thereby forming an enhancement-mode device.
[0034] In the above structure, the higher the activation concentration of the first P-type cap layer 204a with a higher activation concentration, the greater the depletion capability of the electron gas 209 on the surface of the channel layer 202 thereunder, and the higher the threshold voltage of the enhancement mode device formed.
[0035] In the above structure, the second P-type cap layer 204 b with a lower activation concentration forms a Schottky contact with the gate metal layer 206 located thereon, thereby reducing the gate current when the gate is subjected to a forward voltage.
[0036] In the above structure, the lower the activation concentration of the second P-type cap layer 204b with a lower activation concentration, the deeper the depletion in the P-type cap layer and the lower the electric field when the gate is positively pressed. The higher the gate breakdown voltage of the device, the lower the gate leakage current.
[0037] In the above structure, the sidewalls of the first P-type cap layer 204a and the second P-type cap layer 204b are formed by etching, and the bottom of the gate metal layer 206 is narrower than the top of the second P-type cap layer 204b with a lower activation concentration located thereunder. The bottom of the gate metal layer 206 is separated from the sidewalls of the second P-type cap layer 204b with a lower activation concentration located thereunder, thereby reducing gate leakage current.
[0038] Example 2
[0039] A variation of the device implementation of the utility model is as follows Figure 4 As shown, and Figure 3The difference between the embodiments is that there is no dielectric layer above the second P-type cap layer 204b with lower activation concentration, and the second P-type cap layer 204b with lower activation concentration becomes an etching stop layer for the gate metal layer 206, so there is no need to deposit, photolithograph and etch the dielectric layer, and the process is simpler.
[0040] Example 3
[0041] A variation of the device implementation of the utility model is as follows Figure 5 As shown, and Figure 3 The difference of the embodiment is that there is no dielectric layer above the second P-type cap layer 204b with a lower activation concentration, so there is no need to deposit, photolithograph and etch the dielectric layer, and the process is simpler. In addition, the gate metal layer 206 has the same width d as the first P-type cap layer 204a and the second P-type cap layer 204b located thereunder, and is formed by photolithography once using the same mask, which further simplifies the process.
[0042] In the above structure, the bottom of the gate metal layer 206 is connected to the side wall of the second P-type cap layer 204b with a lower activation concentration located below it, and the gate leakage current is relatively low. Figure 3 and Figure 4 The gate leakage current of the embodiment is large.
[0043] Example 4
[0044] A variation of the device implementation of the present invention is as follows: Figure 6 As shown, and Figure 3 The difference of the embodiment is that the sidewalls of the P-type cap layer 204a and the second P-type cap layer 204b are inclined instead of vertical, and the inclination angle is less than 90°. Figure 6 The length of the inclined sidewalls of the first P-type cap layers 204a and 204b is Figure 3 The vertical sidewalls of the first P-type cap layer 204 a and the second P-type cap layer 204 b of the embodiment are long, and the gate leakage current is small.
[0045] In the above structure, the sidewall inclination angles of the first P-type cap layer 204a and the second P-type cap layer 204b depend on the process conditions. The larger the inclination angle of the P-type cap layer sidewall, the longer the length of the sidewall, and the smaller the gate leakage current. At the same time, the longer the length of the channel under the first P-type cap layer 204a with a higher activation concentration, the greater the on-resistance of the device.
[0046] Those skilled in the art should know that the structural features mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures of the embodiments of the present invention.
[0047] Example 5
[0048] According to the structural features of the above-mentioned embodiments of the present invention, combined with the existing GaN high electron mobility transistor manufacturing process, a variety of methods for forming the device embodiments of the present invention can be obtained. An exemplary method for forming the device embodiment of the present invention is as follows: Figure 7 A-7H shows:
[0049] In the first step, a buffer layer 201 is formed on the substrate layer 200, a channel layer 202 is formed on the buffer layer 201, and then a barrier layer 203 is formed on the channel layer 202. Figure 7 As shown in A.
[0050] The material of the substrate layer 200 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), and sapphire.
[0051] The buffer layer 201 may include one material or a combination of multiple materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium nitride (GaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C) and iron (Fe), which is beneficial to reduce leakage current and crystal layer dislocation.
[0052] The material of the channel layer 202 is usually gallium nitride (GaN), but may also be other materials, and the energy band gap of the channel layer 202 is smaller than the energy band gap of the material of the barrier layer 203 located thereon.
[0053] The material of the barrier layer 203 is usually aluminum gallium nitride (AlGaN), but may also be other materials, and the energy band gap of the barrier layer 203 is larger than the energy band gap of the material of the channel layer 202 located therebelow.
[0054] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0055] In the second step, a preliminary P-type cap layer is formed on the barrier layer 203, and the P-type cap layer is activated for the first time to form a preliminary P-type cap layer 224a that has been activated once, such as Figure 7 As shown in B.
[0056] The material of the preliminary P-type cap layer 224a is usually doped gallium nitride (GaN), and may also be doped aluminum gallium nitride (AlGaN) or other materials, which contain magnesium (Mg) or other suitable P-type doping elements; the preliminary P-type cap layer 224a can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0057] In the third step, a P-type cap layer is continuously formed on the preliminary P-type cap layer 224a which has been activated once, and the P-type cap layer is activated for the second time, so as to form a P-type cap layer 214a with a higher activation concentration which has been activated twice and a P-type cap layer 214b with a lower activation concentration which has been activated once and is located above the P-type cap layer 214a. Figure 7 As shown in C.
[0058] The P-type cap layer 214 a with a higher activation concentration and activated twice and the P-type cap layer 214 b with a lower activation concentration and activated once thereon are usually formed by using the same material and the same process, and usually have different thicknesses.
[0059] In the fourth step, photolithography, dry etching, wet etching and other process steps are performed on the surface of the P-type cap layer 214b with a lower activation concentration that has been activated once, so as to form a patterned second P-type cap layer 204b with a lower activation concentration and a patterned first P-type cap layer 204a with a higher activation concentration located therebelow. Figure 7 As shown in D.
[0060] The first P-type cap layer 204 a with a relatively high activation concentration and the second P-type cap layer 204 b with a relatively low activation concentration may be formed integrally using the same photomask.
[0061] In the fifth step, if necessary, a dielectric layer 215 may be formed on the barrier layer 203 and the second P-type cap layer 204b with a lower activation concentration, such as Figure 7 As shown in E.
[0062] The dielectric layer 215 is usually composed of oxide or nitride, such as aluminum oxide (Al2O3), silicon oxide (SiO2), aluminum nitride (AlN), silicon nitride (Si3N4), etc.
[0063] In the sixth step, photolithography, dry etching, wet etching and other process steps are performed on the surface of the dielectric layer 215 to remove part of the surface of the second P-type cap layer 204b with a lower activation concentration, such as Figure 7 As shown in F.
[0064] Step 7: Form a patterned gate metal layer 206 on the second P-type cap layer 204b with a lower activation concentration, such as Figure 7 As shown in G.
[0065] The gate metal layer may be formed by evaporation, sputtering and other processes, and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials. The method of forming the patterned gate metal layer 206 may include process steps such as photolithography, dry etching, and wet etching.
[0066] Typically, the gate metal layer 206 forms a Schottky contact with the second P-type cap layer 204 b with a lower activation concentration thereunder.
[0067] In the eighth step, a source metal layer 207 is formed on the left side of the gate metal layer 206 and a drain metal layer 208 is formed on the right side of the gate metal layer 206. Figure 7 As shown in H.
[0068] The source metal layer and the drain metal layer may be formed by evaporation, sputtering and other processes, and their constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials. The method of forming the patterned source metal layer 207 and the drain metal layer 208 may include process steps such as photolithography, dry etching, and wet etching.
[0069] Typically, the source metal layer 207 and the drain metal layer 208 form ohmic contacts with the channel layer 202 thereunder.
[0070] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.
Claims
1. A transistor device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer, a source metal layer and a drain metal layer respectively located on both sides of the gate metal layer, wherein the channel layer and the barrier layer form a heterojunction and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction; characterized in that: The P-type cap layer at least includes a first P-type cap layer with a higher activation concentration located above the barrier layer and a second P-type cap layer with a lower activation concentration located above the first P-type cap layer. The first P-type cap layer depletes the two-dimensional electron gas to form an enhanced device, and the second P-type cap layer forms a Schottky contact with the gate metal layer.
2. The transistor device according to claim 1, characterized in that The gate metal layer has the same width as the first P-type cap layer and the second P-type cap layer located thereunder, and the gate metal layer is connected to the side wall of the second P-type cap layer; or The width of the gate metal layer is smaller than the width of the first P-type cap layer and the second P-type cap layer.
3. The transistor device according to claim 1, characterized in that The side walls of the first P-type cap layer and the second P-type cap layer are inclined side walls to increase the length of the side walls.
4. The transistor device according to any one of claims 1 to 3, characterized in that: A dielectric layer is also provided above the barrier layer, and the dielectric layer extends toward the P-type cap layer, so that the gate metal layer is separated from the side wall of the second P-type cap layer.