Semiconductor device

Abstract

A semiconductor device includes a p-type epitaxial layer over a substrate, a plurality of n-type wells in the p-type epitaxial layer, a p-type well contacting a first n-type well of the plurality of n-type wells, a first n-type embedded layer in the substrate, a source region in the p-type well, a drain region in a second n-type well of the plurality of n-type wells, and a second n-type embedded layer in the substrate. And a gate structure laterally between the source region and the drain region. Each of the plurality of n-type wells has a bottom surface in complete contact with the substrate. The p-type well overlaps an entirety of the first n-type embedded layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a laterally diffused semiconductor device. Background Art

[0002] The semiconductor industry has experienced rapid growth due to improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has come from shrinking semiconductor process nodes (e.g., shrinking process nodes toward the sub-20 nm node). As semiconductor devices scale down, new technologies are needed to maintain the performance of electronic components between generations. For example, low on-resistance and high breakdown voltage of transistors are desirable for various high power applications.

[0003] According to the difference in polarity, MOSFET can include two main categories. One category is n-type channel MOSFET; the other category is p-type channel MOSFET. On the other hand, according to the difference in structure, MOSFET can be further divided into three subcategories, namely planar MOSFET, lateral diffused MOS (LDMOS) FET and vertical diffused MOSFET. Utility Model Content

[0004] In some embodiments, a semiconductor device includes an epitaxial layer having a first conductivity type, above a substrate; a plurality of wells having a second conductivity type, in the epitaxial layer; a first trench region having the first conductivity type, in the epitaxial layer, the first trench region being located between a first well and a second well among the plurality of wells having the second conductivity type; a well having the first conductivity type, the well forming an interface with a third well among the plurality of wells having the second conductivity type; a gate structure, which is above the interface between the well having the first conductivity type and the third well among the plurality of wells having the second conductivity type; a first source / drain region having the first conductivity type, in the well; and a second source / drain region, which is in the first well and the second well among the plurality of wells having the second conductivity type, and above the first trench region having the first conductivity type.

[0005] In some embodiments, a semiconductor device includes a p-type epitaxial layer on a substrate; a plurality of n-type wells in the p-type epitaxial layer, each of the plurality of n-type wells having a bottom surface completely in contact with the substrate; a p-type well in contact with a first well among the plurality of n-type wells; a first n-type buried layer in the substrate, the p-type well and the first n-type buried layer overlapping in their entirety; a source region in the p-type well; a drain region in a second n-type well among the plurality of n-type wells; and a gate structure laterally interposed between the source region and the drain region.

[0006] In some embodiments, a semiconductor device includes an n-type buried layer in a substrate; a p-type epitaxial layer over the substrate and the n-type buried layer; a p-type well over the n-type buried layer, the p-type well having a bottom surface extending beyond opposite sidewall boundaries of the n-type buried layer; a plurality of n-type wells in the p-type epitaxial layer, wherein the plurality of n-type wells are alternately arranged in a plurality of trench regions in the p-type epitaxial layer; a gate structure extending across an interface between the p-type well and a first n-type well among the plurality of n-type wells; a source region in the p-type well; and a drain region over a first trench region among the plurality of trench regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 14 depicts a cross-sectional view of an intermediate stage in forming an LDMOS device according to some embodiments of the present disclosure;

[0009] Fig.15 A flowchart illustrating a method of forming an LDMOS device according to some embodiments of the present disclosure;

[0010] Fig.16 depicts a cross-sectional view of an LDMOS device according to some embodiments of the present disclosure;

[0011] Fig.17 depicts a cross-sectional view of an LDMOS device according to some embodiments of the present disclosure;

[0012] Fig.18 depicts a cross-sectional view of an LDMOS device according to some embodiments of the present disclosure;

[0013] Fig.19 A cross-sectional view of an LDMOS device according to some embodiments of the present disclosure is shown.

[0014]

Explanation of symbols

[0015] 102:Semiconductor substrate

[0016] 104: n-type buried layer (NBL) layer

[0017] 105: n type buried layer

[0018] 106: p-type epitaxial layer

[0019] 107: Additional n-type buried layer 2 (NBL2) region

[0020] 108: Isolation Structure

[0021] 109: Additional n-type buried layer 2 (NBL2) region

[0022] 110: High Voltage N-Well (HVNW)

[0023] 110a~110f: High Voltage N-Well (HVNW)

[0024] 112: High Voltage P-Well (HVPW)

[0025] 114: p-type groove / groove area

[0026] 116a: Reduced surface field (RESURF) oxide (Rox) layer

[0027] 116b: Reduced surface field (RESURF) oxide (Rox) layer

[0028] 118a: Gate dielectric layer

[0029] 118b: Gate dielectric layer

[0030] 120a: Gate electrode

[0031] 120b: Gate electrode

[0032] 122s: n-type source region

[0033] 122d: n-type drain region

[0034] 124s: n-type source region

[0035] 124d: n-type drain region

[0036] 126: p-type contact area

[0037] 128: Interlayer dielectric (ILD) layer

[0038] 130: Shared contact

[0039] 132: Gate contact

[0040] 134: Drain contact

[0041] 136: Substrate contact

[0042] 140:Metal wiring

[0043] 142: Silicide region

[0044] C1: IV curve

[0045] C2: IV curve

[0046] D1: Non-zero distance

[0047] D2: Non-zero distance

[0048] D3: Width

[0049] D4: Drift zone length

[0050] D5: Drift zone length

[0051] DR1: Drift Zone

[0052] DR2: Drift Zone

[0053] GS1: Gate structure

[0054] GS2: Gate structure

[0055] IMP1: n-type ion implantation process

[0056] IMP2: n-type ion implantation process

[0057] IMP3: p-type ion implantation process

[0058] M1: Patterned mask layer

[0059] M2: Patterned mask layer

[0060] M3: Patterned mask layer

[0061] O1: Opening

[0062] O2: Opening

[0063] O3: Opening

[0064] P1: Depth

[0065] P2: Depth

[0066] S101: Block

[0067] S102: Block

[0068] S103: Block

[0069] S104: Block

[0070] S105: Block

[0071] S106: Block

[0072] S107: Block

[0073] S108: Block DETAILED DESCRIPTION

[0074] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0075] In addition, spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features as depicted in the figures to another or other elements or features. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. As used herein, "substantially," "approximately," "about," "approximately," or "substantially" may generally mean within 20% or within 10% or within 5% of a given value or range. The quantities given herein are approximate, meaning that the terms "substantially," "about," "approximately," or "substantially" may be inferred without being explicitly stated. However, those skilled in the art will recognize that the values ​​or ranges recited throughout the description are merely examples and may be reduced or changed as the integrated circuit is scaled down.

[0076] The present disclosure will be described with respect to embodiments in a specific case, namely a lateral diffused metal oxide semiconductor (LDMOS) field effect transistor and more specifically an n-type lateral metal oxide semiconductor (NLDMOS) transistor. However, the embodiments of the present disclosure may also be applied to a variety of metal oxide semiconductor transistors. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings. LDMOS devices are widely used in various high power applications, such as DC-DC buck converters, AC-DC flyback controllers, motor drives, etc. A limiting factor for such high power applications is the breakdown voltage of the LDMOS device. Therefore, in various embodiments, the present disclosure provides an LDMOS device having an improved configuration of doped regions, wherein the multiple doped regions are customized to improve the breakdown voltage of the LDMOS device to be higher than, for example, 100 volts.

[0077] Figures 1 to 14 A cross-sectional view of an intermediate stage in forming a transistor according to some embodiments of the present disclosure is shown. Figures 1 to 14 The steps in are also schematically reflected in the diagram shown in Fig.15 The transistors formed include adjacent LDMOS transistors sharing a common source terminal according to some exemplary embodiments. Throughout the various views and illustrative embodiments, similar reference numerals are used to designate similar elements. It should be understood that additional operations may be performed by Figures 1 to 14 The depicted before, during and after processes are provided, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable.

[0078] Figure 1 A cross-sectional view of an initial structure is shown. The initial structure includes a semiconductor substrate 102. The semiconductor substrate 102 may include a semiconductor wafer such as a silicon wafer. Alternatively, the semiconductor substrate 102 may include other elemental semiconductors such as germanium. The semiconductor substrate 102 may also include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In addition, the semiconductor substrate 102 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In some embodiments, the semiconductor substrate 102 includes Figure 1 The p-type silicon substrate (p-substrate) is marked as “Psub”.

[0079] Figure 1Also shown is a patterned mask layer M1 formed over the substrate 102 to define the location of an n-type buried layer (NBL) 104 subsequently formed in the substrate 102. The patterned mask layer M1 may include an organic material such as a photoresist material, and may be formed by the following steps: using a spin coating process, followed by patterning the photoresist material, using a suitable lithography technique to form one or more openings O1 extending through the patterned mask layer M1 to expose a target area of ​​the substrate 102. For example, the photoresist layer material is irradiated (exposed), and developed to remove portions of the photoresist material. In more detail, a mask (not shown) may be placed over the photoresist material, and the photoresist material may then be exposed to a radiation beam, which may be an ultraviolet (UV) or an excimer laser such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used.

[0080] exist Figure 2 In the present embodiment, in the presence of the patterned mask layer M1, an n-type ion implantation process IMP1 is performed to dope n-type impurities (e.g., phosphorus, arsenic, antimony, or the like) into the p-type substrate 102 to form an n-type buried layer (NBL) layer 104. The n-type ion implantation is performed using the patterned mask layer M1 as an implantation mask so that the NBL 104 has a top view pattern or geometry that inherits the top view pattern or geometry of the opening O1 of the patterned mask layer M1. In this way, the top view pattern of the opening O1 can be designed to define a desired top view pattern of the NBL 104. In some embodiments, the n-type ion implantation process IMP1 is performed at a rate of about 1E13 atoms / cm 3 to about 1E15 atoms / cm 3 The n-type impurities are implanted at a dosage of about 50 KeV to about 200 KeV.

[0081] exist Figure 3 In the embodiment of the present invention, after forming the NBL 104, the patterned mask layer M1 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask M1 is increased until the photoresist mask M1 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be utilized.

[0082] exist Figure 4 middle, Figure 4 A p-type epitaxial layer 106, labeled "P-epi" in FIG. 1 , is formed over the p-type substrate 102 and the NBL 104. In some embodiments, the p-type epitaxial layer 106 is a crystalline semiconductor material (e.g., silicon, germanium, or silicon germanium) formed using a suitable epitaxial growth method, such as, for example, vapor / solid / liquid phase epitaxy (VPE, SPE, LPE) or metal-organic CVD (MOCVD) or molecular beam epitaxy (MBE) or the like. A dose of p-type impurities (e.g., boron, boron fluoride, indium, or the like) is introduced into the epitaxially grown material in situ during the epitaxial growth or by an ion implantation process performed after the epitaxial growth, or by a combination thereof. In some embodiments, the p-type epitaxial layer 106 has a thickness ranging from about 5 μm to about 10 μm, and a resistivity ranging from about 10 ohm-cm to about 100 ohm-cm, which is intended to prevent leakage and improve breakdown voltage.

[0083] exist Figure 5 In the embodiment of the present invention, an isolation structure 108 such as a shallow trench isolation (STI) region or a local oxidation of silicon (LOCOS) (or field oxide, FOX) region including an isolation feature can be formed in the p-type epitaxial layer 106 to define and electrically isolate various active regions so as to prevent leakage current from flowing between adjacent active regions. As an example, the formation of the STI feature can include dry etching a trench in the trench and filling the trench with an insulator material such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench can have a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In some other embodiments, the STI structure can be produced using a process sequence such as: growing a liner oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning the STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, using a chemical mechanical polishing (CMP) process to etch back and planarize, and using a nitride strip process to remove the silicon nitride.

[0084] exist Figure 6In the embodiment, a patterned mask layer M2 is formed over the p-type epitaxial layer 106 to define the location of a high voltage N-well (HVNW) 110, a high voltage P-well (HVPW) 112, and a p-type trench 114 formed in subsequent processing. The patterned mask layer M2 may include an organic material such as a photoresist material, and may be formed by the following steps: using a spin coating process, followed by patterning the photoresist material, using a suitable lithography technique to form one or more openings O2 extending through the patterned mask layer M2 to expose the HVNW target area of ​​the p-type epitaxial layer 106. For example, the photoresist layer material is irradiated (exposed), and developed to remove portions of the photoresist material. In more detail, a mask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, which may be ultraviolet (UV) or an excimer laser such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used.

[0085] exist Figure 7 In the embodiment of the present invention, in the presence of the patterned mask layer M2, an n-type ion implantation process IMP2 is performed to dope n-type impurities (e.g., phosphorus, arsenic, antimony, or the like) into the p-type epitaxial layer 106 to form high voltage N-wells (HVNW) 110a, 110b, 110c, 110d, 110e, 110f. These N-wells 110a to 110f are collectively referred to as HVNW 110. The n-type ion implantation IMP2 is performed using the patterned mask layer M2 as an implantation mask so that the HVNW 110 has a top view pattern or geometry that inherits the top view pattern or geometry of the corresponding opening O2 of the patterned mask layer M2. In this way, the top view pattern of the opening O2 can be designed to define a desired top view pattern of the HVNW 110. In some embodiments, the n-type ion implantation process IMP2 is performed at a rate of about 1E12 ions / cm 3 to about 1E13 atoms / cm 3 The n-type impurities are implanted at a dosage of about 50 KeV to about 3000 KeV.

[0086] In some embodiments, HVNW 110 has an n-type impurity concentration less than that of NBL 104. In some embodiments, the pattern of patterned mask layer M2 is designed in a manner such that none of HVNW 110 vertically overlaps NBL 104. In detail, NBL 104 has a right sidewall boundary that is laterally retracted by a non-zero distance D1 from a left sidewall boundary of right HVNW 110d, and NBL 104 has a left sidewall boundary that is laterally retracted by a non-zero distance D2 from a right sidewall boundary of right HVNW 110c, and thus NBL 104 can be confined to the source side of the resulting LDMOS device, thereby improving the electrical isolation properties of the resulting LDMOS device and thus improving the breakdown voltage. In some embodiments, non-zero distance D1 is the same as non-zero distance D2. In some other embodiments, non-zero distance D1 is different from (e.g., greater than or less than) non-zero distance D2.

[0087] In some embodiments, each HVNW 110 has a depth P1 that is substantially the same as the thickness of the p-type epitaxial layer 106. In other words, each HVNW 110 vertically extends through the entire thickness of the p-type epitaxial layer 106 and terminates the top surface of the p-type substrate 102. Because the NBL 104 is formed within the p-type substrate 102, the top surface of the NBL 104 is flush with the bottom surface of the HVNW 110 without overlapping the top surface. In contrast to conventional LDMOS devices that may have a deep p-well (DPW) formed in the p-type epitaxial layer and a HVNW formed above the DPW, resulting in a relatively high level pn junction region, such as Figure 7 The improved configuration shown in FIG. 1 ensures that a horizontal pn junction region appears at the top surface of the p-type substrate 102. This design improves vertical junction breakdown and enhances breakdown voltage.

[0088] In some embodiments, the trench regions 114 of the p-type epitaxial layer 106 are shielded by the patterned mask layer M2, and thus these regions 114 are not doped by the ion implantation process IMP2 and maintain their p-type characteristics. These regions 114, also referred to as p-type trenches or p-type trench regions 114 in this case, are alternately arranged with the HVNWs 110 in the horizontal direction. Specifically, each p-type trench 114 is inserted between two adjacent ones of the HVNWs 110 without an additional implantation step and an associated implantation mask. Such an alternating arrangement can improve lateral PN junction region collapse, thereby further improving the breakdown voltage of the resulting LDMOS device. In some embodiments, each p-type trench 114 can have a light n-type impurity concentration that is less than the n-type impurity concentration of the HVNW 110 due to unintentional lateral diffusion from the HVNW 110. Although four p-type trenches 114 are formed between the STI regions 108 in the illustrative embodiment, additional p-type trenches 114 may be included between the STI regions 108 to further improve the breakdown voltage. In some embodiments, the plurality of p-type trenches 114 are located in a "non-NBL region", i.e., a region that does not overlap with the NBL layer 104 on the p-type substrate 102. This design is used to enhance the reduced surface field (RESURF) effect around the drain region of the transistor, thereby improving the breakdown voltage of the resulting LDMOS device. In particular, by forming the p-type trenches 114 that do not overlap with the NBL layer 104, the electric field at the surface of the p-type epitaxial layer 106 can be reduced, thereby improving the breakdown voltage. In some embodiments, each p-type trench 114 has a trench width ranging from about 0.5 μm to about 2 μm.

[0089] exist Figure 8 In the embodiment of the present invention, after forming the HVNW 110, the patterned mask layer M2 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask M2 is increased until the photoresist mask M2 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be utilized.

[0090] Next, another patterned mask layer M3 is formed over the p-type epitaxial layer 106 to define the location of a high voltage P-well (HVPW) 112 to be formed in subsequent processing. The patterned mask layer M3 may include an organic material such as a photoresist material, and may be formed by the following steps: using a spin coating process, followed by patterning the photoresist material, using a suitable lithography technique to form one or more openings O3 extending through the patterned mask layer M3 to expose the HVPW target area of ​​the p-type epitaxial layer 106. For example, the photoresist layer material is irradiated (exposed), and developed to remove portions of the photoresist material. In more detail, a mask (not shown) may be placed over the photoresist material, and the photoresist material may then be exposed to a radiation beam, which may be an ultraviolet (UV) or an excimer laser such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material may be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation may be performed to harden the exposed photoresist material, and a developer may be used to remove exposed or unexposed portions of the photoresist material depending on whether a positive or negative resist is used.

[0091] exist Fig. 9 In the present embodiment, in the presence of the patterned mask layer M3, a p-type ion implantation process IMP3 is performed to dope p-type impurities (e.g., boron, boron fluoride, indium, or the like) into the p-type epitaxial layer 106 to form a high voltage P-well (HVPW) 112 in contact with the HVNWs 110a, 110c, 110d, 110f. The p-type ion implantation IMP3 is performed using the patterned mask layer M3 as an implantation mask so that the HVPW 110 has a top view pattern or geometry that inherits the top view pattern or geometry of the corresponding opening O3 of the patterned mask layer M3. In this way, the top view pattern of the opening O3 can be designed to define a desired top view pattern of the HVPW 112. For example, the HVPW 112 forms an interface with the HVNW 110c and an interface with the HVNW 110d. In some embodiments, the p-type ion implantation process IMP3 is performed at a rate of about 1E12 ions / cm 3 to about 1E13 atoms / cm 3 The p-type impurities are implanted at a dosage of about 50 KeV to about 3000 KeV.

[0092] In some embodiments, the HVPW 112 has a p-type impurity concentration less than the n-type impurity concentration of the NBL 104. In some embodiments, the pattern of the patterned mask layer M3 is designed in a manner such that none of the HVPWs 112 vertically overlaps the entirety of the NBL 104. In detail, the HVPW 112 has a right sidewall boundary extending laterally beyond the opposite sidewall boundary to reach the bottom surface of the HVNW 110. The NBL 104 has a right sidewall boundary laterally retracted by a non-zero distance D1 from the right sidewall boundary of the HVPW 112, and the NBL 104 has a left sidewall boundary laterally retracted by a non-zero distance D2 from the left sidewall boundary of the HVPW 112, and thus the NBL 104 can be confined to just below a source region subsequently formed in the HVPW 112, thereby improving the electrical isolation properties of the resulting LDMOS device and thus improving the breakdown voltage.

[0093] In some embodiments, each HVPW 112 has a depth P2 that is substantially the same as the thickness of the p-type epitaxial layer 106. In other words, the HVPW 112 vertically extends through the full thickness of the p-type epitaxial layer 106 and terminates at the top surface of the p-type substrate 102. Because the NBL 104 is formed within the p-type substrate 102, the top surface of the NBL 104 is flush with and completely overlaps the bottom surface of the HVPW 112. In addition, because the HVNW 110 also vertically extends through the full thickness of the p-type epitaxial layer 106, the bottom surface of the HVNM 110 is flush with the bottom surface of the HVPW 112. In some embodiments, the p-type trenches 114 are shielded by the patterned mask layer M3 during the ion implantation process IMP3, and thus these p-type trenches 114 are not doped by the ion implantation process IMP3 and thus have a lower p-type impurity concentration than the HVPW 112.

[0094] exist Fig.10 In the embodiment of the present invention, after forming the HVPW 112, the patterned mask layer M3 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask M3 is increased until the photoresist mask M3 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be utilized.

[0095] Figures 6 to 10 An exemplary sequential process is shown including forming the HVNW 110, followed by forming the HVPW 112. However, in some alternative embodiments, the HVPW 112 may be formed in advance in the p-type epitaxial layer 106 by using a suitable patterned mask layer as an implantation mask, followed by forming the HVNW 110 in the p-type epitaxial layer 106 by using another patterned mask as an implantation mask.

[0096] exist Fig.11, RESURF oxide (Rox) layers 116a and 116b are formed over the HVNWs 110b, 110c and 110d, 110e, respectively. Each of the Rox layers 116a and 116b is disposed over the corresponding p-type well region 114. In some embodiments, the Rox layers 116a and 116b may be formed by, for example, depositing or growing an oxide layer (e.g., a SiO2 layer) across the p-type epitaxial layer 106, followed by patterning the oxide layer into the Rox layers 116a and 116b by using a suitable etching technique (e.g., dry etching, wet etching, or a combination thereof). The Rox layers 116a and 116b are used to reduce the electric field at the top surface of the p-type epitaxial layer 106, especially at the drift region of the LDMOS device, where collapse is likely to occur. By reducing the surface field using the Rox layers 116a and 116b, the collapse voltage of the resulting LDMOS device may be further improved. In some embodiments, one or more STI regions are formed in the drift region directly below the Rox layers 116 a and 116 b .

[0097] exist Fig.12 , gate dielectric layers 118a and 118b are formed over the p-type epitaxial layer 106, followed by the formation of gate electrodes 120a and 120b over the respective gate dielectric layers 118a and 118b. The gate dielectric layer 118a and the overlying gate electrode 120a together serve as a gate structure GS1 extending over the Rox layer 116a and across the interface between the HVPW 112 and the left HVNW 110c. The gate dielectric layer 118b and the overlying gate electrode 120b together serve as a gate structure GS2 extending over the Rox layer 116b and across the interface between the HVPW 112 and the right HVNW 110d. In some embodiments, the gate structures GS1 and GS2 are formed by, for example, the following steps: growing an oxide layer on the top surface of the p-type epitaxial layer 106 using a thermal oxidation process or an in-situ steam generation (ISSG) process, depositing a gate electrode layer above the oxide layer, and then patterning the gate electrode layer and the oxide layer into gate electrodes 120a, 120b and gate dielectric layers 118a and 118b using suitable lithography and etching techniques.

[0098] The resulting gate dielectric layer 118a has a right side surface that is adjacent to or aligned with the right side surface of the gate electrode 120a, and a left side surface that contacts the right side surface of the Rox layer 116a and is therefore offset from the left side surface of the gate electrode 120a. Similarly, the gate dielectric layer 118b has a left side surface that is adjacent to or aligned with the left side surface of the gate electrode 120b, and a right side surface that contacts the left side surface of the Rox layer 116b and is therefore offset from the right side surface of the gate electrode 120b. In some embodiments, the gate dielectric layers 118a and 118b have a thickness that is less than the thickness of the Rox layers 116a and 116b because the Rox layers 116a and 116b play a different role than the gate dielectric layers 118a and 118b. In detail, the thickness of the Rox layers 116a and 116b is controlled to achieve the desired electric field reduction in the LDMOS drift region, and therefore has a greater thickness than the gate dielectric layers 118a and 118b.

[0099] In some embodiments, the gate dielectric layers 118a and 118b have the same material as the Rox layers 116a and 116b (e.g., silicon oxide). In some other embodiments, the gate dielectric layers 118a and 118b have a material different from that of the Rox layers 116a and 116b. For example, the gate dielectric layers 118a and 118b may include a high-k dielectric material, silicon oxynitride, other suitable materials, or a combination thereof as needed. The high-k material may be selected from the following: metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, hafnium oxide, or a combination thereof. The gate dielectric layers 118a and 118b may have a multilayer structure, such as a silicon oxide layer and another high-k material layer. The gate dielectric layers 118 a and 118 b may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, other suitable processes, or combinations thereof.

[0100] In some embodiments, the gate electrodes 120a and 120b may include doped polycrystalline silicon (or polysilicon). Alternatively, the gate electrodes 120a and 120b may include metals such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The gate electrodes 120a and 120b may be formed by CVD, PVD, electroplating, and other appropriate processes. The gate electrodes 120a and 120b may have a multi-layer structure and may be formed in a multi-step process using a combination of different processes.

[0101] exist Fig.13A , n-type source regions 122s and 124s are formed in the HVPW 112, and n-type drain regions 122d and 124d are formed in respective HVNWs 110. In detail, the n-type drain region 122d is formed in the HVNWs 110a, 110b and above the p-type tank region 114. The p-type tank region 114 directly below the n-type drain region 122d thus has a smaller height (or a lower top surface) than the p-type tank region 114 directly below the gate structure GS1. Similarly, the n-type drain region 124d is formed in the HVNWs 110e, 110f and above the p-type tank region 114. The p-type tank region 114 directly below the n-type drain region 124d has a smaller height (or a lower top surface) than the p-type tank region 114 directly below the gate structure GS2.

[0102] The n-type source / drain regions are formed using an n-type ion implantation process to dope n-type impurities (e.g., phosphorus, arsenic, antimony, or the like) into target portions within the HVPW 112 and the HVNW 110. In some embodiments, the n-type source region 122s and the n-type drain region 122d have a higher n-type impurity concentration than the n-type impurity concentration within the HVNW 110 and the p-type impurity concentration within the HVPW 112. The n-type source region 122s, the n-type drain region 122d, and the gate structure GS1 together serve as an n-type LDMOS, wherein the gate electrode 120a serves as its gate terminal, the n-type source region 122s serves as its source terminal, and the drain region 122d serves as its drain terminal. Similarly, the n-type source region 124s and the n-type drain region 124d have a higher n-type impurity concentration than the n-type impurity concentration within the HVNW 110 and the p-type impurity concentration within the HVPW 112. The n-type source region 124s, the n-type drain region 124d and the gate structure GS2 together serve as another n-type LDMOS, wherein the gate electrode 120b serves as its gate terminal, the n-type source region 124s serves as its source terminal and the drain region 124d serves as its drain terminal. In some embodiments, the dopant concentration of the n-type source / drain regions 122s / 122d and 124s / 124d is about 10 19 Atom / cm 3 to about 10 20 Atom / cm 3 , and other dopant concentration ranges are within the scope of the present disclosure.

[0103] Fig.13AAlso shown are p-type contact regions 126 formed in respective HVPWs 112. The p-type contact regions 126 are formed using a p-type ion implantation process to dope p-type impurities (e.g., boron, boron fluoride, indium, or the like) into target portions within the HVPWs 112. In some embodiments, the p-type contact regions 126 have a higher p-type impurity concentration than the p-type impurity concentration within the HVPWs 112 and function as substrate contacts and / or bulk contacts of integrated circuit structures.

[0104] In some embodiments, after the ion implantation process for forming the n-type source / drain regions 122s / 122d and 124s / 124d, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities.

[0105] The LDMOS device on the left side of the HVPW 112 has a drift region DR1 with a drift region length D4 extending laterally from the n-type drain region 122d to the left sidewall boundary of the HVPW 112. In some embodiments, the ratio of the non-zero distance D2 to the drift region length D4 is less than 1 / 4. If the ratio is too large (e.g., much larger than 1 / 4), the NBL layer 104 may be too narrow, resulting in a potential undesirable leakage path between the HVPW 112 and the p-type substrate 102. If the ratio is too small (e.g., less than 1 / 10), the NBL layer 104 may be too wide, resulting in a lower breakdown voltage. In some embodiments, the drift region length D4 in the left LDMOS device is in the range of 5 μm to 15 μm. In some embodiments, the HVPW 112 has a width D3 in the range of 1 μm to 3 μm.

[0106] The LDMOS device on the right side of the HVPW 112 has a drift region DR2 with a drift region length D5 extending laterally from the n-type drain region 124d to the right sidewall boundary of the HVPW 112. In some embodiments, the ratio of the non-zero distance D1 to the drift region length D4 is less than 1 / 4. If the ratio is too large (e.g., much larger than 1 / 4), the NBL layer 104 may be too narrow, resulting in a potential undesirable leakage path between the HVPW 112 and the p-type substrate 102. If the ratio is too small (e.g., less than 1 / 10), the NBL layer 104 may be too wide, resulting in a lower breakdown voltage. In some embodiments, the drift region length D5 in the right LDMOS device is in the range of 5 μm to 15 μm. In some embodiments, the drift region length D4 in the left LDMOS device is the same as the drift region length D5 in the right LDMOS device. In some embodiments, the drift region length D4 in the left LDMOS device is different from (e.g., smaller than or larger than) the drift region length D5 in the right LDMOS device.

[0107] The gate structure GS1 overlaps the p-type groove 114 in the p-type epitaxial layer 106. In detail, the gate structure GS1 overlaps the p-type groove 114 at the edge region above the Rox layer 116a. In addition, the n-type drain region 122d overlaps the p-type groove 114. Similarly, the gate structure GS2 overlaps the p-type groove 114 at the edge region above the Rox layer 116b, and the n-type drain region 124d overlaps the p-type groove 114. By using the p-type groove 114 confined to the gate edge region and the drain region, the breakdown voltage of the LDMOS device can be improved. The NBL layer 104 overlaps the n-type source regions 122s and 124s, and does not overlap the n-type drain regions 122d and 124d. By using the NBL layer 104 confined to the source side of the LDMOS device, the breakdown voltage of the LDMOS device can be improved.

[0108] Fig. 13B The simulation results are shown in FIG. Fig.13A The breakdown voltage produced by the structure in FIG. Fig. 13B The following is a graph showing the current-voltage characteristics of an LDMOS device obtained from simulation results prepared using device simulation software also known as technology computer-aided design (TCAD). Fig. 13B In the example, the logarithmic drain current (Log Id) is plotted on the vertical axis, and the drain current (V D ) is plotted on the horizontal axis. IV curve C1 represents the current-voltage characteristics of an LDMOS device having an NBL layer extending to just below the drain region and a DPW formed vertically between the NBL layer and the drain region. IV curve C2 represents the current-voltage characteristics of an LDMOS device having an NBL layer extending to just below the drain region and a DPW formed vertically between the NBL layer and the drain region. Fig.13A . The IV curves C1 and C2 show the breakdown voltage at the point where the current increases sharply with almost no voltage increase, i.e., near the turning point of these curves. The breakdown voltage shown by IV curve C1 is between about 85 volts (V) and about 100 V (e.g., 90 V). The breakdown voltage shown by IV curve C2 is between about 140 V and about 160 V (e.g., 150 V). These simulation results show that the breakdown voltage of the LDMOS device can be reduced, for example, by using a local NBL layer 104, a deepened HVNW 110, and a p-type trench 114 alternately configured with a deepened HVNW 110 (e.g., Fig.13A ) is improved, for example, from 90 V to 150 V. This improvement in breakdown voltage is due to an improved electrical potential energy profile, specifically a lower potential achieved at the source side of the LDMOS device.

[0109] exist Fig.14In the embodiment of the present invention, an interlayer dielectric (ILD) layer 128 is deposited to cover the LDMOS device. The ILD layer 128 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (not shown) is deposited on the substrate gate structures GS1, GS2 and the p-type epitaxial layer 106 before depositing the ILD layer 128. The CESL may include a dielectric material having a different etch rate than the material of the overlying ILD layer 128 , such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0110] Fig.14 A common contact 130 formed in the ILD layer 128 and over the p-type contact region 126 is further illustrated. The common contact 130 is electrically coupled to the p-type contact region 126 and the source regions 122s, 124s on opposite sides of the p-type contact region 126. For example, a common silicide region may be formed to continuously cross the source regions 122s, 124s, and the p-type contact region 126, and the common contact 130 is formed over the common silicide region and electrically coupled to the source regions 122s, 124s, and the p-type contact region 126. Fig.14 Further illustrated are gate and drain contacts 132 and 134 formed in the ILD layer 128 and respectively over the gate electrodes 120 a , 120 b and the drain regions 122 d , 124 d . Fig.14 Also shown is a substrate contact 136 over the p-type contact region 126 in contact with the isolation structure 108 .

[0111] Each of these contacts 130-136 may include one or more metal layers, such as a barrier layer, a diffusion layer, and a fill material. For example, in some embodiments, each of the contacts 130-136 includes a barrier layer and a conductive material, and is electrically coupled to an underlying conductive feature (e.g., a silicide region). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Fig.14Further illustrated are metal lines 140 extending over the contacts 130 to 136. The metal lines 140 may each include one or more metal layers, such as a barrier layer, a diffusion layer, and a filling material.

[0112] The contacts 130 to 136 and the metal line 140 may be formed by forming trenches and contact openings in the ILD layer 128 in a trench first or via first approach using, for example, a dual damascene process, such as using suitable photolithography and etching processes, depositing one or more metal material layers in the contact openings. Next, a planarization process such as CMP may be performed to remove excess metal material from the surface of the ILD layer 128.

[0113] Fig.15 Methods of forming an integrated circuit are illustrated in accordance with some embodiments. Although the methods are illustrated and / or described as a series of actions or events, it should be understood that the methods are not limited to the illustrated order or actions. Thus, in some embodiments, the actions may be performed in an order different from that illustrated, and / or may be performed simultaneously. Additionally, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other non-illustrated actions or events may be included.

[0114] At block S101 , one or more NBL layers are formed on a substrate. Figures 1 to 3 Cross-sectional views of some embodiments corresponding to the actions in block S101 are shown.

[0115] At block S102 , a p-type epitaxial layer is grown on a substrate. Figure 4 Cross-sectional views of some embodiments corresponding to the actions in block S102 are shown.

[0116] At block S103 , an STI region is formed in the p-type epitaxial layer. Figure 5 Cross-sectional views of some embodiments corresponding to the actions in block S103 are shown.

[0117] At block S104 , HVPWs and HVNWs are formed in the p-type epitaxial layer, with p-type trenches inserted between the HVNWs. Figures 6 to 10 Cross-sectional views of some embodiments corresponding to the actions in block S104 are shown.

[0118] At block S105 , a Rox layer is formed on the HVNW and the p-type trench. Fig.11 Cross-sectional views of some embodiments corresponding to the actions in block S105 are shown.

[0119] In block S106 , a gate structure is formed on the HVNWs and extends between the HVNWs to the HVPWs. Fig.12 Cross-sectional views of some embodiments corresponding to the actions in block S106 are shown.

[0120] At block S107 , n-type source / drain regions and p-type contact regions are formed in HVNW and HVPW. Fig.13A Cross-sectional views of some embodiments corresponding to the actions in block S107 are shown.

[0121] At block S108 , metal contacts and metal wiring are formed over the n-type source / drain regions and the p-type contact regions. Fig.14 Cross-sectional views of some embodiments corresponding to the actions in block S108 are shown.

[0122] Fig.16 A cross-sectional view of an LDMOS device according to some embodiments of the present disclosure is shown. Fig.16 The structure in is similar to Fig.14 The structure, except Fig.16 The structure includes a silicide region 142 formed on the gate electrodes 120a, 120b, the source regions 122s, 124s, the drain regions 122d, 124d and the p-type contact region 126, and contacts 130 to 136 are formed on the respective silicide regions 142. In some embodiments, after completing Fig.13A After the step of , the silicide region 142 is formed by the following operation: first, a metal (not shown) capable of reacting with the single crystalline silicon of the underlying p-type epitaxial layer 106 and the polycrystalline silicon of the underlying gate electrodes 120a, 120b is deposited over the exposed portions of the p-type epitaxial layer 106 and the gate electrodes 120a, 120b, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals or alloys thereof; and then a thermal annealing process is performed to form the silicide region 142. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 142 is referred to as a silicide region, if the p-type epitaxial layer 106 and / or the gate electrodes 120a, 120b include germanium or silicon germanium, the silicide region 142 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide).

[0123] like Fig.16 As shown in FIG. 1 , the source region 122s of the left LDMOS device, the source region 124s of the right LDMOS device, and the p-type contact region 126 share a common continuous silicide region 142. Therefore, the common contact 130 can be electrically coupled to the source regions 122s, 124s, and the p-type contact region 126 by using the common silicide region 142.

[0124] Fig.17 A cross-sectional view of an LDMOS device according to some embodiments of the present disclosure is shown. Fig.17 The structure shown in Fig.16 The structure, except Fig.17 The structure further includes Fig.17 Another n-type buried layer 105, labeled as "NBL2" in the figure, is formed to support the bottom side of NBL 104. In some embodiments, NBL2 105 is formed before epitaxially growing p-type epitaxial layer 106 on the substrate. NBL2 105 is formed by ionizing the substrate at a rate of about 1E12 ions / cm 3 to about 1E14 atoms / cm 3 The NBL2 105 is formed by implanting n-type impurities (e.g., phosphorus, arsenic, antimony, or the like) into the p-type substrate 102 at a dose of about 50 KeV to about 300 KeV. In some embodiments, the NBL2 105 has an n-type impurity concentration that is less than the n-type impurity concentration of the NBL 104. The NBL2 105 may be formed before or after the formation of the NBL 104. In some embodiments, the NBL2 104 extends beyond the opposite sidewall boundary of the NVPW to directly below the HVNW 110. By forming the high-dose NBL 104 and the low-dose NBL2 105 to support the bottom side of the NBL 104 and keep the high-dose NBL 104 and the low-dose NBL2 105 confined to the source side of the LDMOS device, the breakdown voltage of the LDMOS device may be improved.

[0125] Fig.18 A cross-sectional view of an LDMOS device according to some embodiments of the present disclosure is shown. Fig.18 The structure shown in Fig.17 In addition to the high dose of NBL 104 Fig.18 In some embodiments, the low-dose NBL2 105 has an opposite sidewall boundary substantially aligned with the sidewall boundary of the HVPW 112. By forming the low-dose NBL2 105 confined to the source side of the LDMOS device, the breakdown voltage of the LDMOS device can be improved.

[0126] Fig.19 A cross-sectional view of an LDMOS device according to some embodiments of the present disclosure is shown. Fig.19 The structure shown in Fig.18 , except that additional NBL2 regions 107 and 109 are formed directly below drain regions 122d and 124d, respectively. In some embodiments, NBL2 regions 107 and 109 are formed simultaneously with NBL2 region 105 and thus have the same impurity type and concentration as NBL2 region 105. NBL2 regions 105, 107, 109 are separated from each other, rather than a continuous n-layer buried layer spanning HVNW 110 and HVPW 112. Such discontinuous NBL regions can produce an improved breakdown voltage of the LDMOS device.

[0127] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no specific advantages are required for all embodiments. One advantage is that the breakdown voltage of the LDMOS device can be increased to a range from 100 V to 200 V without performing a double epitaxial step on the substrate. Another advantage is that the LDMOS device with improved breakdown voltage can be widely used in various high power applications, such as DC-DC buck converters, AC-DC flyback controllers, motor drives, etc.

[0128] According to some embodiments, a device includes an epitaxial layer having a first conductivity type over a substrate, a plurality of wells having a second conductivity type in the epitaxial layer, and a first trough region having the first conductivity type in the epitaxial layer. The first trough region is located between a first well and a second well of the plurality of wells having the second conductivity type. The device further includes a well having the first conductivity type, the well forming an interface with a third well of the plurality of wells having the second conductivity type; a gate structure, which is above the interface between the well having the first conductivity type and the third well of the plurality of wells having the second conductivity type; a first source / drain region in the well having the first conductivity type; and a second source / drain region, which is in the first well and the second well of the plurality of wells having the second conductivity type. The second source / drain region is above the first trough region having the first conductivity type. In some embodiments, the first trough region having the first conductivity type has a bottom surface in contact with the substrate. In some embodiments, the first trough region having the first conductivity type has a top surface in contact with the second source / drain region. In some embodiments, the first tub region having the first conductivity type has a height less than a height of the well having the first conductivity. In some embodiments, the device further includes a second tub region having the first conductivity type, the second tub region being in the epitaxial layer and interposed between the second well and the third well of the plurality of wells having the second conductivity type. In some embodiments, the second tub region having the first conductivity type has a top surface higher than a top surface of the first tub region. In some embodiments, the gate structure overlaps the second tub region having the first conductivity type. In some embodiments, the device further includes a reduced surface field (RESURF) oxide layer extending from below the gate structure to the second source / drain region. The RESURF oxide layer is above the second tub region having the first conductivity type. In some embodiments, the RESURF oxide layer does not overlap the first tub region having the first conductivity type. In some embodiments, the gate structure includes a gate dielectric layer and a gate electrode above the gate dielectric layer, and the RESURF oxide layer has a thickness greater than a thickness of the gate dielectric layer.

[0129] According to some embodiments, a device includes a p-type epitaxial layer above a substrate, a plurality of n-type wells in the p-type epitaxial layer, a p-type well contacting a first n-type well among the plurality of n-type wells, a first n-type buried layer in the substrate, a source region in the p-type well, a drain region in a second n-type well among the plurality of n-type wells, and a gate structure laterally between the source region and the drain region. Each of the plurality of n-type wells has a bottom surface that is completely in contact with the substrate. The p-type well overlaps the entirety of the first n-type buried layer. In some embodiments, the first n-type buried layer has opposite sidewall boundaries that are laterally retracted from opposite sidewall boundaries of the p-type well, respectively. In some embodiments, the first n-type buried layer does not overlap any of the plurality of n-type wells. In some embodiments, the device further includes a first p-type trough region, the first p-type trough region being directly below the gate structure, and the first p-type trough region separating the first n-type well among the plurality of n-type wells from the second n-type well among the plurality of n-type wells. In some embodiments, the device further includes a second p-type trough region, the second p-type trough region being directly below the drain region and separating the second n-type well of the plurality of n-type wells from a third n-type well of the plurality of n-type wells. In some embodiments, the first p-type trough region has a top surface higher than a top surface of the second p-type trough region. In some embodiments, the device further includes a second n-type buried layer supporting a bottom side of the first n-type buried layer. The second n-type buried layer has an n-type impurity concentration lower than an n-type impurity concentration of the first n-type buried layer.

[0130] According to some embodiments, a method includes the following steps. An n-type buried layer is formed in a substrate. A p-type epitaxial layer is epitaxially grown over the substrate and the n-type buried layer. A p-type well is formed over the n-type buried layer and has a bottom surface that extends across the opposite sidewall boundaries of the n-type buried layer. A plurality of n-type wells are formed in the p-type epitaxial layer, and a plurality of trench regions are alternately arranged in the p-type epitaxial layer. A gate structure is formed so as to extend across an interface between the p-type well and an n-type well among the plurality of n-type wells. A source region is formed in the p-type well. A drain region is formed over a first trench region among the plurality of trench regions. In some embodiments, the gate structure is formed over a second trench region among the trench regions. In some embodiments, each of the plurality of n-type wells has a bottom surface that is in full contact with the substrate.

[0131] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: An epitaxial layer having a first conductivity type is disposed above a substrate; A plurality of wells of a second conductivity type are provided in the epitaxial layer; A first trench region having the first conductivity type, in the epitaxial layer, the first trench region being located between a first well and a second well among the plurality of wells having the second conductivity type; a well of the first conductivity type, the well forming an interface with a third well of the plurality of wells of the second conductivity type; a gate structure over the interface between the well having the first conductivity type and the third well of the plurality of wells having the second conductivity type; a first source / drain region of the first conductivity type in the well; and A second source / drain region is in the first well and the second well of the plurality of wells having the second conductivity type and is above the first trench region having the first conductivity type.

2. The semiconductor device according to claim 1, wherein The first trench region having the first conductivity type has a bottom surface contacting the substrate.

3. The semiconductor device according to claim 1, wherein Also includes: A second trench region of the first conductivity type is in the epitaxial layer and is located between the second well and the third well of the plurality of wells of the second conductivity type.

4. A semiconductor device, characterized in that: Include: a p-type epitaxial layer on a substrate; A plurality of n-type wells in the p-type epitaxial layer, each of the plurality of n-type wells having a bottom surface completely in contact with the substrate; a p-type well contacting a first n-type well among the plurality of n-type wells; a first n-type buried layer, in the substrate, the p-type well and the first n-type buried layer entirely overlap; a source region in the p-type well; a drain region in a second n-type well among the plurality of n-type wells; and A gate structure is laterally located between the source region and the drain region.

5. The semiconductor device according to claim 4, wherein: The first n-type buried layer has opposite sidewall boundaries which are laterally retracted from opposite sidewall boundaries of the p-type well.

6. The semiconductor device according to claim 4, wherein: The first n-type buried layer does not overlap with any of the plurality of n-type wells.

7. The semiconductor device according to claim 4, wherein: Also includes: A first p-type groove region is directly below the gate structure, and the first p-type groove region separates the first n-type well among the plurality of n-type wells from the second n-type well among the plurality of n-type wells.

8. The semiconductor device according to claim 4, wherein: Also includes: A second n-type buried layer supports a bottom side of the first n-type buried layer.

9. A semiconductor device, characterized in that: Include: An n-type buried layer in a substrate; a p-type epitaxial layer above the substrate and the n-type buried layer; a p-type well above the n-type buried layer, the p-type well having a bottom surface extending beyond opposite sidewall boundaries of the n-type buried layer; A plurality of n-type wells in the p-type epitaxial layer, wherein the plurality of n-type wells are alternately configured in a plurality of trench regions in the p-type epitaxial layer; a gate structure extending across an interface between the p-type well and a first n-type well among the plurality of n-type wells; a source region in the p-type well; and A drain region is above a first trench region among the plurality of trench regions.

10. The semiconductor device according to claim 9, wherein: Each of the plurality of n-type wells has a bottom surface completely contacting the substrate.

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