Semiconductor device

Abstract

A semiconductor device is provided. A first metal gate stack is over the first channel region. A second metal gate stack is over the second channel region. The source / drain feature is between the first channel region and the second channel region. A source / drain contact is over the source / drain feature. The first dielectric cap is over the first metal gate stack. The second dielectric cap is over the second metal gate stack. A contact etch stop layer is over the source / drain contact and over the first and second dielectric caps, wherein a composition of the contact etch stop layer is different from a composition of the first and second dielectric caps. Source / drain vias pass through the interlayer dielectric layer and the contact etch stop layer, where the source / drain vias are in full surface contact with the source / drain contacts, and the source / drain vias and the first dielectric cap are in partial surface contact with the second dielectric cap.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in many generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometry (i.e., the size and / or dimensions of IC features and / or the spacing between these IC features) has decreased. Typically, downscaling is limited only by the ability to lithographically define IC features with ever-decreasing geometry.

[0003] However, as feature sizes continue to decrease, overlap and alignment control become limiting factors when different features are formed on top of each other. For example, when a source / drain via is formed above a source / drain metal contact, any mismatch in the displacement of the overlay will result in incomplete contact between the source / drain via and the source / drain contact. In addition, at the nanometer size of high-density devices, overlay offset may cause unnecessary short circuits between the source / drain via and the metal gate. In order to address the overlay and alignment control issues, it is necessary to improve the contact resistance and avoid coupling or short circuits between the metal gate and the source / drain metal contact. Therefore, although existing methods for forming source / drain vias are generally sufficient for their intended purpose, they are not satisfactory in every aspect. Utility Model Content

[0004] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a workpiece. The workpiece includes a first metal gate stack, a second metal gate stack, a source / drain feature, and a source / drain contact. The first metal gate stack is located above a first channel region. The second metal gate stack is located above the second channel region. The source / drain feature is located between the first channel region and the second channel region. The source / drain contact is located above the source / drain feature. The semiconductor device also includes a first dielectric cap, a second dielectric cap, a contact etch stop layer, an interlayer dielectric layer, and a source / drain via. The first dielectric cap is located above the first metal gate stack. The second dielectric cap is located above the second metal gate stack. The contact etch stop layer is located above the source / drain contact and above the first dielectric cap and the second dielectric cap, wherein the composition of the contact etch stop layer is different from the composition of the first dielectric cap and the second dielectric cap. The interlayer dielectric layer is located above the contact etch stop layer. The source / drain through hole penetrates the interlayer dielectric layer and the contact etch stop layer, wherein the source / drain through hole makes full surface contact with the source / drain contact, and the source / drain through hole and the first dielectric cap make partial surface contact with the second dielectric cap.

[0005] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a workpiece. The workpiece includes a first metal gate stack, a second metal gate stack, a source / drain feature, and a source / drain contact. The first metal gate stack is located above a first channel region. The second metal gate stack is located above the second channel region. The source / drain feature is located between the first channel region and the second channel region. The source / drain contact is located above the source / drain feature. The semiconductor device also includes a first dielectric cap, a second dielectric cap, a contact etch stop layer, an interlayer dielectric layer, a gate via, and a source / drain via. The first dielectric cap covers and directly contacts the first metal gate stack. The second dielectric cap covers and directly contacts the second metal gate stack. The contact etch stop layer is located above the source / drain contact and above the first dielectric cap and the second dielectric cap, wherein the contact etch stop layer and the first dielectric cap and the second dielectric cap are made of different materials. An interlayer dielectric layer is located above the contact etch stop layer. A gate through hole passes through the interlayer dielectric layer, the contact etch stop layer and the first dielectric cap, and the gate through hole contacts the top surface of the first metal gate. A source / drain through hole passes through the interlayer dielectric layer and the contact etch stop layer, and the source / drain through hole trench contacts the top surface of the source / drain contact and the side surface and top surface of the gate through hole.

[0006] Another aspect of the present disclosure relates to a semiconductor device. The device includes a metal gate stack above a channel region of a substrate. A gate spacer is on the sidewall of the metal gate stack. A dielectric cap covers and falls on the metal gate stack and the gate spacer. The device includes a first etch stop layer on the sidewall of the gate spacer and the dielectric cap. A source / drain (S / D) feature is between the channel region of the substrate. The S / D contact is located between the metal gate stack and falls on the S / D feature. The device includes a second etch stop layer above the dielectric cap, the first etch stop layer and the S / D contact. The device includes an interlayer dielectric (ILD) layer above the second etch stop layer. And a first S / D via passes through the ILD layer and the second etch stop layer, and directly contacts the S / D contact and the dielectric cap by extending longitudinally along a first direction. The second etch stop layer and the dielectric cap are made of different materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered limiting in scope, as the present disclosure may be equally applicable to other embodiments.

[0008] Figure 1A A top view of a semiconductor device having source / drain vias is shown according to an embodiment of the present disclosure;

[0009] Figure 1B-Figure 1C According to an embodiment of the present disclosure, Figure 1A A cross-sectional view of the semiconductor device taken along lines BB' and CC';

[0010] Figure 2 A flow chart showing a method of forming a semiconductor device having a source / drain through hole partially or completely according to various aspects of the present disclosure;

[0011] Figure 3-Figure 8 According to an embodiment of the present disclosure, Figure 1A Intercept along line B-B' and according to Figure 2 A cross-sectional view of a semiconductor device processed by the method;

[0012] Fig.9A A top view of a semiconductor device having source / drain via rails is shown according to an embodiment of the present disclosure;

[0013] Fig. 9B According to an embodiment of the present disclosure, Fig.9A A cross-sectional view of the semiconductor device taken along line BB';

[0014] Fig. 10A Another embodiment according to the present disclosure shows a top view of a semiconductor device having source / drain vias and / or via tracks;

[0015] Fig. 10B According to another embodiment of the present disclosure, Fig. 10A A cross-sectional view of the semiconductor device taken along line BB';

[0016] Fig.11 A flowchart showing a method of forming a semiconductor device having a source / drain via and / or a via track partially or completely according to various aspects of the present disclosure;

[0017] Figure 12-Figure 17 According to an embodiment of the present disclosure, Fig. 10A Intercept along line B-B' and according to Fig.11 A cross-sectional view of a semiconductor device processed by the method.

[0018]

Explanation of symbols

[0019] 100,1000:Semiconductor devices

[0020] 101: Isolation Structure

[0021] 102:Substrate

[0022] 106: Active Zone

[0023] 106a: Channel area

[0024] 106b:S / D zone

[0025] 108: Metal gate structure

[0026] 110: S / D contact

[0027] 112: S / D through hole

[0028] 112a: conductive barrier layer

[0029] 114a: Gate through hole

[0030] 114b: Second S / D through hole

[0031] 200,1200:Method

[0032] 202,204,206,208,210,212,1202,1204,1206,1208,1210,1212,1214,1216,1218,1220: Operation

[0033] 302: Gate electrode

[0034] 304: Gate dielectric layer

[0035] 306: Gate stack

[0036] 308: Gate spacer

[0037] 310: Dielectric top cover

[0038] 320: First CESL

[0039] 350: first ILD layer

[0040] 420: Second CESL

[0041] 550: Second ILD layer

[0042] 709: S / D through hole groove

[0043] 909: First S / D through hole trench

[0044] d1: length

[0045] d2,d3: width

[0046] B-B',C-C': line

[0047] x,y,z: direction DETAILED DESCRIPTION

[0048] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0049] In addition, for ease of description, the present disclosure may use spatially relative terms, such as "below", "under", "lower", "above", "upper", etc. to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientations shown in the accompanying drawings. For example, if the device in the figure is turned over, the elements described as "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the exemplary term "below" can cover both above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can also be interpreted accordingly.

[0050] Further, when the terms "about" and "approximately" are used to describe a number or a range of numbers, the terms are generally intended to encompass numbers within a reasonable range, including the described number, such as within + / -10% of the described number, or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" can encompass a size range from 4.5 nm to 5.5 nm.

[0051] The present disclosure relates to methods and devices for source / drain (S / D) vias, including slot vias, via rails, and other vias that fall on S / D metal contacts. As device features are scaled down, the spacing between the metal gate and adjacent S / D features becomes tighter. Therefore, any misalignment when forming the S / D vias above the S / D metal contacts may result in increased contact resistance due to partial landing rather than full contact landing. In addition, misalignment may cause leakage current problems due to the possibility of short circuits between the gate and the S / D features. For example, when forming the S / D via trench, the metal gate may be exposed due to etching with overlay errors. And when filling the source / drain vias, there may be unwanted coupling between the metal gate and the source / drain vias. In order to prevent leakage current and the possibility of short circuits between the gate and the source / drain connection, the present disclosure provides solutions for full contact landing and for proper insulation between the S / D features and the metal gate. For example, the elongated S / D via is a slit via having a portion directly above the metal gate, and a contact etch stop layer is used to prevent undesired etching above the metal gate when the S / D via is formed. For another example, the S / D via is formed as an S / D via track that extends over multiple metal gates and contacts multiple S / D contacts. For another example, in a process associated with a static random access memory (SRAM) device, a process for forming a shared butt contact between a metal gate and a source / drain contact is eliminated. Alternatively, the S / D via is formed to fall directly on the gate via, thereby reducing manufacturing costs.

[0052] To illustrate various aspects of the present disclosure, a method of forming a semiconductor device is discussed below. The embodiments shown in the present disclosure can be implemented by gate-all-around (GAA) field effect transistors (FETs), but the present disclosure is not limited to this. For example, fin FETs or other types of transistors can also be used to implement the present disclosure. Those of ordinary skill in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein.

[0053] Figure 1AA top view of a semiconductor device 100 with source / drain vias 112 is shown according to an embodiment of the present disclosure. The semiconductor device 100 may be a portion of an integrated circuit (IC) chip, a system on chip (SoC), or a portion thereof, which may include various passive or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device includes a nonvolatile memory, such as non-volatile random access memory (NVRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), other suitable memory types, or combinations thereof.

[0054] Still reference Figure 1A , the semiconductor device 100 includes an active region 106 extending longitudinally along the x-direction and a metal gate structure 108 extending longitudinally along the y-direction. The metal gate structure 108 is disposed in a channel region 106a (refer to Figure 1B ) above. A source / drain (S / D) region 106b (refer to Figure 1B). The S / D region 106b is disposed between adjacent metal gate structures 108. An S / D contact 110 (also referred to as an S / D metal contact) is disposed above the S / D region 106b. The S / D contact 110 lands on the S / D feature of the S / D region 106b. The S / D contact 110 may be parallel to the metal gate structure 108 and extend longitudinally along the y direction. In some embodiments, the S / D contact 110 may only land on the S / D region of a single active region 106. An S / D through hole 112 is disposed above the S / D contact 110 and lands on the S / D contact 110. The S / D through hole 112 is parallel to the active region 106 and extends longitudinally along the x direction. The S / D via 112 is also referred to as a slot via, and the S / D via 112 makes full-surface contact with the top of the S / D contact 110, and the S / D via 112 may extend to directly above a portion of the metal gate structure 108 on each side of the S / D contact 110. Figure 1A Only one S / D via 112 is shown, but the present disclosure is not limited thereto. For example, the semiconductor device 100 may include additional S / D vias 112 connected to additional S / D contacts 110 .

[0055] Figure 1B Show Figure 1A FIG. 1 is a cross-sectional view of the semiconductor device 100 taken along line BB' in FIG. Figure 1B When referring to Figure 3-Figure 8 describe Figure 2 Additional details will be provided when the method is developed. Figure 1BAs shown, the active region 106 is disposed above the substrate 102. The active region 106 includes a channel region 106a and a source / drain region 106b. The metal gate structure 108 is directly disposed above the channel region 106a. The channel region 106a of the GAA FET may include a stacked transistor channel. The channel region 106a for the fin FET may include a single fin-shaped transistor channel. The source / drain region 106b may include a source / drain epitaxial component doped with an n-type or p-type dopant. Each metal gate structure 108 includes a gate stack 306, a gate spacer 308 on the sidewall of the gate stack 306, and a gate dielectric cap 310 above the gate stack 306 and above the gate spacer 308. The gate dielectric cap 310 directly falls on and covers the top surface of the gate stack 306 and the gate spacer 308. Each gate stack 306 includes a gate dielectric layer 304 and a gate electrode 302. The gate electrode 302 may include a top portion above the bottom portion. The top of the gate electrode 302 may be wider in the x-direction and cover the top surface of the gate dielectric layer 304. The height of the gate spacer 308 in the z-direction may be higher than the gate stack 306. As such, the gate dielectric cap 310 may be T-shaped, with a bottom portion located between opposite side surfaces of the gate spacer 308 and a top portion located above the top surface of the gate spacer 308.

[0056] Still reference Figure 1B , source / drain (S / D) contacts 110 may be formed over and on the S / D regions 106 b. The S / D contacts 110 are disposed between the metal gate structures 108. The S / D contacts 110 may be lined along the sidewalls of the first contact etch stop layers (CESL) 320. The first CESL 320 is also on the sidewalls of the metal gate structure 108, and the first CESL 320 isolates the metal gate structure 108 from the S / D contacts 110. In some embodiments, if the S / D contacts 110 are not formed over the corresponding S / D regions 106 b, a first interlayer dielectric (ILD) layer 350 is disposed over these S / D regions 106 b. These S / D regions 106 b are also aligned with the first CESL 320, wherein the first CESL 320 surrounds the side surfaces and bottom surfaces of the first ILD layer 350.

[0057] Still refer to reference Figure 1B, the second CESL 420 is disposed over the gate structure 108, the first CESL 320, and the first ILD layer 350. The second CESL 420 has a different material composition than the first CESL 320. The second CESL 420 also has a different material composition than the gate dielectric cap 310. The second ILD layer 550 is disposed over the second CESL 420. The first ILD layer 350 and the second ILD layer 550 may have the same material composition. The S / D via 112 may be formed to pass through the second ILD layer 550 and the second CESL 420 and land on the S / D contact 110. The S / D via 112 is in full direct contact with the top surface of the S / D contact 110 and partially in contact with the top surface of the gate dielectric cap 310. The S / D via 112 has a length d1 in the x-direction and the S / D contact 110 has a width d2 in the x-direction. The length d1 is greater than the width d2, and the ratio of d1 to d2 is greater than 2. The ratio of d1 to d2 is greater than 2 to ensure full contact between the top surface of S / D contact 110 and the bottom surface of S / D via 112 and that the bottom surface of S / D via 112 falls on the top surface of S / D contact 110. For example, the ratio of d1 to d2 is about 3.

[0058] Figure 1C According to an embodiment of the present disclosure, Figure 1A 1 is a cross-sectional view of a semiconductor device 100 taken along line CC' in FIG. In this figure, an isolation structure 101 is disposed above a substrate 102. The isolation structure 101, such as a shallow trench isolation (STI), is inserted and isolates adjacent S / D regions 106b along the y direction. A first CESL 320 may fall on the isolation structure 101 and conformally fall on a portion of the S / D region 106b. A first ILD layer 350 is disposed above the first CESL 320, which itself is disposed above the S / D region 106b and the isolation structure 101. The S / D contact 110 passes through the first ILD layer 350 and the first CESL 320 to fall on the S / D features of multiple S / D regions 106b. The second CESL 420 falls on the S / D contact 110 and on the top surface of the first ILD layer 350. The second ILD layer 550 is located on the second CESL 420. The S / D via 112 passes through the second ILD layer 550 and the second CESL 420 to land on the S / D contact 110. In this figure, the S / D via 112 has a width d3 in the y direction, and the width of the S / D via 112 is shorter than the length of the S / D contact 110 in the y direction. In one embodiment, d3 has a similar size to d2. Therefore, the ratio of the length d1 to the width d3 should also be greater than 2. For example, the ratio of d1 to d3 is about 3.

[0059] Figure 2A flow chart of a method 200 for forming a semiconductor device 100 having a source / drain via 112 in part or in whole according to various aspects of the present disclosure is shown. The method 200 is briefly described below. At operation 202, the method 200 receives or provides a workpiece, the workpiece including a metal gate stack above a channel region of an active region. The workpiece also includes source / drain (S / D) features between the channel regions and an S / D contact above one of the S / D features. The active region includes the channel region and the S / D region, and the source / drain region includes the S / D feature. At operation 204, the method 200 forms a dielectric cap (or gate dielectric cap) above the metal gate stack. At operation 206, the method 200 forms a contact etch stop layer (CESL) above the S / D contact and above the dielectric cap, wherein the material composition of the CESL and the dielectric cap is different. At operation 208, the method 200 forms an interlayer dielectric (ILD) layer above the CESL. At operation 210, method 200 performs a patterning process to form an S / D via trench through the ILD layer and through the CESL. The S / D via trench exposes the top surface of the S / D contact. At operation 212, method 200 forms an S / D via in the S / D via trench. The S / D via makes full surface contact with the S / D contact and makes partial surface contact with two or more dielectric caps. The present disclosure contemplates additional processing. Additional operations may be provided before, during, and after method 200, and some of the described operations may be moved, replaced, or removed for additional embodiments of method 200.

[0060] Figure 3-Figure 8 According to an embodiment of the present disclosure, Figure 1A Intercept along line B-B' and according to Figure 2 2 is a cross-sectional view of a semiconductor device 100 processed by method 200 of the present invention. For the sake of clarity, these figures have been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the device 100, and some of the features described below may be replaced, modified, or removed in other embodiments of the device 100.

[0061] At operation 202, the method 200 receives a workpiece 300 of a semiconductor device 100, an embodiment of which is Figure 3. The workpiece 300 may include a substrate 102 and an active region 106 above the substrate. The substrate 102 may be a silicon (Si) substrate, or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The active region 106 may be an extension of the substrate 102 protruding from the substrate 102. As described above, the active region 106 includes a channel region 106a below the metal gate structure 108 and an S / D region 106b between the channel region 106a. At this stage of manufacturing, the metal gate structure 108 includes a metal gate stack 306 and a gate spacer 308 along the sidewalls of the metal gate stack 306.

[0062] The gate spacer 308 may be made of silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. Figure 3 A single layer of gate spacers 308 along the sidewalls of the metal gate stack 306 is shown, but the disclosure is not limited thereto. For example, the gate spacers 308 may have multiple layers, and each layer may have a different material for specific design considerations such as etch protection and isolation.

[0063] Each metal gate stack 306 includes a gate dielectric layer 304 and a gate electrode 302 disposed on the gate dielectric layer 304. In some embodiments, the gate dielectric layer 304 includes an interface layer and a high-k dielectric layer disposed on the interface layer. As shown, the gate dielectric layer 304 surrounds the gate electrode 302.

[0064] The gate electrode 302 may be formed by any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma CVD (HDPCVD), metallorganic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), spin coating, electroplating, other deposition processes or combinations thereof. The gate electrode 302 may include one or more conductive materials, such as a work function metal layer, a metal fill layer and / or other suitable conductive material layer. The work function layer (if present) may be the same or different and may be an n-type work function layer or a p-type work function layer. The gate dielectric layer 304 includes a high-k dielectric material, such as a material having a dielectric constant greater than that of silicon oxide (k≈3.9). Each gate electrode 302 includes a suitable conductive material, such as aluminum (Al), tungsten (W), cobalt (Co) and / or copper (Cu). Each gate electrode 302 may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In the Fin FET structure, the metal gate stack 306 covers the top and side surfaces of the fin-shaped channel in the channel region 106a. In the GAA FET structure, the metal gate stack 306 completely surrounds the vertically stacked transistor channel (not shown) in the channel region 106a. In other cases, the metal gate stack 306 includes a portion disposed directly above the channel region 106a.

[0065] S / D region 106b includes S / D features epitaxially grown from substrate 102 and / or channel region 106a. The S / D features may include n-type S / D features corresponding to n-type transistor regions or p-type S / D features corresponding to p-type transistor regions. The S / D features may be formed by an epitaxial process using a CVD deposition technique (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof). The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the substrate 102 and / or the channel region 106a. In some embodiments, for n-type transistors, the epitaxial S / D features include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial S / D features). In some embodiments, for p-type transistors, the epitaxial source / drain features include silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain features).

[0066] The S / D contact 110 is disposed above the S / D feature in the S / D region 106b and falls directly on the S / D feature. The S / D contact 110 may include a silicide feature and a metal filling layer above the silicide feature. The silicide feature is disposed between the S / D feature and the metal filling layer. The silicide feature may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi) or other suitable compounds. The metal filling layer above the silicide component may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta) or molybdenum (Mo).

[0067] Lining the sidewalls of the S / D contact 110 is a first contact etch stop layer (CESL) 320. The first CESL 320 includes a dielectric material such as silicon nitride and may include one or more layers. The first CESL 320 is disposed between the S / D contact 110 and the gate spacer 308 along the x-direction. The first CESL 320 also lines the surface of the first interlayer dielectric (ILD) layer 350 between the metal gate structures 108. The first ILD layer 350 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, oxide formed by TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, Black Oxide, and the like. (Applied Materials, Santa Clara, CA), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, MI), polyimide, other low-k dielectric materials, or combinations thereof. For the purpose of etching selectivity, the first ILD layer 350 includes a different material from the first CESL 320. For example, the first ILD layer 350 is made of silicon oxide and the first CESL 320 is made of silicon nitride. The first ILD layer 350 can be disposed on the S / D region 106b where the S / D contact 110 is not formed. In some embodiments (not shown), even after the S / D contact 110 is formed, a portion of the first ILD layer 350 remains, wherein a portion of the first ILD layer 350 is disposed between the S / D contact 110 and the first CESL 320.

[0068] At operation 204 , the method 200 forms a dielectric cap 310 (or gate dielectric cap) over the metal gate stack 306 . Figure 4-5 Example process steps for forming the dielectric cap 310 are shown. Figure 4, a dielectric cap trench 309 is formed by etching the top of the gate stack 306 and the top of the gate spacer 308. The etching process can be a dry etching process, a wet etching process, other suitable etching processes or a combination thereof. In some embodiments, the etching process is a multi-step etching process to etch the gate stack 306 and the gate spacer 308 separately. In some embodiments, a lithography process is performed to form a patterned mask layer covering the first ILD layer 350 and the S / D contact 110, and then the etching process uses this patterned mask layer as an etching mask when forming the dielectric cap trench 309. In any case, the gate stack 306 and the gate spacer 308 are etched so that the top surface of the gate stack 306 and the gate spacer 308 is lower than the top surface of the first CESL 320, the first ILD layer 350 and the S / D contact 110. In an embodiment, the gate stack 306 is further etched below the top surface of the gate spacer 308 to provide further isolation of the gate stack 306 from other metal features in subsequent process steps.

[0069] Reference now Figure 5 , a dielectric cap 310 is formed in the dielectric cap trench 309. In an embodiment, before the dielectric cap 310 is formed, a conductive metal layer 301 such as a tungsten metal layer is deposited over the metal gate stack 306 and becomes a part of the metal gate stack 306. Specifically, the conductive metal layer 301 becomes the top of the gate electrode 302. The top of the gate electrode 302 (i.e., the conductive metal layer 301) falls on the top surface of the gate dielectric layer 304 and the side surface of the opposite gate spacer 308. In this case, the top of the gate electrode 302 is wider than the bottom of the gate electrode 302 along the x-direction, forming a T-shaped gate electrode 302. In an embodiment, the top surface of the T-shaped gate electrode 302 is still lower than the top surface of the gate spacer 308.

[0070] Still reference Figure 5, the dielectric cap 310 can be formed by a deposition process followed by a planarization process such as CMP. The deposition process may include processes such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes or combinations thereof. Each dielectric cap 310 can be T-shaped, having a top and a bottom, wherein the top is wider than the bottom along the x-direction. The top of the dielectric cap 310 partially contacts the top surface of the gate spacer 308, and the bottom of the dielectric cap 310 partially contacts the top surface of the gate stack 306. In an embodiment, the dielectric cap 310 and the first CESL 320 have the same material composition. In an embodiment, the dielectric cap 310 is made of silicon nitride. The dielectric cap 310 can be referred to as a part of the metal gate structure 108, which also includes the metal gate stack 306 and the gate spacer 308.

[0071] Reference now Figure 6 At operation 206, the method 200 forms a contact etch stop layer (CESL) 420 over the S / D contacts 110 and over the dielectric cap 310, wherein the dielectric cap 310 and the CESL 420 have different material compositions. The CESL 420 (referred to herein as the second CESL 420) is different in material composition from the first CESL 320 and the first ILD layer 350. The second CESL 420 is directly disposed on the top surface of the first ILD layer 350, the first CESL 320, the dielectric cap 310, and the S / D contacts 110. The material composition of the CESL 420 is selected to have an etch selectivity greater than 10 when compared to other dielectric layers disposed thereon (e.g., the dielectric cap 310, the first CESL 320, and the first ILD layer 350). In an embodiment, the second CESL 420 includes carbon, and the dielectric cap 310 and the first CESL 320 do not contain carbon. In an embodiment, the second CESL 420 includes oxygen, and the dielectric cap 310 and the first CESL 320 do not contain oxygen. In an embodiment, the second CESL 420 is made of silicon carbonate (SiCO) or silicon carbonitride (SiCN), and the dielectric cap 310 and the first CESL 320 are made of silicon nitride (SiN).

[0072] Still refer to Figure 6 At operation 208 , the method 200 forms an interlayer dielectric (ILD) layer 550 , referred to herein as a second ILD layer 550 , over the second CESL 420 .

[0073] The ILD layer 550 may be formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof. The second ILD layer 550 may have a material composition similar to or the same as the first ILD layer 350. For the purpose of etching selectivity, the material composition of the second ILD layer 550 is also different from the second CESL 420.

[0074] At operation 210, method 200 performs a patterning process to form S / D via trenches 709 through the second ILD layer 550 and through the CESL 420, an embodiment of which is Figure 7 . The patterning process may include one or more lithography and etching processes. In some embodiments, a lithography process is performed to form a patterned mask layer, and when the S / D via trench 709 is formed, the etching process uses the patterned mask layer as an etching mask. Due to the difference in etching selectivity, the etching process may include multiple etching processes to etch the second ILD layer 550 and the second CESL 420 respectively. For example, the patterning process may first perform an ILD etching process using an etchant to etch the ILD layer to expose the top surface of the CESL. Then, the patterning process performs a selective etching process, which uses a different etchant to selectively etch the second CESL 420 without substantially etching the dielectric cap 310 and the first CESL 320. If the dielectric cap 310 and / or the first CESL 320 are etched during the etching process, there is a risk of etching to the gate electrode 302 that is too close to the gate stack 306, resulting in undesirable coupling between the subsequently formed S / D via and the metal gate stack 306. Since the second CESL 420 has a different dielectric material (e.g., SiCO) than the dielectric cap 310 and the first CESL 320, over-etching problems that expose the metal gate stack 306 are prevented. In an embodiment, when etching the second CESL 420, the selective etching process uses an etchant having an etching selectivity greater than 10 compared to etching the dielectric cap 310 and the first CESL 320. In an embodiment, the second CESL 420 also has a different material composition than the gate spacer 308. As such, the selective etching process also does not etch the gate spacer 308 due to the difference in etching selectivity.

[0075] The S / D via trench 709 completely exposes the top surface of the S / D contact 110 and partially exposes the top surface of the gate dielectric cap 310 adjacent to the S / D contact 110. The S / D via trench 709 also exposes the top surface of the first CESL 320 on the liner sidewall of the S / D contact 110. The S / D via trench 709 has a dimension d1 in the x-direction, and the S / D contact 110 has a dimension d2 in the x-direction, where d1 is greater than d2. Because the dielectric cap 310 acts as an etch stop layer to prevent over-etching into the gate stack 306, the S / D via trench 709 can be formed to have a larger dimension d1. The larger dimension d1 also ensures full surface contact between the subsequently formed S / D via 112 and the S / D contact 110. To ensure full surface contact, the ratio of d1 to d2 should be greater than 2, for example, about 3.

[0076] At operation 212, method 200 forms S / D vias 112 in S / D via trenches 709, an embodiment of which is Figure 8 The S / D through hole 112 makes full surface contact with the top surface of the S / D contact 110, and the S / D through hole 112 makes partial surface contact with two or more dielectric caps 310. Figure 8 In the illustrated embodiment, the S / D via 112 makes partial surface contact with the dielectric cap 310 adjacent to the S / D contact 110. The S / D via 112 also makes direct contact with the top surface of the first CESL 320. The S / D via 112 may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), molybdenum (Mo), or a combination thereof. In an embodiment, the S / D via 112 may include a conductive barrier layer 112a ( Figure 8 Not shown, but Fig.17 ) and a metal filling layer over the conductive barrier layer 112a. The conductive barrier layer acts as a glue layer and may include titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The metal filling layer may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), molybdenum (Mo), or a combination thereof. The S / D via 112 may be formed by first depositing a conductive barrier layer 112a in the S / D via trench 709 and then performing CVD isotropic metal growth on the conductive barrier layer 112a to form a metal filling layer. In an embodiment, the deposited metal filling layer is tungsten.

[0077] The method 200 may perform further steps to complete the fabrication of the semiconductor device 100. Additional operations may be provided before, during, and after the method 200, such as forming another S / D via 112 over another S / D contact 110. Furthermore, some of the operations described may be moved, replaced, or removed for additional embodiments of the method 200. For example, Fig.9A and Fig. 9B A top view and a cross-sectional view of a semiconductor device 100 are shown according to another embodiment of the present disclosure. Fig.9A and Fig. 9B and Figure 1A and Figure 1B Similar, and for the sake of brevity, similar features will not be described again. As shown in the figure, Fig. 9B Shows Fig.9A A cross-sectional view taken along line BB'. The difference here is that the S / D via 112 extends longer in the x-direction, thereby making full-surface contact with multiple S / D contacts 110. In this case, the S / D via 112 can be referred to as an S / D via rail and the S / D via rail makes full-surface contact with at least one dielectric cap 310. Additional features can be formed above the S / D via or via rail 112. Additional features can include metal interconnects with metal lines that are in direct contact with the top surface of the S / D via or via rail 112.

[0078] In some devices (e.g., SRAM), a metal interconnect, often referred to as a shared butt contact, is used to establish an electrical connection between a gate and an adjacent S / D contact. In the embodiments of the present disclosure, it is not necessary to form a dedicated shared butt contact, which facilitates forming an extended S / D via 112 that directly contacts the gate, such as Fig. 10A and Fig. 10B as shown in . Fig. 10A and Fig. 10B A top view and a cross-sectional view of a semiconductor device 1000 having source / drain vias 112 (and / or via rails 112 ) are shown. Figure 10A-10B and Figure 1A-1B and Figure 9A-9B Similar, and for the sake of brevity, similar features will not be described again. As shown in the figure, Fig. 10B Shows Fig. 10A A cross-sectional view taken along line BB'.

[0079] refer to Fig. 10A , semiconductor device 1000 shows two S / D vias 112. S / D vias 112 have a thickened perimeter to indicate the inclusion of a conductive barrier layer 112a, which will be referred to below. Fig.15 As mentioned above, the conductive barrier layer 112a may also be present in the previously described embodiments. Fig. 10AAlso shown is an additional via 114 directly above two metal gate structures 108 and one S / D contact 110. The additional via 114 does not have a conductive barrier layer 112a. The additional via 114 includes two gate vias 114a and an S / D via 114b. The S / D via 114b is different from the S / D via 112 and may be referred to herein as a second S / D via 114b above the second S / D contact 110.

[0080] One of the S / D through holes 112 (in Fig. 10A The bottom of Fig.9A Another S / D via 112 is a via that connects the metal gate stack 306 of the metal gate structure 108 to the S / D contact 110 through the gate via 114a. This S / D via 112 is an S / D-to-gate via and may be referred to herein as a first S / D via 112. Fig. 10B According to the embodiment of the present disclosure, Fig. 10A FIG. 1 is a cross-sectional view of the semiconductor device 1000 taken along line BB′ passing through the first S / D via 112 . Fig. 10B and Figure 1B Similar, and for the sake of brevity, similar features will not be described again.

[0081] like Fig. 10BAs shown, the gate via 114a passes through the second ILD layer 550, the second CESL 420 and the dielectric cap 310. The gate via 114a falls on the corresponding top surface of the gate stack 306 (specifically, the gate electrode 302). The first S / D via 112 falls directly on the first gate via 114a and the adjacent first S / D contact 110. The first S / D via 112 includes a conductive barrier layer 112a aligned with the sidewall and top surface of the first gate via 114a. The first S / D via 112 electrically connects the first S / D contact 110 to the gate stack 306 directly contacting the first gate via 114a. The first S / D via 112 makes full surface contact with the top surface of the first S / D contact 110. The second S / D via 114b falls on the second S / D contact 110, but does not fall on any gate via 114a, nor is it electrically connected to any gate stack 306. The second gate via 114a is isolated from the second S / D via 114b by the second CESL 420 and the second ILD layer 550. In an embodiment, the top surface of the second gate via 114a is above the top surface of the first gate via 114a. In an embodiment, the top surface of the second gate via 114a is substantially coplanar with the top surface of the first S / D via 112 and the top surface of the second S / D via 114b. The first gate via 114a on the right, the second gate via 114a on the left, and the second S / D via 114b each have a smaller width in the x-direction than the first S / D via 112. In an embodiment, because the first S / D via 112 is formed differently, the first, second gate vias 114a and the second S / D via 114b have smaller widths and do not include the conductive barrier layer 112a.

[0082] Fig.11A flow chart of a method 1200 for forming a semiconductor device 1000 having a source / drain via 112 (and / or a via track 112) in part or in whole according to various aspects of the present disclosure is shown. The method 1200 is briefly described below. At operation 1202, the method 1200 receives or provides a workpiece, the workpiece including a metal gate stack above a channel region of an active region. The workpiece also includes source / drain (S / D) features between the channel regions and S / D contacts above the S / D features. The active region includes a channel region and an S / D region, and the source / drain region includes an S / D feature. At operation 1204, the method 1200 forms a dielectric cap (or gate dielectric cap) above the metal gate stack. At operation 1206, the method 1200 forms a contact etch stop layer (CESL) above the S / D contacts and above the dielectric cap, wherein the CESL is different in composition from the dielectric cap. At operation 1208, the method 1200 forms an interlayer dielectric (ILD) layer over the CESL. At operation 1210, the method 1200 performs a first patterning process to form a gate via trench that exposes the top surface of the metal gate stack. At operation 1212, the method 1200 forms a gate via in the gate via trench. At operation 1214, the method 1200 performs a second patterning process to form a first S / D via trench through the ILD layer and through the CESL. The first S / D via trench exposes the top surface and side surfaces of the first plurality of gate vias. The first S / D via trench also exposes the top surface of the first plurality of S / D contacts. At operation 1216, the method 1200 forms a first S / D via in the first S / D via trench. Each first S / D via makes full surface contact with one of the first plurality of S / D contacts and makes partial surface contact with two or more dielectric caps. At operation 1218, the method 1200 performs a third patterning process to form a second S / D via trench through the ILD layer and through the CESL. The second S / D via trench exposes a top surface of a second plurality of S / D contacts. At operation 1220, the method 1200 forms a second S / D via in the second S / D via trench. The present disclosure contemplates additional processing. Additional operations may be provided before, during, and after the method 1200, and some of the described operations may be moved, replaced, or removed for additional embodiments of the method 1200.

[0083] Figure 12-Figure 17 According to the embodiment of the present disclosure, Fig. 10A Intercept along line B-B' and according to Fig.11 12 is a cross-sectional view of a semiconductor device 10000 processed by method 1200. Operations 1202 to 1208 in method 1200 are substantially similar to operations 202 to 208 in method 200. Since these operations have been previously described, reference will be made to Fig.12Method 1200 is described beginning at the end of operation 1218 .

[0084] At the end of operation 1208, reference Fig.12 , the semiconductor device 1000 shows an interlayer dielectric (ILD) layer 550 formed over the second CESL 420, very similar to Figure 6 The semiconductor device 100 is shown in FIG. 1 , except that, at this stage of manufacturing, the semiconductor device 1000 further includes a second S / D contact 110 on the second S / D region 106 b , while the semiconductor device 100 shows a first ILD layer 350 on the second S / D region 106 b .

[0085] At operation 1210, the method 1200 performs a first patterning process to form a gate via trench (not shown) above the gate structure 108 that exposes the top surface of the metal gate stack. The first patterning process may include one or more lithography and etching processes. In some embodiments, a lithography process is performed to form a patterned mask layer, and when the gate via trench is formed, the etching process uses the patterned mask layer as an etching mask. Due to the difference in etching selectivity, the etching process may include multiple etching processes to etch the second ILD layer 550, the second CESL 420, and the dielectric cap 310, respectively. For example, as described above, the second CESL 420 and the dielectric cap 310 may have different materials so that the etching selectivity is greater than 10. In this way, when the gate via trench is formed to expose the gate electrode 302 of the gate stack 306, a separate etching process may be performed to etch these layers separately.

[0086] At operation 1212, method 1200 forms a gate via 114a in the gate via trench, an embodiment of which is Fig.13 . Since the gate via 114a is small and has a high aspect ratio, the gate via 114 can be formed by selective metal deposition with anisotropic metal growth, and there is no conductive barrier layer. This type of metal deposition can also be referred to as bottom-up selective growth, in which the deposited metal grows substantially in the z direction without much growth in the x or y direction. Bottom-up selective growth can be achieved without first depositing a conductive barrier layer (or glue layer) in the gate via trench. The gate via 114a is formed in this way so that the gate via 114a does not have a conductive barrier layer such as titanium nitride surrounding the deposited metal. In an embodiment, the deposited metal forming the gate via 114a is tungsten (W). In other embodiments, other suitable metal filling materials such as aluminum (Al), titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tantalum (Ta), or molybdenum (Mo) can be used.

[0087] At operation 1214, the method 1200 performs a second patterning process to form a first S / D via trench 909, such as a first S / D via trench 909, an embodiment of which is Fig.14 . The first S / D via trench 909 passes through the ILD layer 550 and through the second CESL 420. The first S / D via trench 909 exposes the top surface and side surfaces of the first plurality of gate vias 114a. These gate vias 114a may have an etch-back, such as Fig.15 The first gate through hole 114a on the right side is etched back so that the top surface of the first gate through hole 114a is lower than that of other gate through holes 114a (eg Fig.15 The top surface of the second gate through hole 114a on the left side.

[0088] The second patterning process of operation 1214 may include one or more lithography and etching processes that are very similar to the first patterning process, except that each first S / D via trench 909 is formed to be wider in the x-direction. Wherein the first S / D via trench 909 completely exposes the top surface of the first plurality of S / D contacts 110. The first S / D via trench 909 can also expose the top surface of the dielectric cap 310, which acts as an effective etch stop layer due to the etching selectivity between the second CESL 420 and the dielectric cap 310 as described with respect to operation 210 of method 200. In an embodiment, before performing the second patterning process (not shown), an oxide recap is performed over the gate via 114a and the ILD layer 550.

[0089] At operation 1216 , the method 1200 forms a first S / D via 112 in the first S / D via trench 909 . Figure 15-16 1 shows an example process step for forming the first S / D via 112. Since the first S / D via 112 is formed larger and wider and has a lower aspect ratio, the first S / D via 112 can be formed by metal deposition with isotropic metal growth and has a conductive barrier layer 112a. Now referring to Fig.15 , isotropic metal growth is achieved by first conformally depositing a conductive barrier layer 112a in the first S / D via trench 909. The conductive barrier layer 112a acts as a glue layer and may include titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The conductive barrier layer 112a is disposed on the exposed top and side surfaces of the first plurality of gate vias 114a, e.g. Fig.16 The conductive barrier layer 112a also falls on the top surface of the first S / D contact 110 adjacent to the first gate through hole 114a. Fig.16, a metal filling layer is deposited on the conductive barrier layer 112a to form the first S / D via 112. The metal filling layer may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), molybdenum (Mo) or a combination thereof. The metal filling layer may be deposited by performing CVD isotropic metal growth on the conductive barrier layer 112a. In an embodiment, the deposited metal filling layer is tungsten. Each first S / D via 112 makes full surface contact with one of the first plurality of S / D contacts 110. The first S / D via 112 may also make partial surface contact with two or more dielectric caps 310. After forming the first S / D via 112, a CMP process and / or other planarization process may be performed to etch the top portion of the conductive barrier layer 112a and expose the gate via 114a and the first S / D via 112.

[0090] At operation 1218, the method 1200 performs a third patterning process to form a second S / D via trench (not shown) through the ILD layer 550 and through the CESL 420. The third patterning process may include one or more lithography and etching processes. In some embodiments, the lithography process is performed to form a patterned mask layer, and when forming the second S / D via trench, the etching process uses the patterned mask layer as an etching mask. The second S / D via trench is formed to be narrower than the first S / D via trench 909 in the x-direction. The second S / D via trench exposes the top surface of the second plurality of S / D contacts 110. In an embodiment, the second S / D via trench does not expose the top surface of the dielectric cap 310. In another embodiment, the second S / D via trench only partially exposes the top surface of the second plurality of S / D contacts 110.

[0091] At operation 1220, the method 1200 forms a second S / D via 114b in the second S / D via trench, an embodiment of which is Fig.17. Similar to the gate via 114a, because the second S / D via 114b is smaller and has a high aspect ratio, the second S / D via 114b can be formed by selective metal deposition with anisotropic metal growth, and there is no conductive barrier layer. As described, this type of metal deposition can also be referred to as bottom-up selective growth, in which the deposited metal grows substantially in the z direction without much growth in the x or y direction. Bottom-up selective growth can be achieved without first depositing a conductive barrier layer (or glue layer) in the gate via trench. The second S / D via 114b is formed in this way so that there is no conductive barrier layer such as titanium nitride surrounding the deposited metal in the second S / D via 114b. In an embodiment, the deposited metal forming the second S / D via 114b is tungsten (W). In other embodiments, other suitable metal filling materials such as aluminum (Al), titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tantalum (Ta) or molybdenum (Mo) can be used. It should be noted that the first S / D via 112 and the second S / D via 114b are formed in different process steps and by different metal growth schemes. Thus, the first S / D via 112 completely contacts the top surface of the S / D contact 110, while the second S / D via 114b may only partially contact the top surface of the S / D contact 110.

[0092] Although not limiting, the present disclosure provides advantages for semiconductor devices having source / drain (S / D) vias. One example advantage is that the S / D vias are formed to completely contact the top surface of the S / D contacts. Another example advantage is that the S / D vias are elongated into slot-shaped vias or via tracks and can be formed directly above a metal gate structure and contact multiple gate vias. Another example advantage is that different types of contact etch stop layers are used to prevent undesirable etching on the metal gate when forming the S / D vias. Another example advantage is that in a process associated with a static random access memory (SRAM) device, by forming the S / D vias directly on the gate vias, the process of forming a shared butt contact between the metal gate and the source / drain contacts is eliminated.

[0093] One aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes receiving a workpiece having a first metal gate stack above a first channel region, a second metal gate stack above a second channel region, a source / drain (S / D) feature between the first channel region and the second channel region, and an S / D contact above the S / D feature. The method includes forming a first dielectric cap and a second dielectric cap above the first metal gate stack and the second metal gate stack, respectively. The method includes forming a contact etch stop layer (CESL) above the S / D contact and above the first dielectric cap and the second dielectric cap, wherein the composition of the CESL is different from the composition of the first dielectric cap and the second dielectric cap. The method includes forming an interlayer dielectric (ILD) layer above the CESL. The method includes performing a patterning process to form an S / D via trench through the ILD layer and through the CESL, wherein the patterning process includes a selective etching process using an etchant to selectively etch the CESL without etching the first dielectric cap and the second dielectric cap, and the S / D via trench fully exposes a top surface of the S / D contact and partially exposes a top surface of the first dielectric cap and a top surface of the second dielectric cap. The method includes forming an S / D via in the S / D via trench, wherein the S / D via makes full-surface contact with the S / D contact, and the S / D via and the first dielectric cap make partial surface contact with the second dielectric cap.

[0094] In one embodiment, the S / D via has a length extending in a first direction from the first metal gate stack to the second metal gate stack, has a width extending in a second direction perpendicular to the first direction, and the length is greater than the width. In another embodiment, the ratio of the length to the width of the S / D via is greater than 2. In another embodiment, the S / D via extends in the first direction above the first metal gate stack to make full-surface contact with a second S / D contact above a second S / D feature, and the second S / D feature is located between the first channel region and the third channel region.

[0095] In one embodiment, the patterning process further includes an ILD etching process, wherein the ILD etching process is performed before the selective etching process, and the etchant used in the ILD etching process can etch the ILD layer to expose the top surface of the CESL. In one embodiment, the CESL includes carbon, and the first dielectric cap and the second dielectric cap do not include carbon. In another embodiment, the CESL is made of silicon carbonate (SiCO) or silicon carbonitride (SiCN), and the first dielectric cap and the second dielectric cap are made of silicon nitride (SiN).

[0096] In one embodiment, the etchant used has an etch selectivity greater than 10 when etching the CESL in the selective etch process compared to etching the first dielectric cap and the second dielectric cap.

[0097] In one embodiment, the method further includes forming gate spacers along sidewalls of the first metal gate stack and the second metal gate stack, wherein the first dielectric cap and the second dielectric cap are directly located above the first metal gate stack, the second gate stack and the gate spacers, wherein the CESL and the gate spacers are made of different materials, and the selective etching process selectively etches the CESL without substantially etching the gate spacers.

[0098] In one embodiment, the method further includes forming a dielectric layer adjacent to the gate spacer, wherein the dielectric layer surrounds the S / D contacts, wherein the CESL and the dielectric layer are made of different materials, and the selective process selectively etches the CESL without substantially etching the dielectric layer.

[0099] Another aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes receiving a workpiece having a first metal gate stack above a first channel region, a second metal gate stack above a second channel region, a source / drain (S / D) feature between the first channel region and the second channel region, and an S / D contact above the S / D feature. The method includes forming a first dielectric cap and a second dielectric cap that respectively cover and directly contact the first metal gate stack and the second metal gate stack. The method includes forming a contact etch stop layer (CESL) above the S / D contact and above the first dielectric cap and the second dielectric cap, wherein the CESL and the first dielectric cap and the second dielectric cap are made of different materials. An interlayer dielectric (ILD) layer is formed above the CESL. The method includes forming a gate through-hole trench through the ILD layer, through the CESL, and through the first dielectric cap, the gate through-hole trench exposing the top surface of the first metal gate. The method includes forming a gate through hole in the gate through-hole trench. The method includes forming an S / D via trench through the ILD layer and through the CESL, the S / D via trench exposing a top surface of the S / D contact and a side surface and a top surface of the gate via. The method includes forming an S / D via in the S / D via trench, wherein the S / D via is located on a top surface of the S / D contact and a side surface and a top surface of the gate via.

[0100] In one embodiment, a first patterning process and selective metal deposition with anisotropic metal growth are performed to form gate vias, and a second patterning process and isotropic metal growth are performed to form S / D vias. In another embodiment, the sidewalls of the S / D contacts have a conductive isolation layer, and the gate vias do not have any conductive isolation layer.

[0101] In one embodiment, the workpiece further includes a third metal gate stack over a third channel region, a second S / D feature adjacent to the third channel region, and a second S / D contact over the second S / D feature. The method further includes forming a third dielectric cap covering and directly contacting the third metal gate stack; forming a second gate via trench through the ILD layer, through the CESL, and through the third dielectric cap, the second gate via trench exposing a top surface of the third metal gate stack; forming a second gate via in the second gate via trench; forming a second S / D via trench through the ILD layer, through the CESL, the second S / D via trench exposing a top surface of the second S / D contact; and forming a second S / D via in the second S / D via trench. In another embodiment, the second gate via and the second S / D via are not bonded to each other and are both formed by selective metal deposition with anisotropic metal growth. In another embodiment, a first patterning process is performed to simultaneously form the first gate via and the second gate via.

[0102] Another aspect of the present disclosure relates to a semiconductor device. The device includes a metal gate stack above a channel region of a substrate; a gate spacer on a sidewall of the metal gate stack; and a dielectric cap covering and falling on the metal gate stack and the gate spacer. The device includes a first etch stop layer on the sidewall of the gate spacer and the dielectric cap; a source / drain (S / D) feature between the channel region of the substrate; and an S / D contact between the metal gate stack and falling on the S / D feature. The device includes a second etch stop layer above the dielectric cap, the first etch stop layer, and the S / D contact. The device includes an interlayer dielectric (ILD) layer above the second etch stop layer; and a first S / D via that passes through the ILD layer and the second etch stop layer and directly contacts the S / D contact and the dielectric cap by extending longitudinally in a first direction; wherein the second etch stop layer and the dielectric cap are made of different materials.

[0103] In one embodiment, the device further includes another S / D feature and another S / D contact falling on the other S / D feature; another gate stack adjacent to the other S / D feature; a gate via that passes through the ILD layer and the second etch stop layer, and the gate via falls on one of the metal gate stacks; a second S / D via that falls on the top surface of the other S / D contact and the side and top surfaces of the gate via.

[0104] In one embodiment, each metal gate stack includes a gate dielectric layer and a gate electrode, wherein the gate electrode includes a bottom and a top, the top of the gate electrode is disposed above the top surface of the gate dielectric layer, and wherein the top surface of the gate spacer is located above the top surface of the metal gate stack.

[0105] In one embodiment, the dielectric cap and the first etch stop layer are made of silicon nitride, and the second etch stop layer is made of silicon carbonate or silicon oxycarbide.

[0106] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a workpiece. The workpiece includes a first metal gate stack, a second metal gate stack, a source / drain feature, and a source / drain contact. The first metal gate stack is located above the first channel region. The second metal gate stack is located above the second channel region. The source / drain feature is located between the first channel region and the second channel region. The source / drain contact is located above the source / drain feature. The semiconductor device also includes a first dielectric cap, a second dielectric cap, a contact etch stop layer, an interlayer dielectric layer, and a source / drain via. The first dielectric cap is located above the first metal gate stack. The second dielectric cap is located above the second metal gate stack. The contact etch stop layer is located above the source / drain contact and above the first dielectric cap and the second dielectric cap, wherein the composition of the contact etch stop layer is different from the composition of the first dielectric cap and the second dielectric cap. The interlayer dielectric layer is located above the contact etch stop layer. The source / drain through hole penetrates the interlayer dielectric layer and the contact etch stop layer, wherein the source / drain through hole makes full surface contact with the source / drain contact, and the source / drain through hole and the first dielectric cap make partial surface contact with the second dielectric cap.

[0107] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a workpiece. The workpiece includes a first metal gate stack, a second metal gate stack, a source / drain feature, and a source / drain contact. The first metal gate stack is located above a first channel region. The second metal gate stack is located above the second channel region. The source / drain feature is located between the first channel region and the second channel region. The source / drain contact is located above the source / drain feature. The semiconductor device also includes a first dielectric cap, a second dielectric cap, a contact etch stop layer, an interlayer dielectric layer, a gate via, and a source / drain via. The first dielectric cap covers and directly contacts the first metal gate stack. The second dielectric cap covers and directly contacts the second metal gate stack. The contact etch stop layer is located above the source / drain contact and above the first dielectric cap and the second dielectric cap, wherein the contact etch stop layer and the first dielectric cap and the second dielectric cap are made of different materials. An interlayer dielectric layer is located above the contact etch stop layer. A gate through hole passes through the interlayer dielectric layer, the contact etch stop layer and the first dielectric cap, and the gate through hole contacts the top surface of the first metal gate. A source / drain through hole passes through the interlayer dielectric layer and the contact etch stop layer, and the source / drain through hole trench contacts the top surface of the source / drain contact and the side surface and top surface of the gate through hole.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the content of the present disclosure. It should be understood by those skilled in the art that the content of the present disclosure can be easily used as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions and modifications herein.

Claims

1. A semiconductor device, characterized in that: include: A work piece, comprising: a first metal gate stack located above a first channel region; a second metal gate stack located above a second channel region; a source / drain feature located between the first channel region and the second channel region; and a source / drain contact located above the source / drain feature; a first dielectric cap located above the first metal gate stack; a second dielectric cap located above the second metal gate stack; a contact etch stop layer over the source / drain contacts and over the first dielectric cap and the second dielectric cap, wherein the contact etch stop layer has a composition different from that of the first dielectric cap and the second dielectric cap; an interlayer dielectric layer located above the contact etch stop layer; and A source / drain through hole passes through the interlayer dielectric layer and the contact etch stop layer, wherein the source / drain through hole makes full surface contact with the source / drain contact, and the source / drain through hole and the first dielectric cap make partial surface contact with the second dielectric cap.

2. The semiconductor device according to claim 1, wherein The source / drain through hole has a length extending along a first direction from the first metal gate stack to the second metal gate stack, and has a width extending along a second direction perpendicular to the first direction, and the length is greater than the width.

3. The semiconductor device according to claim 1, wherein The contact etch stop layer includes carbon, and the first dielectric cap and the second dielectric cap do not include carbon.

4. The semiconductor device according to claim 3, wherein: The contact etch stop layer is made of silicon carbonate or silicon carbonitride, The first dielectric cap and the second dielectric cap are made of silicon nitride.

5. A semiconductor device, characterized in that: include: A work piece, comprising: a first metal gate stack located above a first channel region; a second metal gate stack located above a second channel region; a source / drain feature located between the first channel region and the second channel region; and a source / drain contact located above the source / drain feature; a first dielectric cap covering and directly contacting the first metal gate stack; a second dielectric cap covering and directly contacting the second metal gate stack; a contact etch stop layer located above the source / drain contacts and above the first dielectric cap and the second dielectric cap, wherein the contact etch stop layer and the first dielectric cap and the second dielectric cap are made of different materials; an interlayer dielectric layer located above the contact etch stop layer; a gate through hole passing through the interlayer dielectric layer, through the contact etch stop layer and through the first dielectric cap, the gate through hole contacting a top surface of the first metal gate; and A source / drain through hole passes through the interlayer dielectric layer and the contact etch stop layer, and the source / drain through hole trench contacts a top surface of the source / drain contact and a side surface and a top surface of the gate through hole.

6. The semiconductor device according to claim 5, wherein: The sidewalls of the source / drain contact have a conductive isolation layer, and the gate through hole does not have any of the conductive isolation layer.

7. A semiconductor device, characterized in that: include: A plurality of metal gate stacks are disposed above a plurality of channel regions of a substrate; a plurality of gate spacers on a plurality of sidewalls of the plurality of metal gate stacks; A plurality of dielectric caps covering and falling on the plurality of metal gate stacks and the plurality of gate spacers; a plurality of first etch stop layers on the plurality of sidewalls of the plurality of gate spacers and the plurality of dielectric caps; a plurality of source / drain features between the plurality of channel regions of the substrate; a plurality of source / drain contacts located between the plurality of metal gate stacks and overlying the plurality of source / drain features; a second etch stop layer over the plurality of dielectric caps, the plurality of first etch stop layers, and the plurality of source / drain contacts; an interlayer dielectric layer over the second etch stop layer; as well as a first source / drain through hole, passing through the interlayer dielectric layer and the second etch stop layer, and directly contacting the plurality of source / drain contacts and the plurality of dielectric caps by longitudinally extending along a first direction; The second etching stop layer and the plurality of dielectric caps are made of different materials.

8. The semiconductor device according to claim 7, wherein: Further including: another source / drain feature and another source / drain contact land on the other source / drain feature; another gate stack adjacent to another source / drain feature; a gate through hole, passing through the interlayer dielectric layer and the second etch stop layer, and the gate through hole falls on one of the plurality of metal gate stacks; and A second source / drain through hole is located on a top surface of another source / drain contact and a side surface and a top surface of the gate through hole.

9. The semiconductor device according to claim 7, wherein: Each of the plurality of metal gate stacks comprises a gate dielectric layer and a gate electrode, wherein the gate electrode comprises a bottom portion and a top portion, and a top portion of the gate electrode is disposed above a top surface of the gate dielectric layer. Wherein, multiple top surfaces of the multiple gate spacers are located above multiple top surfaces of the multiple metal gate stacks.

10. The semiconductor device according to claim 7, wherein: The plurality of dielectric caps and the plurality of first etching stop layers are made of silicon nitride, and the second etching stop layer is made of silicon carbonate or silicon oxycarbide.

Images