Semiconductor device

Abstract

A semiconductor device includes a first conductive feature formed over a substrate; the second conductive part is formed on the substrate, and the highest point of the top surface of the second conductive part is higher than the highest point of the top surface of the first conductive part; a first conformal dielectric layer over the first conductive feature and the second conductive feature; the conformal oxide layer is located above the first conformal dielectric layer, the conformal oxide layer comprises a first part arranged right above the first conductive part and a second part arranged above the second conductive part, and the thickness of the first part is equal to that of the second part; a second conformal dielectric layer on the conformal oxide layer, the second conformal dielectric layer including a non-planar top surface; a multilayer dielectric structure on the second conformal dielectric layer and having a flat top surface; the first joint structure is positioned on the first conductive component and is electrically coupled to the first conductive component; the second bonding structure is on and electrically coupled to the second conductive feature.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. During the evolution of ICs, functional density (that is, the number of interconnected devices per unit chip area) has generally increased while geometry size (that is, the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. Such size reductions also increase the complexity of the process and manufacturing of ICs.

[0003] For example, the packaging of integrated circuits has become increasingly complex, packaging more device dies in the same package to achieve more functions. System-on-integrate-chip (SoIC) has evolved to include many device dies in the same package, such as process devices and memory cubes. SoIC can include device dies formed using different technologies and having different functions connected to the same device die, thereby forming a system. This can save manufacturing costs and optimize device performance. Various conductive pads and bonding structures (e.g., bonding pad vias, bonding pad metal wires) are formed in the device die, so that SoIC can achieve satisfactory electrical functions. Although existing SoIC formation methods are generally adequate, they are not satisfactory in all aspects. Utility Model Content

[0004] The present disclosure aims to provide a semiconductor device to solve at least one of the above problems.

[0005] The present disclosure provides a semiconductor device, comprising: a first conductive component formed on a substrate; a second conductive component formed on the substrate, and the highest point of the top surface of the second conductive component is higher than the highest point of the top surface of the first conductive component; a first conformal dielectric layer located on the first conductive component and the second conductive component; a conformal oxide layer located on the first conformal dielectric layer, wherein the conformal oxide layer includes a first portion arranged directly above the first conductive component and a second portion arranged above the second conductive component, wherein the thickness of the first portion is substantially equal to the thickness of the second portion; a second conformal dielectric layer located on the conformal oxide layer, wherein the second conformal dielectric layer includes a non-planar top surface; a multilayer dielectric structure located on the second conformal dielectric layer and having a substantially flat top surface; a first bonding structure located on the first conductive component and electrically coupled to the first conductive component; and a second bonding structure located on the second conductive component and electrically coupled to the second conductive component.

[0006] According to one embodiment of the present disclosure, a thickness of the second conformal dielectric layer is greater than a thickness of the first conformal dielectric layer.

[0007] According to one embodiment of the present disclosure, a top surface of the second conformal dielectric layer includes a contour of a dished surface.

[0008] According to one embodiment of the present disclosure, the multilayer dielectric structure includes a non-planar bottom surface.

[0009] According to one embodiment of the present disclosure, the first conductive component is separated from another first conductive component adjacent to the first conductive component by a distance, wherein the distance is between 3 μm and 10 μm.

[0010] According to one embodiment of the present disclosure, the width of the second conductive component is greater than the width of the first conductive component.

[0011] According to one embodiment of the present disclosure, the first conductive component and the second conductive component have a convex top surface that is bent inward.

[0012] According to one embodiment of the present disclosure, the multilayer dielectric structure includes a first dielectric layer, wherein the first dielectric layer includes a first portion disposed directly above the first conductive component and a second portion disposed above the second conductive component, wherein a thickness of the first portion is greater than a thickness of the second portion.

[0013] According to one embodiment of the present disclosure, the thickness difference between the first portion and the second portion of the first dielectric layer is equal to the height difference between the highest point of the top surface of the second conductive component and the highest point of the top surface of the first conductive component.

[0014] According to one embodiment of the present disclosure, the first dielectric layer has a flat top surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments of the present disclosure are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various elements may be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure.

[0016] Figure 1 A flow chart of a method for forming a semiconductor structure is illustrated according to some embodiments of the present disclosure.

[0017] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 According to various embodiments of the present disclosure, a cross-sectional view is used to illustrate the Figure 1 A method of manufacturing a semiconductor structure during a process of manufacturing the semiconductor structure.

[0018] The reference numerals are as follows:

[0019] 100: Method

[0020] 102: Block

[0021] 104: Block

[0022] 106: Block

[0023] 108: Block

[0024] 110: Block

[0025] 112: Block

[0026] 114: Block

[0027] 116: Block

[0028] 118: Block

[0029] 120: Block

[0030] 122: Block

[0031] 124: Block

[0032] 126: Block

[0033] 128: Block

[0034] 200:Workpiece

[0035] 200A: First Area

[0036] 200B: Second area

[0037] 200p: top surface

[0038] 200t: Top surface

[0039] 202:IC substrate

[0040] 206: Interconnection structure

[0041] 208: Dielectric Materials

[0042] 210:Metal Wire

[0043] 212: Passivation film

[0044] 214: first conductive layer

[0045] 214a: first conductor plate

[0046] 214b: first dummy board

[0047] 216: first insulating layer

[0048] 218a: second conductor plate

[0049] 218b: Second dummy board

[0050] 220: Second insulation layer

[0051] 222a: third conductor plate

[0052] 222b: The third dummy board

[0053] 224:MIM capacitor

[0054] 226: Passivation structure

[0055] 228a: Passivation structure

[0056] 228b: Passivation structure

[0057] 228c: Passivation structure

[0058] 230: Barrier layer

[0059] 232: Seed layer

[0060] 234: Filling layer

[0061] 236: Conductive pad

[0062] 238: Conductive pad

[0063] 240: Conductive pad

[0064] 242: Conductive pad

[0065] 244: first etching stop layer

[0066] 246: Dielectric structure

[0067] 246d: Curved surface

[0068] 247: Planarization process

[0069] 248: Planarization process

[0070] 248d: Surface

[0071] 250: Second etching stop layer

[0072] 250d: curved surface

[0073] 252: first dielectric layer

[0074] 254: third etching stop layer

[0075] 256: Second dielectric layer

[0076] 258: Anti-reflection layer

[0077] 261: First etching process

[0078] 262a: Opening

[0079] 262b: Opening

[0080] 264: Second etching process

[0081] 266a: Opening

[0082] 266b: Opening

[0083] 268: The third etching process

[0084] 270a: Opening

[0085] 270b: Opening

[0086] 272:Joint structure

[0087] 274:Joint structure

[0088] D1: Distance

[0089] H1: Height

[0090] H2: Height

[0091] H3: Height

[0092] W1: Width

[0093] W2: Width

[0094] T0:Thickness

[0095] T1: Thickness

[0096] T2: Thickness

[0097] T3:Thickness

[0098] T4:Thickness

[0099] T5:Thickness DETAILED DESCRIPTION

[0100] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the illustration of the embodiments of the present disclosure. Of course, the above are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed above a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0101] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used to facilitate describing the relationship between one feature or component and another feature or component in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0102] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range that takes into account variations inherent in manufacturing processes as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing components having features associated with the number, the number or range of numbers covers a reasonable range including the number, such as within + / -10% of the number. For example, a manufacturing tolerance associated with a deposited material layer is known to those skilled in the art to be + / -15%, and a material layer having a thickness of "about 5 nanometers" may cover a size range of 4.25 nanometers to 5.75 nanometers.

[0103] The present disclosure provides various embodiments of system-level integrated chip (SoIC) packages and methods for forming the same. In an exemplary method, conductive pads having different profiles are formed. For example, the top surface of a first type of conductive pad formed in a first area of ​​a workpiece is higher than the top surface of a second type of conductive pad formed in a second area of ​​the workpiece. The height difference between these top surfaces may produce a loading effect on at least some of the dielectric layers formed on those conductive pads. The loading effect can be mitigated or substantially eliminated by forming an etch stop layer of different thicknesses, controlling the polishing endpoint of the planarization process, and performing different etching processes to form openings for bonding structures therein without over-etching those conductive pads. Therefore, the yield and reliability of the SoIC package can be improved. An intermediate stage of forming a SoIC package is described according to some embodiments. It should be understood that although the formation of the SoIC package is used as an example to explain the concepts of the embodiments of the present disclosure, the embodiments of the present disclosure are easily applicable to other bonding methods and structures.

[0104] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a flow chart showing a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 2-Figure 22 Describing method 100, Figure 2-Figure 22 is a partial cross-sectional view of a workpiece 200 at different stages of manufacture according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit the present disclosure to the content explicitly illustrated therein. Additional steps may be provided before, during, and after method 100, and some of the steps described may be replaced, deleted, or moved for additional embodiments of the method. For the sake of brevity, not all steps are described in detail here. Because workpiece 200 will be manufactured into a semiconductor structure or SoIC package at the end of the manufacturing process, workpiece 200 may be referred to as semiconductor structure 200 or SoIC package 200 as the context requires. Throughout this disclosure, unless otherwise specified, similar element numbers represent similar parts.

[0105] refer to Figure 1 and Figure 2 , method 100 includes block 102, in which a work piece 200 is received. In various embodiments, work piece 200 may be referred to as semiconductor structure 200. Work piece 200 includes an IC substrate 202. In some embodiments, IC substrate 202 includes a semiconductor substrate, such as a silicon substrate. IC substrate 202 may also include various devices, such as field-effect transistors (FETs), memory cells, imaging sensors, passive devices, other devices, or combinations thereof. In some embodiments, IC substrate 202 includes a flat active region with various IC devices, such as a planar field effect transistor (FET). In some other embodiments, IC substrate 202 includes a fin (e.g., vertically protruding) active region on which various IC devices are formed. As a non-limiting example, a circuit (not shown) may be formed in IC substrate 202. The circuit may include a planar transistor or a FinFET type transistor.

[0106] The workpiece 200 also includes an interconnect structure 206 formed above the IC substrate 202. The interconnect structure 206 includes various conductive components, such as metal lines (e.g., metal lines 210), contacts, and vias to provide horizontal and vertical electrical wiring. Metal lines such as metal lines 210 are distributed in multiple metal layers, such as a first metal layer (e.g., M1 layer), a second metal layer (e.g., M2 layer), etc., and a top metal layer. Among them, the conductive components of the interconnect structure 206 can provide electrical connections to circuits in the IC substrate 202. The interconnect structure 206 also includes a dielectric material 208, which is configured to provide electrical isolation between various conductive components to prevent short circuits. The dielectric material 208 may include a plurality of dielectric layers and may be formed of phospho silicate glass (PSG), boro silicate glass (BSG), boron-doped phospho silicate glass (BPSG), fluorine-doped silicic glass (FSG), tetraethylorthosilicate (TEOS), etc., and may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc. In some embodiments, the dielectric material 208 may be formed of a low-k dielectric material having a k value lower than about 3.0. The dielectric material 208 may also be formed of an extra-low-k (ELK) dielectric material having a k value less than 2.5. In some embodiments, the dielectric material 208 may be formed of an oxygen- and / or carbon-containing low-k dielectric material, Hydrogen Silses Quioxane (HSQ), Methyl Silses Quioxane (MSQ), etc., or a combination thereof. In some embodiments, part or all of the dielectric layers of the dielectric material 208 are formed of non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), etc. In some embodiments, an etch stop layer (not shown) formed of silicon carbide, silicon nitride, etc. may be formed between the dielectric layers of the dielectric material 208.In some embodiments, the dielectric layer of dielectric material 208 is formed of a porous material such as SiOCN, SiCN, SiOC, SiOCH, etc. In some embodiments, interconnect structure 206 may include one or more other types of layers, such as a diffusion barrier layer (not shown). In some embodiments, the conductive features (e.g., metal lines 210) of interconnect structure 206 may be made of, for example, tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, or alloys thereof.

[0107] In some embodiments, the interconnect structure 206 may be formed using a damascene process and / or a dual damascene process, a via-first process, or a metal-first process. In one embodiment, an insulating layer (not separately labeled) is formed, and an opening (not shown) is formed therein using acceptable photolithography and etching techniques. A diffusion barrier layer (not shown) may be formed in the opening and may include materials such as TaN, Ta, TiN, Ti, CoW, etc., and may be formed in the opening using a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The conductive material may be formed in the opening from copper, aluminum, nickel, tungsten, cobalt, silver, combinations of the foregoing, etc., and may be formed over the diffusion barrier layer in the opening using an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc., or a combination thereof. After forming the conductive material, excess conductive material may be removed using, for example, a planarization process such as chemical mechanical polishing (CMP), thereby leaving conductive features (e.g., metal line 210) in the openings of the corresponding insulating layers. The process may then be repeated to form additional insulating layers and conductive features therein.

[0108] refer to Figure 1 and Figure 3-Figure 8 , the method 100 includes block 104, wherein a metal-insulator-metal (MIM) capacitor 224 is formed in the first region 200A of the workpiece 200 and over the interconnect structure 206. Referring now to Figure 3In some embodiments, before forming the MIM capacitor 224, a passivation film 212 is formed over the interconnect structure 206, for example, over the top metal layer of the interconnect structure 206. The passivation film 212 can provide protection for the IC substrate 110. In some embodiments, the passivation film 212 includes a silicon nitride (SiN) film and an undoped silica glass (USG) film on the SiN film. These films are formed by a suitable deposition technique, such as high density plasma chemical vapor deposition (HDPCVD) and the like.

[0109] like Figure 3 As shown, the formation of the MIM capacitor 224 includes forming a first conductive layer 214 over the passivation film 212. The first conductive layer 214 can be deposited on the workpiece 200 using PVD, CVD, or metal organic chemical vapor deposition (MOCVD). In some embodiments, the first conductive layer 214 can include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), cobalt (Co), nickel (Ni), tungsten (W), aluminum (Al), or other suitable materials. The first conductive layer 214 can cover the entire top surface of the workpiece 200. After forming the first conductive layer 214, as shown in FIG. Figure 4 As shown, the first conductive layer 214 is patterned to form a first conductor plate 214a and a first dummy plate 214b in the first region 200A. The patterning step may include depositing a hard mask layer over the first conductive layer 214, forming a photoresist layer over the hard mask layer, patterning the photoresist layer using photolithography, etching the hard mask layer using the patterned photoresist layer as an etching mask, and then etching the first conductive layer 214 using the patterned hard mask as an etching mask. After forming the first conductive plate 214a and the first dummy plate 214b, the hard mask layer and the photoresist layer may be selectively removed.

[0110] The formation steps of the MIM capacitor 224 then proceed to forming a first insulator layer 216 over the workpiece 200. Figure 5As shown, after patterning the first conductive layer 214 to form the first conductor plate 214a and the first dummy plate 214b, the first insulating layer 216 is deposited. In one embodiment, the first insulator layer 216 is conformally deposited to have a substantially uniform thickness on the top surface of the workpiece 200 (e.g., having substantially the same thickness on the top surface and the sidewall surface of the first conductor plate 214a). The first insulator layer 216 can be deposited using CVD, ALD, or a suitable deposition method and can be a high dielectric constant (high-k) dielectric layer including hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, or a combination thereof.

[0111] After forming the first insulator layer 216, refer to Figure 6 , the formation step of the MIM capacitor 224 proceeds to forming a second conductor plate 218a and a second dummy plate 218b on the first insulator layer 216 and in the first region 200A. In this example, the second conductor plate 218a is formed directly above the first conductor plate 214a and overlaps vertically, and the second dummy plate 218b is formed directly above the first dummy plate 214b and overlaps vertically. The formation of the second conductor plate 218a and the second dummy plate 218b can be similar to the formation of the first conductor plate 214a and the first dummy plate 214b, respectively. For example, a second conductive layer can be deposited above the workpiece 200 and then patterned to form the second conductor plate 218a and the second dummy plate 218b.

[0112] In this embodiment, after forming the second conductor plate 218a, refer to Figure 7 , the formation step of the MIM capacitor 224 proceeds to forming a second insulating layer 220 over the workpiece 200. In one embodiment, the second insulating layer 220 is conformally deposited to have a substantially uniform thickness on the top surface of the workpiece 200 (e.g., having substantially the same thickness on the top surface and the sidewall surface of the second conductor plate 218a). The formation and composition of the second insulating layer 220 can be similar to the formation and composition of the first insulating layer 216, and repeated descriptions are omitted for brevity.

[0113] exist Figure 8 In the illustrated embodiment, the step of forming the MIM capacitor 224 continues by forming a third conductor plate 222a and a third dummy plate 222b on the second insulating layer 220 and in the first region 200A. Figure 8In the illustrated embodiment, the third conductor plate 222a is formed directly above the second conductor plate 218a and vertically overlaps with the first conductor plate 214a, and the third dummy plate 222b is formed directly above the second conductor plate 218a without vertically overlapping with the first conductor plate 214a. The formation and composition of the third conductor plate 222a and the third dummy plate 222b can be similar to the formation and composition of the first conductor plate 214a and the first dummy plate 214b, respectively, and repeated description is omitted for brevity.

[0114] After forming the third conductor plate 220a, the structure of the MIM capacitor 224 is completed. It should be noted that the MIM capacitor 224 is a multi-plate capacitor, which may include more than two conductor plates (or more than two metal layers). Figure 8 The MIM capacitor 224 shown may include three conductor plates 214a, 218a, and 222a stacked vertically on top of each other. Since the capacitor includes two electrodes, some of these conductor plates may be electrically coupled together to function as one electrode. It should also be understood that Figure 3-Figure 8 Only non-limiting examples of manufacturing processes for the MIM capacitor 224 are illustrated. Figure 8 The arrangement or configuration of the various conductor plates 214a, 218a and 222a of the MIM capacitor 224 shown in the figure is not intended to represent a limitation. In other embodiments, the MIM capacitor 224 can have other shapes or configurations, or other numbers of functional conductors or metal plates (e.g., more than three) and dummy plates.

[0115] refer to Figure 1 and Fig. 9 , the method 100 includes block 106, where a passivation structure 226 is formed over the MIM capacitor 224. Fig. 9 As shown, MIM capacitor 224 is sandwiched between passivation structure 226 and passivation film 212. In some embodiments, passivation structure 226 may include a dielectric layer or two or more dielectric layers formed of any suitable material such as silicon oxide or silicon nitride. In one embodiment, passivation structure 226 includes silicon oxide formed by plasma enhanced chemical vapor deposition (PECVD).

[0116] refer to Figure 1 and Fig.10 , the method 100 includes block 108, where openings 228a, 228b, and 228c are formed in the first region 200A. After forming the passivation structure 226, a patterned mask film (not shown) is formed on the passivation structure 226. When the patterned mask film is used as an etching mask, an etching process can be performed to form the openings 228a-228c, such as Fig.10In the illustrated embodiment, the opening 228a extends through the third conductor plate 222a and the first conductor plate 214a, the opening 228b extends through the third dummy plate 222b and the second conductor plate 218a, and the opening 228c extends through the first dummy plate 214b and the second dummy plate 218b. It is understood that the openings 228a-228c may also extend through the passivation film 212 and expose the conductive components (e.g., metal lines 210) of the interconnect structure 206, so that at least some of the conductive pads to be formed (e.g., Fig.11 Conductive pads 236, 238, 240 (shown in FIG. 2 ) may electrically interconnect electrodes or conductor plates of the MIM capacitor 224 to the interconnect structure 206. After the openings 228a-228c are formed, the patterned mask film may be selectively removed.

[0117] refer to Figure 1 and Fig.11 The method 100 includes block 108 wherein a first type of conductive pad (e.g., conductive pads 236, 238, 240) is formed in a first region 200A of the workpiece 200 and a second type of conductive pad (e.g., conductive pad 242) is formed in a second region 200B of the workpiece 200. After the openings 228a-228c are formed in the first region 200A, refer to Fig.11 , first type conductive pads (e.g., conductive pads 236, 238, and 240) are formed in openings 228a-228c in the first region 200A and above the passivation structure 226, respectively, and second type conductive pads (e.g., conductive pads 242) are formed above the passivation structure 226 and in a second region 200B adjacent to the first region 200A. More specifically, in the present embodiment, in order to form conductive pads in the first region 200A and the second region 200B, a barrier material layer (not shown) is first conformally deposited on the passivation structure 226 and into the openings 228a-228c using a suitable deposition technique, such as ALD, PVD, or CVD. The barrier material layer may include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, cobalt nitride, tungsten nitride, ruthenium, ruthenium nitride, other metals, or other metal nitrides. After the barrier material layer is formed, a blanket seed material layer is then formed over the barrier material. The seed material layer may include copper or a copper alloy. In one embodiment, the seed material layer is formed of copper. The barrier material layer and the seed material layer may then be patterned to form a barrier layer 230 and a seed layer 232 in the openings 228a-228c in the first region 200A and the second region 200B and over the passivation structure 226. The barrier layer 230 and the seed layer 232 in the first region 200A include portions in the openings 228a-228c and portions directly over the passivation structure 226, and all of the barrier layer 230 and the seed layer 232 in the second region 200B are formed directly over the passivation structure 226.

[0118] After forming the barrier layer 230 and the seed layer 232, an electrochemical plating (ECP) process is performed to form a metal filling layer 234 on the seed layer 232. In one embodiment, the metal filling layer 234 is formed of copper (Cu). The barrier layer 230, the seed layer 232, and the metal filling layer 234 formed in and above the opening 228a are collectively referred to as a conductive pad 236. The barrier layer 230, the seed layer 232, and the metal filling layer 234 formed in and above the opening 228b are collectively referred to as a conductive pad 238. The barrier layer 230, the seed layer 232, and the metal filling layer 234 formed in and above the opening 228c are collectively referred to as a conductive pad 240. The barrier layer 230, the seed layer 232, and the metal filling layer 234 formed directly above the passivation structure 226 in the second region 200B of the workpiece are collectively referred to as a conductive pad 242. In this embodiment, Fig.11 Two conductive pads 242 are illustrated in the figure, but it should be understood that the workpiece 200 may include any suitable number of conductive pads 242. The conductive pads (e.g., conductive pads 236, 238, 240) formed in the first area 200A may be referred to as first type conductive pads. The conductive pads 242 formed in the second area 200B may be referred to as second conductive pads 242. The first and second types of conductive pads may have a convex top surface that is curved inward. In some embodiments, each first type conductive pad 236 / 238 / 240 spans a width W1 along the X direction, and each conductive pad 242 spans a width W2 along the X direction, and the width W2 may be greater than the width W1 to provide a flexible bonding configuration. Two adjacent conductive pads in the conductive pads 236 / 238 / 240 are separated by a distance D1. In some embodiments, in order to provide a compact SoIC, the distance D1 is between about 3μm and about 10μm.

[0119] During the electrochemical plating (ECP) process, due to the nature of the ECP process, when the metal filling layer 234 in the first region 200A is formed to first fill the openings 228a-228c, the metal filling layer 234 in the second region 200B is formed directly above the passivation structure 226. That is, due to the presence of the openings 228a-228c in the first region 200A, after the ECP process, the portion of the metal filling layer 234 formed directly above the protection structure 226 in the first region 200A has a height H1 that is less than the height H2 of the metal filling layer 234 formed directly above the passivation structure 226 in the second region 200B. In other words, the highest point of the top surface of the second type conductive pad 242 is higher than the highest point of the top surface of the first type conductive pad 236 / 238 / 240. In one embodiment, the height difference H3 between the height H1 and the height H2 is between about 1 μm and 2.5 μm. It should be noted that in embodiments where the metal filling layer 234 is not formed by ECP, the height difference H3 can be ignored. For example, in embodiments where the metal filling layer 234 is formed using CVD or ALD and may include Al or AlCu, after the deposition process, a planarization process and a combination of photolithography and etching processes may be performed to form a metal filling layer mainly composed of Al. In this way, the top surfaces of the first type conductive pad and the second type conductive pad will be substantially coplanar. That is, the present disclosure mainly focuses on solving problems caused by the ECP process (e.g., the loading effect of the dielectric layer formed on the conductive pad).

[0120] refer to Figure 1 and Fig.12 , the method 100 includes block 112, wherein a first etch stop layer 244 is conformally formed over the work piece 200. After forming the first type conductive pads 236, 238, 240 and the second type conductive pads 242, the first etch stop layer 244 is conformally formed over the work piece 200 using CVD, ALD or a suitable deposition method to have a substantially uniform thickness T0 on the top surface of the work piece 200. The first etch stop layer 244 is configured to indicate a polishing endpoint of a subsequent planarization process (e.g., planarization process 247) and an etching endpoint of a subsequent etching process (e.g., etching process 268). In one embodiment, the first etch stop layer 244 includes silicon nitride (SiN). To ensure that the subsequently formed dielectric layer (e.g., dielectric structure 246) can substantially fill the space between two adjacent first conductive pads to provide good isolation, and due to the limitation of the distance D1, the thickness T0 of the first etch stop layer 244 can be between about 0.05 μm and about 0.25 μm.

[0121] refer to Figure 1 and Fig.13, the method 100 includes block 114, where a dielectric structure 246 is formed over the first etch stop layer 244. Fig.13 After forming the first etch stop layer 244, a dielectric structure 246 is formed on the first etch stop layer 244. In some embodiments, the dielectric structure 246 may be used as a polishing film. The dielectric structure 246 may include one or more dielectric layers. In one embodiment, the formation of the dielectric structure 246 includes forming an oxide layer by performing a high density plasma chemical vapor deposition (HDPCVD) process, and then forming a dielectric layer (e.g., an undoped quartz glass (USG) film) on the oxide layer using CVD, ALD, or other suitable processes. Due to the height difference H3, as shown in FIG. Fig.13 As shown, the dielectric structure 246 suffers from topography dishing (eg, curved surface 246 d ), particularly in the region between the first type conductive pad 240 and the second type conductive pad 242 adjacent to the first type conductive pad 240 .

[0122] refer to Figure 1 and Fig.14 , the method 100 includes block 116, where a planarization process (e.g., CMP) 247 is performed on the workpiece 200. In this embodiment, the polishing endpoint of the planarization process 247 is controlled by the first etch stop layer 244. Since the first etch stop layer 244 has a non-planar top surface and due to the height difference H3, as shown in FIG. Fig.14 As indicated in FIG. 2 , after the planarization process 247, the workpiece 200 has a non-planar top surface 200t. The height difference H3 between the first type conductive pads 236 / 238 / 240 and the second type conductive pads 242 may also cause process problems in the planarization process 247 in the area between the first type conductive pads 240 and the second type conductive pads 242 adjacent to the first type conductive pads 240, such as dishing (e.g., curved surface 246d). Fig.14 The dishing shown in FIG. 5 is caused by uneven material removal rates during the planarization process.

[0123] If the planarization process 247 is configured to provide the workpiece 200 with a substantially planar top surface 200p (eg, Fig.13In other words, the portion of the planarized dielectric structure 246 formed directly above the first type conductive pad 236 / 238 / 240 is thicker than the portion of the planarized dielectric structure 246 formed directly above the second type conductive pad 242. The thickness difference may be substantially equal to the height difference H3. However, this loading effect will adversely affect the etching results of the etching process implemented to form the bonding structure opening (e.g., openings 270a-270b). More specifically, when the etching process duration is short, the portion of the planarization dielectric structure 246 formed directly above the first type conductive pad 236 / 238 / 240 may not be completely etched to expose the first type conductive pad 236 / 238 / 240, resulting in poor electrical connection between the first type conductive pad 236 / 238 / 240 and the subsequently formed bonding structure 272, thereby reducing the yield of the semiconductor structure 200; when the etching process duration is long, the portion of the thin first etch stop layer 244 formed directly on the second type conductive pad 242 may be removed earlier than the portion formed directly on the first type conductive pad 236 / 238 / 240, and the second type conductive pad 242 (formed of copper) thereunder may be over-etched. The particles generated due to the over-etching of the second conductive pad 242 may adversely affect the performance of the semiconductor structure 200. Therefore, in the present disclosure, the polishing endpoint of the planarization process 247 is controlled to stop at the first etch stop layer 244, and the resulting workpiece 200 (such as Fig.14 ) has a non-flat top surface 200t.

[0124] refer to Figure 1 and Fig.15, the method 100 includes block 118, wherein a dielectric layer 248 is conformally formed over the work piece 200. After performing the planarization process 247, the dielectric layer 248 is conformally deposited to have a substantially uniform thickness on the top surface of the work piece 200. That is, the top surface of the dielectric layer 248 is non-planar and has a dished surface profile (e.g., a curved surface 248d). The dielectric layer 248 can be deposited using CVD, ALD, or other suitable processes and can include USG. Since the planarization process 247 stops at the first etch stop layer 244 and the dielectric layer 248 is conformally deposited, the thickness T1 of the portion of the dielectric layer 248 directly disposed over the first type conductive pad 236 / 238 / 240 is substantially equal to the thickness T2 of the portion of the dielectric layer 248 disposed directly over the second conductive pad 242. The ratio of the height difference H3 to the thickness difference between the thickness T1 and the thickness T2 (i.e., |T1-T2|) is greater than 20. In one embodiment, the thickness difference between the thickness T1 and the thickness T2 (ie, | T1 − T2 |) is less than about 0.05 μm.

[0125] refer to Figure 1 and Fig.16 , method 100 includes block 120, wherein a second etch stop layer 250 is conformally formed over the work piece 200. The second etch stop layer 250 is conformally formed over the work piece 200 using CVD, ALD, or a suitable deposition method and has a substantially uniform thickness T3 over the top surface of the work piece 200 over the work piece 200. That is, the top surface of the second etch stop layer 250 is non-planar and has a dished surface profile (e.g., curved surface 250d). The second etch stop layer 250 is configured to indicate an etch endpoint of a subsequent etching process (e.g., etching process 264). In one embodiment, the second etch stop layer 250 includes silicon nitride (SiN). As Fig.17 As shown and will be described later, the portion of the first dielectric layer 252 formed directly above the first type conductive pads 236 / 238 / 240 is thicker than the portion of the first dielectric layer 252 formed directly above the second type conductive pads 242. In order to provide satisfactory etching results for subsequent etching processes, a thick second etch stop layer 250 is formed (relative to the thin first etch stop layer 244) so ​​that the thick second etch stop layer 250 can withstand the etching process for a longer time. In some embodiments, to achieve this goal, the ratio of the thickness T3 of the second etch stop layer 250 to the thickness T0 of the first etch stop layer 244 is between about 2 and about 10. In one embodiment, the thickness T3 is between about 0.5 μm and about 3 μm.

[0126] refer to Figure 1 and Fig.17, method 100 includes block 122, where a multilayer dielectric structure 260 is formed above the second etch stop layer 250. In the present embodiment, the formation of the multilayer dielectric structure 260 includes forming a first dielectric layer 252 on the second etch stop layer 250. The first dielectric layer 252 may be formed using PVD, CVD, ALD, or a suitable deposition method. In one embodiment, the first dielectric layer 252 includes TEOS. Fig.17 As shown in , the first dielectric layer 252 has a non-planar bottom surface. After depositing the first dielectric layer 252, a planarization process is performed on the first dielectric layer 252 to provide a substantially planar top surface of the first dielectric layer 252. Fig.17 As shown in , the substantially flat top surface of the flat first dielectric layer 252 is above the non-flat top surface of the second etch stop layer 250. Due to the non-flat top surface of the second etch stop layer 250 and the planarization of the first dielectric layer 252, the thickness T4 / 240 of the portion of the flat first dielectric layer 252 disposed directly above the first type conductive pad 236 / 238 is greater than the thickness T5 of the flat first dielectric layer 252 directly above the second conductive pad 242. The thickness difference between the thickness T4 and the thickness T5 (i.e., |T4-T5|) may be substantially equal to the height difference H3. However, as described above, due to the formation of a thicker second etch stop layer 250, this thickness difference (i.e., |T4-T5|) does not significantly affect the etching result of the subsequent etching process 266.

[0127] After forming the first dielectric layer 252 having a substantially flat top surface, still referring to Fig.17 , the step of forming the multilayer dielectric structure 260 continues to form a third etch stop layer 254. The third etch stop layer 254 is similar to the second etch stop layer 250. One of the differences between the third etch stop layer 254 and the second etch stop layer 250 is that the third etch stop layer 254 has a substantially flat top surface and a substantially flat bottom surface, while the second etch stop layer 250 has a non-flat top surface and a non-flat bottom surface. In one embodiment, the third etch stop layer 254 includes silicon nitride, and the thickness of the third etch stop layer 254 can be continuously equal to the thickness T3.

[0128] The formation step of the multilayer dielectric structure 260 then proceeds to forming a second dielectric layer 256 on the third etch stop layer 254. The second dielectric layer 256 may include TEOS and may serve as a bonding film. In some embodiments, the second dielectric layer 256 may be formed using ALD, CVD or other suitable processes and have a substantially flat top surface. After forming the second dielectric layer 256, an anti-reflective layer 258 is deposited above the second dielectric layer 256 to improve the photolithography process performance. In one embodiment, the anti-reflective layer 258 includes silicon oxynitride (SiON). The first dielectric layer 252, the third etch stop layer 254, the second dielectric layer 256 and the anti-reflective layer 258 are collectively referred to as a multilayer dielectric structure 260. It should be understood that the multilayer dielectric structure 260 may have other configurations and include different dielectric layers.

[0129] refer to Figure 1 and Figure 18-Figure 20 The method 100 includes block 124, where a plurality of etching processes are performed to form openings 270a exposing the first type conductive pads 236 / 238 / 240 and openings 270b exposing the second type conductive pads 242. Fig.18 After forming the multilayer dielectric structure 260, a first etching process 261 is performed to form an opening 262a in the first region 200A and an opening 262b in the second region 200B. In the present embodiment, the first etching process 261 stops at the third etch stop layer 254. A combination of photolithography and etching processes is performed to define Fig.18262a and 262b shown in . For example, forming the openings 262a and 262b includes performing a photolithography process to form a patterned impedance layer on the multilayer dielectric structure 260 and performing a first etching process 261 to transfer the pattern defined in the patterned impedance layer to the anti-reflective layer 258 and the second dielectric layer 256. The photolithography process may include forming a impedance layer (not shown) on the anti-reflective layer 258 (for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process. In the exposure process, the impedance layer is exposed to radiation energy (for example, ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light), wherein the mask pattern, the transmitted and / or reflected radiation is projected onto the impedance layer according to the mask pattern and / or the mask type (for example, a binary mask, a phase shift mask, or an EUV mask) of the mask, so that the image is projected onto the impedance layer corresponding to the mask pattern. Since the impedance layer is sensitive to radiation energy, the exposed portion of the impedance layer undergoes chemical changes, and the exposed (or unexposed) portion of the impedance layer dissolves in the development process, depending on the characteristics of the impedance layer and the characteristics of the development solution used in the development process. After development, the patterned impedance layer includes an impedance pattern corresponding to the mask. The first etching process 261 uses the patterned impedance layer as an etching mask to remove portions of the anti-reflective layer 258 and the second dielectric layer 256 to form openings 262a and 262b. After the openings 262a and 262b are formed, the patterned impedance layer can be removed.

[0130] refer to Fig.19 , after forming the openings 262a and 262b, a second etching process 264 is performed to vertically extend the openings 262a and 262b, thereby forming an extended opening 262a in the first region 200A and an extended opening 262b in the second region 200B. The extended opening 262a in the first region 200A may be referred to as an opening 266a, and the extended opening 262b in the second region 200B may be referred to as an opening 266b. A patterned mask film may be formed before performing the second etching process 264. In one embodiment, the second etching process 264 may implement a first etchant to selectively etch the third etch stop layer 254 relative to the first dielectric layer 252, implement a second etchant to selectively etch the first dielectric layer 252 relative to the second etch stop layer 250, and implement a third etchant to selectively etch the second etch stop layer 250. In other words, the second etching process 264 may include a subset of etching processes, and each of the subsets of etching processes is configured to achieve a different function. As described above with respect to Fig.17As described above, although the portion of the first dielectric layer 252 disposed directly above the first type conductive pad 236 / 238 / 240 is thicker than the portion of the first dielectric layer 252 disposed directly above the second type conductive pad 242, in addition to implementing an etching process that can selectively etch the first dielectric layer 252 without substantially etching the second etch stop layer 250, the second etch stop layer 250 is configured to have a thickness that can withstand a longer etching time. In this way, the portion of the first dielectric layer 252 disposed directly above the first type conductive pad 236 / 238 / 240 and the portion of the first dielectric layer 252 disposed directly above the second type conductive pad 242 can be selectively removed within the etching duration without substantially damaging the second etch stop layer 250. In other words, the thickness difference |T4-T5| may not significantly affect the etching result of the second etching process 264.

[0131] refer to Fig. 20 , after forming the openings 266a and 266b, a third etching process 268 is performed to vertically extend the openings 266a and 266b, thereby forming an extended opening 266a in the first region 200A and an extended opening 266b in the second region 200B. The extended opening 266a in the first region 200A may be referred to as an opening 270a, and the extended opening 266b in the second region 200B may be referred to as an opening 270b. In one embodiment, the third etching process 268 may implement a first etchant to selectively etch the dielectric layer 248 and implement a second etchant to selectively etch the first etch stop layer 244 to expose the first type and second type conductive pads thereunder. The extent to which the dielectric layer 248 is etched may be controlled by the duration of the third etching process 268. As described above, the dielectric layer 248 is a conformal dielectric layer and has a thickness T1 (e.g., Fig.15 ) is substantially equal to thickness T2 (as shown Fig.15 ). The first etch stop layer 244 is also a conformal dielectric layer. Therefore, the first type conductive pads 236 / 238 / 240 and the second type conductive pads 242 can be exposed to the openings 270a and 270b substantially at the same time. That is, after performing the third etching process 268, the degree of etching the first type conductive pads 236 / 238 / 240 is substantially equal to the degree of etching the second type conductive pads 242. In one embodiment, the degree difference is less than about 0.05μm. Therefore, by controlling the duration of the third etching process 268, the first type conductive pads will not be under-etched, the second type conductive pads will not be over-etched, and a satisfactory electrical connection can be provided between the conductive pads and the bonding structures 272 / 274 to be formed thereon.

[0132] refer to Figure 1 and Fig.21, method 100 includes block 126, wherein a bonding structure 272 is formed in the opening 270a in the first region 200A and a bonding structure 274 is formed in the opening 270b in the second region 200B. The formation steps of bonding structures 272 and 274 may include depositing a conductive material over the workpiece 200 and into the openings 270a and 270b. In some embodiments, the conductive material may include a double-layer structure. For example, to deposit the conductive material, a barrier layer (not separately labeled) is first conformally deposited over the workpiece and into the openings 270a and 270b using a suitable deposition technique (e.g., ALD or CVD), and then a metal fill layer (not separately labeled) is deposited on the barrier layer using ALD, PVD, CVD, chemical plating, or electroplating. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), or another metal nitride. The metal fill layer may be formed of any suitable material, such as copper (Cu), aluminum (Al). After the deposition of the conductive material, a planarization process (e.g., CMP) may then be performed so that the conductive material has a flat top surface. The portion of the conductive material formed above the first dielectric layer 252 may be referred to as a bonding pad metal line (BPM), and the portion of the conductive material formed below the bonding pad metal line may be referred to as a bonding pad via (BPV). The bonding structure 272 tracks the shape of the opening 270a, and the bonding structure 274 tracks the shape of the opening 270b.

[0133] refer to Figure 1 and Fig. 22, method 100 includes block 128, in which further processes are performed. Such further processes may include performing a singulation process along the scribing lines (not shown) of the workpiece 200 to separate adjacent device structures in the circuit of the workpiece 200 to form separate semiconductor grains. Prior to the singulation process, the back side of the substrate 202 may be attached to a carrier substrate (not shown) by an adhesive layer (not shown). The carrier substrate may be formed of a semiconductor material (e.g., silicon), or may be a glass substrate, a ceramic substrate, or the like. The adhesive layer may include a die attach film (DAF) such as an epoxy resin, a phenolic resin, an acrylic rubber, a silica filler, or a combination thereof, and may be applied with a lamination technique. The singulation process may include a plasma cutting process, a laser cutting process, a sawing process, or a combination thereof. In some embodiments, a dielectric region (also referred to as a "gap-filling dielectric" region) may be formed around the semiconductor grains. The dielectric region may be formed of one or more layers of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, etc., or a combination thereof, and may be formed using processes such as CVD, PECVD, PVD, etc., or a combination thereof. The individual semiconductor die is used to bond with another semiconductor die in a subsequent process step (see Fig. 22 In some embodiments, the semiconductor die is a memory die, such as a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, a flash memory die, or may be another type of die. In some embodiments, the semiconductor die includes a logic die, which may be a central processing unit (CPU) die, a micro control unit (MCU) die, an input-output (IO) die, a baseband (BB) die, and an application processor (AP), etc.

[0134] This further process may also include bonding the two semiconductor dies. The bonding operation may be performed by a bonding step. This further process may also include forming an under-bump metallurgy.

[0135] (under-bμmp metallurgies, UBM). In some embodiments, each UBM includes a barrier layer (not shown) and a seed layer (not shown) above the barrier layer. The barrier layer can be a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or a layer formed of a titanium alloy or a tantalum alloy. The material of the seed layer may include copper or a copper alloy. The UBM may also contain other metals, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, and combinations thereof. This further process may also include bonding the workpiece to a substrate, which may be a printed circuit board (PCB), a substrate of another semiconductor die, an interposer die, or a substrate of other suitable devices.

[0136] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and their formation. For example, the present disclosure provides methods for forming bonding structures above conductive pads formed by ECP, even when the conductive pads formed by ECP have different configurations and have non-coplanar top surfaces. The resulting semiconductor structure provides satisfactory electrical connections between the bonding structures and those conductive pads. In addition, the conductive pads are not over-etched during the formation process of the bonding structures. In this way, the yield and reliability of the semiconductor structure can be advantageously improved.

[0137] The present disclosure provides many different embodiments. Semiconductor structures and methods for manufacturing the same are provided herein. In one exemplary embodiment, the present disclosure relates to a method. The method includes providing a workpiece having a first conductive pad above a first region of a substrate and a second conductive pad above a second region of the substrate, wherein a portion of the first conductive pad disposed directly above the substrate has a first height, and the second conductive pad has a second height greater than the first height, conformally forming a first etch stop layer on the first conductive pad and the second conductive pad, forming a dielectric structure above the first etch stop layer, performing a planarization process on the dielectric layer, and after completing the planarization process, conformally depositing a dielectric layer above the workpiece, the dielectric layer including a first portion disposed directly above the first conductive pad and a second portion disposed directly above the second conductive pad. The difference in thickness between a first thickness of the first portion of the dielectric layer and a second thickness of the second portion of the dielectric layer is less than the difference in height between the first height and the second height.

[0138] In some embodiments, the first region of the substrate includes a metal-insulator-metal capacitor embedded in a passivation structure. The first conductive pad includes a top portion formed directly above the passivation structure and having a first height. The first conductive pad also includes a bottom portion extending into the passivation structure, which is physically and electrically coupled to a conductor plate of the metal-insulator-metal capacitor. The entire second conductive pad is located directly above the passivation structure. In some embodiments, each of the first conductive pad and the second conductive pad includes a seed layer and a metal fill layer located on the seed layer. The metal fill layer includes copper (Cu). In some embodiments, the method also includes conformally forming a second etch stop layer above the workpiece, forming an oxide layer above the second etch stop layer, flattening the oxide layer until the oxide layer has a substantially flat top surface above the second etch stop layer, forming a third etch stop layer on the flat oxide layer, and forming a bonding film on the third etch stop layer. The thickness of the second etch stop layer is greater than the thickness of the first etch stop layer. In some embodiments, the ratio of the thickness of the second etch stop layer to the thickness of the first etch stop layer is between about 2 and about 10. In some embodiments, the method further includes performing a first etching process on the workpiece to form a first opening in the first region and a second opening in the second region, the first opening and the second opening exposing a third etch stop layer, performing a second etching process on the workpiece to vertically extend the first opening and the second opening, the extended first opening and the second opening exposing the second etch stop layer, wherein the depth of the extended portion of the extended first opening is greater than the depth of the extended portion of the extended second opening, performing a third etching process on the workpiece to further vertically extend the extended first opening and the second opening to expose the first conductive pad and the second conductive pad, respectively, and forming the first bonding pad and the second bonding pad in the further extended first opening and the second opening, respectively. In some cases, the composition of the first etch stop layer is the same as the composition of the second etch stop layer. In some embodiments, the top surface of the second etch stop layer includes a dished surface profile. In some cases, the ratio of the height difference to the thickness difference is greater than 20.

[0139] In another exemplary embodiment, the present disclosure is directed to a method. The method includes forming a first conductive component over a first region of a substrate and forming a second conductive component over a second region of the substrate, wherein a peak of a top surface of the second conductive component is above a peak of a top surface of the second conductive component, conformally depositing a first etch stop layer over the substrate, conformally depositing a dielectric layer over the first etch stop layer, conformally depositing a second etch stop layer over the dielectric layer, wherein the second etch stop layer includes a non-planar top surface, forming a multilayer dielectric structure over the second etch stop layer, wherein the multilayer dielectric structure includes a substantially planar top surface and a non-planar bottom surface, and forming a first bonding pad and a second bonding pad extending through the multilayer dielectric structure, the second etch stop layer, the dielectric layer, and the first etch stop layer to physically and electrically couple to the first conductive component and the second conductive component, respectively.

[0140] In some embodiments, the method further comprises, after conformally depositing the first etch stop layer over the substrate, forming a hybrid dielectric structure over the first etch stop layer, and performing a planarization process on the hybrid dielectric structure, wherein, after performing the planarization process, the hybrid dielectric structure comprises a non-planar top surface. Conformally depositing the dielectric layer over the first etch stop layer is performed after performing the planarization process. In some embodiments, the substrate comprises a metal-insulator-metal capacitor in a first region of the substrate, and the steps of forming the first and second conductive components comprise forming a passivation film over the metal-insulator-metal capacitor and the substrate, forming a via opening extending through the passivation film and exposing a corresponding conductor plate of the metal-insulator-metal capacitor, and performing an electrochemical plating process (ECP) to form a first conductive component in and over the via opening, and forming a second conductive component over the via opening and over the passivation film. In some embodiments, each of the first conductive component and the second conductive component comprises a seed layer and a metal fill layer on the seed layer, wherein the metal fill layer comprises copper (Cu). In some embodiments, the thickness of the second etch stop layer is greater than the thickness of the first etch stop layer. In some cases, the first bond pad extends into the first conductive component to a first depth, and the second bond pad extends into the second conductive component to a second depth substantially equal to the first depth. In some cases, the multilayer dielectric structure includes a non-planar bottom surface.

[0141] In yet another exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first conductive component formed above a substrate, a second conductive component formed above the substrate, and the highest point of the top surface of the second conductive component is above the highest point of the top surface of the first conductive component, a first conformal dielectric layer is above the first conductive component and the second conductive component, and a conformal oxide layer is above the first conformal dielectric layer. The conformal oxide layer includes a first portion disposed directly above the first conductive component and a second portion disposed directly above the second conductive component. The thickness of the first portion is substantially equal to the thickness of the second portion. The semiconductor structure also includes a second conformal dielectric layer located on the conformal oxide layer and including a non-planar top surface, a multilayer dielectric structure located on the second conformal dielectric layer and having a substantially flat top surface, a first bonding structure located on the first conductive component and electrically coupled to the first conductive component, and a second bonding structure located on the second conductive component and electrically coupled to the second conductive component.

[0142] In some embodiments, the second conformal dielectric layer has a thickness greater than a thickness of the first conformal dielectric layer. In some implementations, a top surface of the second conformal dielectric layer includes a dished surface profile. In some cases, the first conductive component and the second conductive component include copper.

[0143] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first conductive component formed on a substrate; A second conductive component is formed on the substrate, and a highest point of a top surface of the second conductive component is higher than a highest point of a top surface of the first conductive component; a first conformal dielectric layer disposed over the first conductive component and the second conductive component; a conformal oxide layer over the first conformal dielectric layer, wherein the conformal oxide layer comprises a first portion disposed directly over the first conductive component and a second portion disposed over the second conductive component, wherein a thickness of the first portion is equal to a thickness of the second portion; a second conformal dielectric layer disposed on the conformal oxide layer, wherein the second conformal dielectric layer includes a non-planar top surface; a multi-layer dielectric structure disposed on the second conformal dielectric layer and having a flat top surface; a first bonding structure located on the first conductive component and electrically coupled to the first conductive component; as well as A second bonding structure is located on the second conductive component and electrically coupled to the second conductive component.

2. The semiconductor device according to claim 1, wherein A thickness of the second conformal dielectric layer is greater than a thickness of the first conformal dielectric layer.

3. The semiconductor device according to claim 1, wherein: A top surface of the second conformal dielectric layer includes a profile of a dished surface.

4. The semiconductor device according to claim 1 or 2, wherein: The multi-layer dielectric structure includes a non-planar bottom surface.

5. The semiconductor device according to claim 1, wherein: The first conductive component is spaced apart from another first conductive component adjacent to the first conductive component by a distance, wherein the distance is between 3 μm and 10 μm.

6. The semiconductor device according to claim 1, wherein: The width of the second conductive component is greater than the width of the first conductive component.

7. The semiconductor device according to claim 1, wherein The first conductive component and the second conductive component have a convex top surface that is bent inwardly.

8. The semiconductor device according to claim 1, wherein The multilayer dielectric structure includes a first dielectric layer, wherein the first dielectric layer includes a first portion disposed directly above the first conductive component and a second portion disposed above the second conductive component, wherein a thickness of the first portion is greater than a thickness of the second portion.

9. The semiconductor device according to claim 8, wherein: A thickness difference between the first portion and the second portion of the first dielectric layer is equal to a height difference between the highest point of the top surface of the second conductive component and the highest point of the top surface of the first conductive component.

10. The semiconductor device according to claim 8, wherein The first dielectric layer has a flat top surface.

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