Chip test socket S parameter test structure
By designing the chip test socket S parameter test structure, using the electrical connection and clamping method of the connector and the sandwich plate to solve the problem of the chip test socket manufacturer difficulty to provide the S parameter, and realize the accurate measurement of the chip test socket S parameter.
Patent Information
- Application Number
- CN202420903093.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-28
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2034-04-28
AI Technical Summary
Existing chip test socket manufacturers have difficulty providing the S parameters of chip test sockets, which makes it impossible to achieve accurate chip testing.
A chip test socket S parameter test structure is designed, including the first connector, the first clamping board, the second connector, and the second clamping board. Through the electrical connection and clamp structure of these components Testing system of chip test socket S parameter.
The accurate measurement of the chip test socket S parameter is implemented. Through vector network analyzer and the principle of direct calibration, it can be decomposed and to embed S parameters, thereby improving the accuracy and reliability of the test.
Smart Images
Figure CN222420316U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip testing, in particular to an S parameter testing structure of a chip testing socket. Background Art
[0002] The chip test socket is a connector socket that connects the chip to the PCB board. Its main function is to meet the connection requirements between the chip pin terminal and the PCB test mainboard. The biggest advantage is that the chip can be replaced at any time during the chip test without damaging the chip and PCB, thereby achieving fast and efficient testing. It has the characteristics of simple operation, accurate fault location, convenience and speed, and high test yield.
[0003] S parameters are a tool for describing the electrical behavior of components under the stimulation of high-frequency signals with RF characteristics. They are described by the measurable physical quantity "scattered" from the outside of the component after the component "reacts" or "scatters" to the incident signal. The size of the measured physical quantity reflects that components with different characteristics will "scatter" the same input signal to different degrees. This different degree of scattering can be used to describe the characteristics of the component, and this expression has become a very useful electrical model. These physical quantities are called incident voltage, reflected voltage, transmission voltage, etc. Many passive devices such as cables, connectors, PCB traces and other transmission media will exhibit this characteristic, so they can all be characterized by S parameters.
[0004] Currently, many chip design manufacturers in the market need high-speed chip test sockets, and require chip test socket manufacturers to provide measured S parameters of the chip test sockets. However, chip test socket manufacturers generally cannot provide S parameters due to technical reasons or will not provide S parameters due to cost reasons. Therefore, a chip test socket S parameter test structure is needed to accurately measure the S parameters of the chip test socket. Utility Model Content
[0005] The utility model aims to provide a chip test socket S parameter test structure, which can accurately measure the S parameters of the chip test socket.
[0006] To achieve this purpose, the utility model adopts the following technical solutions:
[0007] Chip test socket S parameter test structure, including:
[0008] a first connector;
[0009] A first clamping plate abutting against the first connector;
[0010] a second connector;
[0011] A second clamping plate abutting against the second connector;
[0012] A side of the first clamping plate away from the first connector and a side of the second clamping plate away from the second connector are clamped together on opposite sides of the chip test socket and the first clamping plate, the chip test socket and the second clamping plate are electrically connected in sequence, or a side of the first clamping plate away from the first connector and a side of the second clamping plate away from the second connector are abutted and electrically connected.
[0013] As a preferred solution, the chip test socket S parameter test structure further includes:
[0014] A positioning member, wherein the first connector, the second connector, the first clamping plate, the second clamping plate and the chip test socket are all provided with positioning holes, and the positioning member is inserted into the positioning holes.
[0015] As a preferred solution, the chip test socket S parameter test structure further includes:
[0016] The first fixing member can detachably connect the first connector, the first clamping plate and the chip test socket.
[0017] As a preferred solution, the chip test socket S parameter test structure further includes:
[0018] The second fixing member, the first fixing member passes through the first connector, the first clamping plate, the second clamping plate and the second connector in sequence, and the first fixing member is threadedly connected with the second fixing member.
[0019] As a preferred solution, the first fixing member can detachably connect the second connector, the second clamping plate and the chip test socket.
[0020] As a preferred solution, the first clamping plate and the second clamping plate are made of aluminum.
[0021] As a preferred solution, the first clamping plate comprises:
[0022] The first connector includes an insulating layer, the insulating layer abuts against the connecting portion, and a diameter D1 of the insulating layer is greater than an outer diameter D2 of the connecting portion.
[0023] As a preferred solution, the first clamping plate further comprises:
[0024] The conductive layer, the insulating layer is arranged around the outer periphery of the conductive layer, the conductive layer is in contact with the connecting portion, and the diameter d1 of the conductive layer is smaller than the inner diameter d2 of the connecting portion.
[0025] As a preferred solution, the chip test socket S parameter test structure further includes:
[0026] The chip test socket is provided with a countersunk hole and a receiving hole connected to each other, the signal pin is received in the receiving hole and the countersunk hole, and the countersunk hole is located at one end of the receiving hole close to the first clamping plate.
[0027] As a preferred solution, the signal needle abuts against the conductive layer, and a diameter d3 of the signal needle is smaller than a diameter d1 of the conductive layer.
[0028] Beneficial effects of the utility model:
[0029] The utility model provides an S parameter test structure of a chip test socket. When testing the S parameter test structure of the chip test socket, a first clamping plate is connected to a first connector, and a second clamping plate is connected to a second connector. Then, a side of the first clamping plate away from the first connector and a side of the second clamping plate away from the second connector are clamped together on two opposite sides of the chip test socket, and the first clamping plate, the chip test socket and the second clamping plate are electrically connected in sequence, and then the S parameters of the overall structure are measured by a vector network analyzer; then, a side of the first clamping plate away from the first connector and a side of the second clamping plate away from the second connector are abutted and electrically connected, thereby constructing a through calibration piece, and the S parameters of the through calibration piece are measured by a vector network analyzer, and then the S parameters of the through calibration piece are decomposed into symmetrical S left and S right by using the through calibration principle, and finally the S left, S right and the S parameters of the overall structure are imported into Circuit software for de-embedding, thereby accurately measuring the S parameters of the chip test socket. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a structural schematic diagram of the S parameter test structure of the chip test socket provided by the embodiment of the utility model;
[0031] Figure 2 This is a cross-sectional view of the S parameter test structure of the chip test socket provided by the embodiment of the utility model Figure 1 ;
[0032] Figure 3 This is a cross-sectional view of the S parameter test structure of the chip test socket provided by the embodiment of the utility model Figure 2 ;
[0033] Figure 4 yes Figure 2 Enlarged view of point A in the middle.
[0034] In the figure:
[0035] 100, chip test socket; 101, countersunk hole; 102, receiving hole;
[0036] 10. First connector; 11. Connecting portion; 20. First clamping plate; 21. Insulating layer; 22. Conductive layer; 30. Second connector; 40. Second clamping plate; 50. Positioning member; 60. First fixing member; 70. Second fixing member; 80. Signal pin. DETAILED DESCRIPTION
[0037] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0038] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0039] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0040] In the description of this embodiment, the terms "upper", "lower", "right", etc., are based on the directions or positions shown in the drawings, and are only for the convenience of description and simplified operation, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.
[0041] like Figure 1 and Figure 2As shown, the utility model provides a chip test socket S parameter test structure, which includes a first connector 10, a first clamping plate 20, a second connector 30 and a second clamping plate 40, the first clamping plate 20 abuts against the first connector 10, and the second clamping plate 40 abuts against the second connector 30; the side of the first clamping plate 20 away from the first connector 10 and the side of the second clamping plate 40 away from the second connector 30 are clamped together on the opposite sides of the chip test socket 100 and the first clamping plate 20, the chip test socket 100 and the second clamping plate 40 are electrically connected in sequence, or, the side of the first clamping plate 20 away from the first connector 10 abuts against and is electrically connected to the side of the second clamping plate 40 away from the second connector 30.
[0042] like Figure 1 and Figure 2 As shown, when the chip test socket S parameter test structure is tested, the first clamping plate 20 abuts against the first connector 10, and the second clamping plate 40 abuts against the second connector 30, and then the side of the first clamping plate 20 away from the first connector 10 and the side of the second clamping plate 40 away from the second connector 30 are clamped together on the opposite sides of the chip test socket 100, and the first clamping plate 20, the chip test socket 100 and the second clamping plate 40 are electrically connected in sequence, and then the S parameters of the overall structure are measured by a vector network analyzer; then the side of the first clamping plate 20 away from the first connector 10 and the side of the second clamping plate 40 away from the second connector 30 are abutted and electrically connected, thereby constructing a straight-through calibration piece, and the S parameters of the straight-through calibration piece are measured using a vector network analyzer, and then the S parameters of the straight-through calibration piece are decomposed into symmetrical S left and S right by using the straight-through calibration principle, and finally the S left, S right and the S parameters of the overall structure are imported into the Circuit software for de-embedding, thereby accurately measuring the S parameters of the chip test socket 100.
[0043] like Figure 1 and Figure 2 As shown, the chip test socket S parameter test structure also includes a positioning member 50, and the first connector 10, the second connector 30, the first clamping plate 20, the second clamping plate 40 and the chip test socket 100 are all provided with positioning holes, and the positioning member 50 is inserted into the positioning hole. When the first connector 10 is abutted against the first clamping plate 20, the second connector 30 is abutted against the second clamping plate 40, the first clamping plate 20 is abutted against the second clamping plate 40, the first clamping plate 20 is abutted against the chip test socket 100, and the second clamping plate 40 is abutted against the chip test socket 100, the positioning member 50 and the positioning hole cooperate with each other to play a positioning role, thereby ensuring accurate positioning during abutment, so that the final test result is accurate. In this embodiment, the positioning member 50 is a pin, and the pin has a simple structure and low cost. In other embodiments, the positioning member 50 can also be a structure with a simple structure and low cost, such as a pin shaft, which is not limited in this embodiment.
[0044] like Figure 1 and Figure 2 As shown, the chip test socket S parameter test structure also includes a first fixing member 60, which can detachably connect the first connector 10, the first clamping plate 20 and the chip test socket 100. Therefore, when measuring the S parameters of the overall structure, the abutment between the first connector 10, the first clamping plate 20 and the chip test socket 100 is more firm, and relative displacement will not occur, and the test result is more accurate. In this embodiment, the first fixing member 60 is a bolt, and the chip test socket 100 is provided with a threaded hole, and the bolt is threadedly connected to the threaded hole, which has a simple structure and is easy to operate.
[0045] In addition, if Figure 2 As shown, the first fixing member 60 can detachably connect the second connector 30, the second clamping plate 40 and the chip test socket 100. The principle and structure thereof are consistent with those described above and will not be described in detail in this embodiment.
[0046] like Figure 3 As shown, the chip test socket S parameter test structure also includes a second fixing member 70, the first fixing member 60 passes through the first connector 10, the first clamping plate 20, the second clamping plate 40 and the second connector 30 in sequence, and the first fixing member 60 is threadedly connected with the second fixing member 70. Therefore, when measuring the S parameters of the straight-through calibration component, after the first connector 10, the first clamping plate 20, the second clamping plate 40 and the second connector 30 are abutted, the first fixing member 60 and the second fixing member 70 fix the first connector 10, the first clamping plate 20, the second clamping plate 40 and the second connector 30 together, thereby avoiding relative displacement and ensuring the accuracy of the measurement result. In this embodiment, the second fixing member 70 is a nut, and the structure of the bolt and the nut is simple and low in cost.
[0047] like Figure 2 and Figure 4 As shown, the first clamping plate 20 includes an insulating layer 21, and the first connector 10 includes a connecting portion 11. The insulating layer 21 abuts against the connecting portion 11, and a diameter D1 of the insulating layer 21 is larger than an outer diameter D2 of the connecting portion 11, thereby ensuring that the first clamping plate 20 and the connecting portion 11 can be stably electrically connected.
[0048] like Figure 2 and Figure 4 As shown, the first clamping plate 20 also includes a conductive layer 22, and the insulating layer 21 is arranged around the outer periphery of the conductive layer 22. The conductive layer 22 abuts against the connecting portion 11, and the diameter d1 of the conductive layer 22 is smaller than the inner diameter d2 of the connecting portion 11, thereby ensuring that the first clamping plate 20 and the connecting portion 11 can be stably electrically connected.
[0049] like Figure 2 and Figure 4As shown, the chip test socket S parameter test structure also includes a signal pin 80. The chip test socket 100 is provided with a connected countersunk hole 101 and a receiving hole 102. The signal pin 80 is received in the receiving hole 102 and the countersunk hole 101. The countersunk hole 101 is located at one end of the receiving hole 102 close to the first clamping plate 20. The setting of the countersunk hole 101 can improve the measurement accuracy of the S parameters of the overall structure.
[0050] like Figure 2 and Figure 4 As shown, the signal pin 80 abuts against the conductive layer 22 , and the diameter d3 of the signal pin 80 is smaller than the diameter d1 of the conductive layer 22 , thereby ensuring that the first clamping plate 20 and the chip test socket 100 can be stably electrically connected.
[0051] like Figure 1 As shown, the chip test socket 100 , the first clamping plate 20 and the second clamping plate 40 are all made of aluminum, so the measurement performance is good.
[0052] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, various obvious changes, readjustments and substitutions can be made without departing from the scope of protection of the present invention. It is not necessary and impossible to list all implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the scope of protection of the claims of the present invention.
Claims
1. Chip test socket S parameter test structure, characterized in that: include: A first connector (10); A first clamping plate (20) abutting against the first connector (10); A second connector (30); A second clamping plate (40) abutting against the second connector (30); The side of the first clamping plate (20) away from the first connector (10) and the side of the second clamping plate (40) away from the second connector (30) are clamped together on opposite sides of the chip test socket (100), and the first clamping plate (20), the chip test socket (100) and the second clamping plate (40) are electrically connected in sequence, or the side of the first clamping plate (20) away from the first connector (10) and the side of the second clamping plate (40) away from the second connector (30) are abutted and electrically connected.
2. The chip test socket S parameter test structure according to claim 1, characterized in that: The chip test socket S parameter test structure also includes: A positioning member (50), the first connector (10), the second connector (30), the first clamping plate (20), the second clamping plate (40) and the chip test socket (100) are all provided with positioning holes, and the positioning member (50) is inserted into the positioning holes.
3. The chip test socket S parameter test structure according to claim 1, characterized in that: The chip test socket S parameter test structure also includes: The first fixing member (60) can detachably connect the first connector (10), the first clamping plate (20) and the chip test socket (100).
4. The chip test socket S parameter test structure according to claim 3, characterized in that: The chip test socket S parameter test structure also includes: A second fixing member (70), wherein the first fixing member (60) passes through the first connector (10), the first clamping plate (20), the second clamping plate (40) and the second connector (30) in sequence, and the first fixing member (60) is threadedly connected to the second fixing member (70).
5. The chip test socket S parameter test structure according to claim 3, characterized in that: The first fixing member (60) can detachably connect the second connector (30), the second clamping plate (40) and the chip test socket (100).
6. The chip test socket S parameter test structure according to any one of claims 1 to 5, characterized in that: The first clamping plate (20) and the second clamping plate (40) are made of aluminum.
7. The chip test socket S parameter test structure according to claim 1, characterized in that: The first clamping plate (20) comprises: An insulating layer (21), the first connector (10) comprises a connecting portion (11), the insulating layer (21) abuts against the connecting portion (11), and a diameter D1 of the insulating layer (21) is greater than an outer diameter D2 of the connecting portion (11).
8. The chip test socket S parameter test structure according to claim 7, characterized in that: The first clamping plate (20) further comprises: A conductive layer (22), wherein the insulating layer (21) is arranged around the outer periphery of the conductive layer (22), the conductive layer (22) abuts against the connecting portion (11), and a diameter d1 of the conductive layer (22) is smaller than an inner diameter d2 of the connecting portion (11).
9. The chip test socket S parameter test structure according to claim 8, characterized in that: The chip test socket S parameter test structure also includes: The chip test socket (100) is provided with a countersunk hole (101) and a receiving hole (102) which are connected to each other. The signal pin (80) is received in the receiving hole (102) and the countersunk hole (101). The countersunk hole (101) is located at one end of the receiving hole (102) close to the first clamping plate (20).
10. The chip test socket S parameter test structure according to claim 9, characterized in that: The signal needle (80) abuts against the conductive layer (22), and a diameter d3 of the signal needle (80) is smaller than a diameter d1 of the conductive layer (22).