Charge pump circuit, chip and electronic equipment
By transferring the charge of parasitic capacitors during the dead area of the charge pump circuit, the problem of large switching loss during the charging process is solved, and the effect of reducing switching loss and improving energy conversion rates is achieved.
Patent Information
- Application Number
- CN202420178786.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-24
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2034-01-24
AI Technical Summary
During the charging process of the charge pump circuit, frequent switching operations increase switching losses and affect efficiency.
A charge pump circuit is designed, including the branch of the first charge pump, the branch of the second charge pump, and the charge transfer control branch. During the dead zone of the first work mode or the second working mode, the charge of the parasitic capacitor storage of the second target switch was transferred to the parasitic capacitor of the first target switch through the charge transfer control branch, and part of the charge was transferred to the specified output terminal Essence
By transferring the charge of the parasite capacitor, the charging requirements of the switching device within the next control cycle are reduced, the switching loss is reduced, and the energy conversion rate of the charge pump circuit is increased.
Smart Images
Figure CN222423515U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of control technology, and in particular to a charge pump circuit, a chip and an electronic device. Background Art
[0002] As electronic devices are equipped with more and more power loads, the capacity of their batteries is getting larger and larger. For this reason, in the related art, a charge pump circuit is provided in the electronic devices to charge the batteries.
[0003] For example, in the first stage, the charge pump circuit controls multiple capacitors to be connected in series, and uses high voltage and low current to charge the capacitors; in the second stage, the charge pump circuit controls multiple capacitors to be connected in parallel, and uses low voltage and high current to charge the battery, so as to achieve the effect of fast charging. Based on the above working process analysis, during the charging process, the charge pump circuit needs to frequently turn on or off the switch device, thereby increasing the switching loss. Utility Model Content
[0004] The present disclosure provides a charge pump circuit, a chip and an electronic device to solve the above technical problems.
[0005] According to a first aspect of the present disclosure, there is provided a charge pump circuit, comprising: a first charge pump branch, a second charge pump branch and a charge transfer control branch; the charge transfer control branch is electrically connected to the first charge pump branch and the second charge pump branch respectively, and the charge transfer control branch is electrically connected to a designated output terminal;
[0006] The charge transfer control branch is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another portion of the charge to a load electrically connected to the designated output terminal during a dead period in the first operating mode or the second operating mode;
[0007] The dead zone period refers to the period during which the switching devices in the first charge pump branch and the second charge pump branch are both in the off state, the first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.
[0008] Optionally, the first charge pump branch includes a first sub-branch and a second sub-branch electrically connected; the second charge pump branch includes a third sub-branch and a fourth sub-branch electrically connected; the first sub-branch is electrically connected to the fourth sub-branch, and the second sub-branch is electrically connected to the third sub-branch; the charge transfer control branch includes a first transfer control sub-branch;
[0009] The first transfer control sub-branch is electrically connected to the first sub-branch, the third sub-branch and the designated output terminal of the charge pump circuit, respectively, and is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another part of the charge to a load electrically connected to the designated output terminal during the dead zone of the first operating mode.
[0010] Optionally, the first sub-branch includes a first switch device, a fourth switch device and a sixth switch device; the first transfer control sub-branch includes a first inductor;
[0011] The first end of the first switch device is electrically connected to the input end of the charge pump circuit, and the second end of the first switch device is electrically connected to the first end of the fourth switch device; the second end of the fourth switch device is electrically connected to the first end of the sixth switch device, and the second end of the sixth switch device is electrically connected to the fourth sub-branch;
[0012] The third sub-branch includes a second switch device, a third switch device and a fifth switch device; a first end of the second switch device is electrically connected to an input end of the charge pump circuit, a second end of the second switch device is electrically connected to a first end of the third switch device; a second end of the third switch device is electrically connected to a first end of the fifth switch device, and a second end of the fifth switch device is electrically connected to the second sub-branch;
[0013] In one of the first sub-phase and the second sub-phase during the dead zone, the first end of the first inductor is electrically connected to the second end of the first switching device, and the second end of the first inductor is electrically connected to the designated output end; in another sub-phase during the dead zone, the first end of the first inductor is electrically connected to the designated output end, and the second end of the first inductor is electrically connected to the second end of the second switching device.
[0014] Optionally, the first transfer control sub-branch includes a first transfer control switch and a second transfer control switch; the first end of the first transfer control switch is electrically connected to the second end of the first switch device, and the second end of the first transfer control switch is electrically connected to the first end of the first inductor; the second end of the first inductor is electrically connected to the first end of the second transfer control switch, and the second end of the second transfer control switch is electrically connected to the designated output end; the control ends of the first transfer control switch and the second transfer control switch are used to receive control signals;
[0015] The first transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the first end of the first inductor to the second end of the first switching device;
[0016] The second transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the second end of the first inductor to the designated output end.
[0017] Optionally, the first transfer control sub-branch further includes a third transfer control switch and a fourth transfer control switch; a first end of the third transfer control switch is electrically connected to the second end of the first inductor, and a second end of the third transfer control switch is electrically connected to the second end of the second switch device; a first end of the fourth transfer control switch is electrically connected to the first end of the first inductor, and a second end of the fourth transfer control switch is electrically connected to the designated output end;
[0018] The third transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the second end of the first inductor to the second end of the second switch device;
[0019] The fourth transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the first end of the first inductor to the designated output end.
[0020] Optionally, the designated output terminal includes a first output terminal, and the first output terminal is electrically connected to the second terminal of the fourth switching device and the second terminal of the third switching device respectively.
[0021] Optionally, the fourth sub-branch includes a thirteenth switching device, a fourteenth switching device and a fifteenth switching device; a first end of the thirteenth switching device is electrically connected to the first sub-branch, a second end of the thirteenth switching device is electrically connected to a first end of the fourteenth switching device, a first end of the fifteenth switching device is electrically connected to a second end of the fourteenth switching device, and a second end of the fifteenth switching device is grounded;
[0022] The second sub-branch includes an eleventh switching device, a twelfth switching device, and a sixteenth switching device; the first end of the twelfth switching device is electrically connected to the third sub-branch, the second end of the twelfth switching device is electrically connected to the first end of the eleventh switching device, the first end of the sixteenth switching device is electrically connected to the second end of the eleventh switching device, and the second end of the sixteenth switching device is grounded.
[0023] Optionally, the designated output terminal includes a second output terminal, and the second output terminal is electrically connected to the second terminal of the thirteenth switching device and the second terminal of the twelfth switching device respectively.
[0024] Optionally, the designated output terminal includes a third output terminal, and the third output terminal is electrically connected to the second terminal of the eleventh switching device and the second terminal of the fourteenth switching device respectively.
[0025] Optionally, the first inductance value of the first inductor is less than a target inductance value, and the target inductance value refers to an inductance value that matches the parasitic capacitance resonance of the switching device in the first charge pump branch and / or the second charge pump branch at the switching frequency of the two charge pump branches in the charge pump circuit.
[0026] According to a second aspect of the present disclosure, a chip is provided, comprising a charge pump circuit as described in any one of the first aspects.
[0027] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor, a battery, a charging interface, and a charge pump circuit as described in any one of the first aspects; the charge pump circuit is electrically connected to the battery and the charging interface respectively; the processor is electrically connected to the charge pump circuit;
[0028] The processor is used to control the first target switch of the first charge pump branch and the second target switch of the second charge pump branch to switch to the on state and the off state in one control cycle;
[0029] The processor is used to switch the charge pump circuit to one of the first working mode or the second working mode, and control all the switch devices of the first charge pump branch and the second charge pump branch to switch to the disconnected state during the dead period of the working mode;
[0030] The processor is further configured to output a control signal to a charge transfer control branch of the charge pump circuit during a dead period of the operating mode;
[0031] The charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch and another part of the charge to the load electrically connected to the designated output terminal when receiving a control signal during the dead time period of the working mode;
[0032] and / or,
[0033] A processor, a battery, a charging interface and the chip as described in the second aspect; the chip is electrically connected to the battery, the charging interface and the processor respectively;
[0034] The processor is used to control the first target switch of the charge pump circuit in the chip to switch to the on state and the second target switch to switch to the off state within a control cycle;
[0035] The processor is used to switch the charge pump circuit to one of the first working mode or the second working mode, and control all the switch devices of the first charge pump branch and the second charge pump branch to switch to the disconnected state during the dead period of the working mode;
[0036] The processor is further configured to output a control signal to a charge transfer control branch of the charge pump circuit during a dead period of the operating mode;
[0037] The charge transfer control branch is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch and another portion of the charge to a load electrically connected to the designated output terminal when a control signal is received during the dead zone of the working mode.
[0038] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:
[0039] The charge pump circuit provided in this embodiment includes a first charge pump branch, a second charge pump branch and a charge transfer control branch; the charge transfer control branch is electrically connected to the first charge pump branch and the second charge pump branch respectively, and the charge transfer control branch is electrically connected to the designated output terminal; the charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another part of the charge to the load electrically connected to the designated output terminal during the dead period in the first working mode or the second working mode; the dead period refers to the period during which the switch devices in the first charge pump branch and the second charge pump branch are both in the off state, the first target switch refers to the switch device in the on state in the previous control cycle, and the second target switch refers to the switch device in the off state in the previous control cycle. In this way, in this embodiment, by transferring part of the charge of the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch in the first working mode and the second working mode, the first target switch can be used as the second target switch in the next control cycle, that is, when the first target switch is switched to the off state, the parasitic capacitance stores charge and does not need to be charged, thereby achieving the effect of reducing switching loss. Furthermore, in this embodiment, another part of the charge of the parasitic capacitor can be transferred to the load or the charge can be absorbed from the load, thereby ensuring a zero voltage switching condition, reducing switching losses, and improving the energy conversion rate of the charge pump circuit.
[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 The present invention is a block diagram of an electronic device according to an embodiment of the present invention.
[0042] Figure 2 The block diagram is a charge pump circuit according to an embodiment of the present disclosure.
[0043] Figure 3 The block diagram is a charge pump circuit according to an embodiment of the present disclosure.
[0044] Figure 4 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0045] Figure 5 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0046] Figure 6 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0047] Figure 7 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0048] Figure 8 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0049] Fig. 9 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0050] Fig.10 FIG. 4 is a circuit diagram of another charge pump circuit according to an embodiment of the present disclosure.
[0051] Fig.11 The present invention is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.
[0053] In order to solve the above technical problems, the embodiments of the present disclosure provide a charge pump circuit, a chip and an electronic device. Figure 1 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Figure 1 An electronic device 10 includes a processor 11, a battery 14, a charging interface 12, and a charge pump circuit 13. The charge pump circuit 13 is electrically connected to the battery 14 and the charging interface 12 respectively; the processor 11 is electrically connected to the charge pump circuit 13.
[0054] In one example, the charging interface 12 may include, but is not limited to, a USB Type-C interface, a MicroUSB, etc. If it can support charging of the charge pump circuit 13, the corresponding charging interface falls within the protection scope of the present disclosure.
[0055] In one example, see Figure 2 The charge pump circuit 13 includes a first charge pump branch 21, a second charge pump branch 22 and a charge transfer control branch 23. The charge transfer control branch 23 is electrically connected to the first charge pump branch 21 and the second charge pump branch 22, respectively, and the charge transfer control branch 23 is electrically connected to a designated output terminal. The designated output terminal refers to one of the first output terminal, the second output terminal or the third output terminal. Each output terminal will be described later, and will not be described here.
[0056] The charge transfer control branch 23 is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another part of the charge to the load electrically connected to the designated output terminal during the dead time period in the first working mode or the second working mode;
[0057] The above-mentioned dead zone period refers to the period when the switching devices in the first charge pump branch 21 and the second charge pump branch 22 are both in the off state, the first target switch refers to the switching device that is in the on state in the previous control cycle, and the second target switch refers to the switching device that is in the off state in the previous control cycle.
[0058] In one example, see Figure 2 and Figure 3 , the first charge pump branch 21 includes a first sub-branch 211 and a second sub-branch 212 that are electrically connected; the second charge pump branch 22 includes a third sub-branch 221 and a fourth sub-branch 222 that are electrically connected; the first sub-branch 211 and the fourth sub-branch 222 are electrically connected, and the second sub-branch 212 is electrically connected to the third sub-branch 221. It can be understood that the first charge pump branch 21 and the second charge pump branch 22 form a cross-charging architecture, that is, the first charge pump branch 21 and the second charge pump branch 22 form a cross-charging architecture with respect to the first line where the power source BAT is located.
[0059] In this example, see Figure 3 The charge transfer control branch 23 includes a first transfer control sub-branch 231. The first transfer control sub-branch 231 is electrically connected to the first sub-branch 211, the third sub-branch 221 and the designated output terminal of the charge pump circuit, respectively, and is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another part of the charge to a load electrically connected to the designated output terminal during the dead time of the first working mode of the charge pump circuit.
[0060] It should be noted that the dead zone period refers to the period when the switching devices in the first charge pump branch 21 and the second charge pump branch 22 are in the off state, the first target switch refers to the switching device that is in the on state in the previous control cycle, and the second target switch refers to the switching device that is in the off state in the previous control cycle.
[0061] It should also be noted that the charge pump circuit in this example includes two working modes, such as the first working mode and the second working mode. The first working mode may refer to a 4:1 charging mode, for example, if the input voltage is 20V and the input current is 5A, the output voltage is 5V and the output current is 20A; the second working mode refers to a 2:1 charging mode, for example, if the input voltage is 10V and the input current is 5A, the output voltage is 5V and the output current is 10A. It is understandable that the working mode can be adjusted according to the specific charging architecture, and the corresponding scheme falls within the protection scope of this disclosure.
[0062] Continue to see Figure 3 The first sub-branch 211 includes a first switch device Q1, a fourth switch device Q4, and a sixth switch device Q6. The first end of the first switch device Q1 is electrically connected to the input end of the charge pump circuit (the input end is connected to the power supply BAT), and the second end of the first switch device Q1 is electrically connected to the first end of the fourth switch device Q4; the second end of the fourth switch device Q4 is electrically connected to the first end of the sixth switch device Q6, and the second end of the sixth switch device Q6 is electrically connected to the fourth sub-branch 222.
[0063] Continue to see Figure 3 The second sub-branch 212 includes a first capacitor C1, a third capacitor C3, a seventh switch device Q7, an eighth switch device Q8, an eleventh switch device Q11, a twelfth switch device Q12 and a sixteenth switch device Q16. The first end of the seventh switch device Q7 is electrically connected to the third capacitor C3, the twelfth switch Q12 and the third sub-branch 221, respectively; the second end of the seventh switch device Q7 is electrically connected to the second end of the first capacitor C1 and the first end of the eighth switch device Q8, respectively; the first end of the first capacitor is electrically connected to the second end of the first switch device Q1 in the first sub-branch 211; the second end of the eighth switch device Q8 is grounded. The second end of the third capacitor C3 is electrically connected to the second end of the eleventh switch device Q11 and the first end of the sixteenth switch device Q16, respectively; the second end of the sixteenth switch device Q16 is grounded. The second end of the twelfth switch device Q12 is electrically connected to the second output terminal VOUT of the charge pump circuit and the first end of the eleventh switch device Q11, respectively.
[0064] Continue to see Figure 3The third sub-branch 221 includes a second switching device Q2, a third switching device Q3 and a fifth switching device Q5; the first end of the second switching device Q2 is electrically connected to the input end of the charge pump circuit, and the second end of the second switching device Q2 is electrically connected to the first end of the third switching device Q3; the second end of the third switching device Q3 is electrically connected to the first end of the fifth switching device Q5, and the second end of the fifth switching device Q5 is electrically connected to the second sub-branch 212.
[0065] Continue to see Figure 3 The fourth sub-branch 222 includes a second capacitor C2, a fourth capacitor C4, a ninth switch device Q9, a tenth switch device Q10, a thirteenth switch device Q13, a fourteenth switch device Q14 and a fifteenth switch device Q15. Among them, the first end of the tenth switch device Q10 is electrically connected to the first end of the fourth capacitor C4, the first end of the thirteenth switch device Q13 and the second end of the sixth switch device Q6 in the first sub-branch; the second end of the tenth switch device Q10 is electrically connected to the first end of the ninth switch device Q9 and the second end of the second capacitor C2; the first end of the second capacitor C2 is electrically connected to the second end of the second switch device Q2; the second end of the ninth switch device Q9 is grounded. The second end of the thirteenth switch device Q13 is electrically connected to the second output terminal VOUT of the charge pump circuit and the first end of the fourteenth switch device Q14. The second end of the fourteenth switch device Q14 is electrically connected to the second end of the fourth capacitor C4 and the first end of the fifteenth switch device Q15. The second end of the fifteenth switch device Q15 is grounded.
[0066] Continue to see Figure 3 The first transfer control sub-branch 231 includes a first inductor L1. In one of the first sub-phase and the second sub-phase during the dead time, the first end of the first inductor L1 is electrically connected to the second end of the first switch device Q1, and the second end of the first inductor L1 is electrically connected to the designated output end of the charge pump circuit; in the other sub-phase during the dead time, the first end of the first inductor L1 is electrically connected to the designated output end of the charge pump circuit, and the second end of the first inductor L1 is electrically connected to the second end of the second switch device Q2.
[0067] It should also be noted that the inductance value of the first inductor L1 is less than the target inductance value, which refers to the inductance value that matches the parasitic capacitance of the switch device in the first charge pump branch and / or the second charge pump branch when resonating at the switching frequency of the two charge pump branches in the charge pump circuit. In this way, when the inductance value of the first inductor L1 is small, resonance can be avoided and the dead time can be avoided from being extended, or in other words, the charge transfer can be completed without affecting the duration of the dead time of the two charge pump branches, thereby ensuring the normal operation of the charge pump circuit.
[0068] In one embodiment, see Figure 4The charge pump circuit further includes a fifth capacitor C5, a first end of which is electrically connected to the second end of the fourth switch device Q4 and the second end of the third switch device Q3, respectively, and a second end of the fifth capacitor C5 is grounded. At this time, the first end of the fifth capacitor C5 can be used as a first output end, and its output voltage is twice the output voltage of the second output end VOUT.
[0069] In one embodiment, see Figure 4 The charge pump circuit further includes a sixth capacitor C6, a seventeenth switch device Q17, and an eighteenth switch device Q18. The first end of the seventeenth switch device Q17 is electrically connected to the second end of the eleventh switch device Q11, and the second end of the seventeenth switch device Q17 is electrically connected to the first end of the sixth capacitor C6 and the first end of the eighteenth switch device Q18, respectively. The second end of the eighteenth switch device Q18 is electrically connected to the first end of the fifteenth switch device Q15. The second end of the sixth capacitor C6 is grounded. In this way, the first end of the sixth capacitor C6 can be used as a third output terminal, outputting the same voltage as the second output terminal VOUT.
[0070] In one embodiment, see Figure 5 The first transfer control sub-branch 231 includes a first transfer control switch Q20 and a second transfer control switch Q21; the first end of the first transfer control switch Q20 is electrically connected to the second end of the first switch device Q1, and the second end of the first transfer control switch Q20 is electrically connected to the first end of the first inductor L1; the second end of the first inductor L1 is electrically connected to the first end of the second transfer control switch Q21, and the second end of the second transfer control switch Q21 is electrically connected to the designated output end of the charge pump circuit; the control ends of the first transfer control switch Q20 and the second transfer control switch Q21 are used to receive control signals; the first transfer control switch Q20 is used to switch to a conductive state when receiving a control signal during the dead period of the first working mode, so as to electrically connect the first end of the first inductor L1 to the second end of the first switch device Q1; the second transfer control switch Q21 is used to switch to a conductive state when receiving a control signal during the dead period, so as to electrically connect the second end of the first inductor L1 to the designated output end of the charge pump circuit. In this way, the charges stored in the parasitic capacitor of the first charge pump branch can flow to the first inductor, a part of the charges is stored in the inductor, and the other part of the charges flows to the designated output terminal and to the load connected to the designated output terminal.
[0071] It should be noted that the first transfer control switch Q20 can be implemented by an N-type MOS tube, and the control signal is a high-level signal; the first transfer control switch Q20 can be implemented by a P-type MOS tube, and the control signal is a low-level signal. That is, the control signal can only be set according to the selection of the first transfer control switch Q20. It is understandable that the control signals of other switching devices in the embodiments of the present disclosure can be set with reference to the control signal of the first transfer control switch Q20. In the case where the switch device can be switched to the on or off state, the corresponding solution falls within the protection scope of the present disclosure.
[0072] In one embodiment, see Figure 5 The first transfer control sub-branch 231 further includes a third transfer control switch Q22 and a fourth transfer control switch Q23; the first end of the third transfer control switch Q22 is electrically connected to the second end of the first inductor L1, and the second end of the third transfer control switch Q22 is electrically connected to the second end of the second switch device Q2; the first end of the fourth transfer control switch Q23 is electrically connected to the first end of the first inductor L1, and the second end of the fourth transfer control switch Q23 is electrically connected to the designated output end of the charge pump circuit; the third transfer control switch Q22 is used to switch to a conductive state when receiving a control signal during the dead time period, so as to electrically connect the second end of the first inductor L1 to the second end of the second switch device Q2; the fourth transfer control switch Q23 is used to switch to a conductive state when receiving a control signal during the dead time period of the first working mode, so as to electrically connect the first end of the first inductor L1 to the designated output end of the charge pump circuit. In this way, part of the charge stored in the first inductor can flow to the second charge pump branch and the other part of the charge flows to the load connected to the designated output end.
[0073] It should be noted that at least one of the first transfer control switch, the second transfer control switch, the third transfer control switch and the fourth transfer control switch is implemented using a field effect transistor, which can be integrated into the same chip or circuit board with the switching devices in each sub-branch of the charge pump circuit, and can also be manufactured using the same process, which is beneficial to reducing the volume and cost of the charge pump circuit.
[0074] In this embodiment, combined with Figure 5 The charge pump circuit shown describes the charging process and the charge transfer process. It is understandable that when the charging interface 12 of the electronic device is electrically connected to the external charging device (i.e., the power supply BAT), the processor 11 can control the first charge pump branch 21 or the second charge pump branch 22 of the charge pump circuit 13 to charge the battery 14.
[0075] In the first working mode, the processor can control the charge pump circuit to switch to the first working mode, that is, the 4:1 charging mode. Taking the processor controlling the first charge pump branch 21 as an example, the charging process includes:
[0076] In the first charging stage, the processor 11 controls the first switch device Q1, the third switch device Q3, the fifth switch device Q5, the seventh switch device Q7, the ninth switch device Q9, the eleventh switch device Q11, the thirteenth switch device Q13, the fifteenth switch device Q15 and the seventeenth switch device Q17 to switch to the on state, controls the second switch device Q2, the fourth switch device Q4, the sixth switch device Q6, the eighth switch device Q8, the tenth switch device Q10, the twelfth switch device Q12, the fourteenth switch device Q14, the sixteenth switch device Q16 and the eighteenth switch device Q18 to switch to the off state, and switches the first transfer control switch Q20, the second transfer control switch Q21, the third transfer control switch Q22 and the fourth transfer control switch Q23 to the off state. The equivalent circuit is as follows: Figure 6 shown.
[0077] Among them, the first target switch includes the first switching device Q1, the third switching device Q3, the fifth switching device Q5, the seventh switching device Q7 and the ninth switching device Q9; the second target switch includes the second switching device Q2, the fourth switching device Q4, the sixth switching device Q6, the eighth switching device Q8 and the tenth switching device Q10.
[0078] It should be noted that Figure 6 Only the parasitic capacitances of the switch devices Q1 to Q10 involved in charge transfer are illustrated, and the parasitic capacitances of other switch devices are not illustrated. Assuming that the power supply voltage is 20V, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 are all equal.
[0079] See also Figure 6 , the current path includes:
[0080] Path 1
[0081] GND->Q9->C2->Q3->VO1->C5->GND;
[0082] Path 2
[0083] BAT->Q1->C1->Q7->Q5->C5->GND;
[0084] Path 3
[0085] BAT->Q1->C1->Q7->C3->Q11->VOUT;
[0086] Path 4
[0087] BAT->Q1->C1->Q7->C3->Q17->VO2->C6->GND.
[0088] During the battery charging process, the second switch device Q2, the fourth switch device Q4, the sixth switch device Q6, the eighth switch device Q8 and the tenth switch device Q10 are charged, and the voltages after charging are 10V, 10V, 10V, 5V and 5V respectively.
[0089] Dead zone period
[0090] In one example, the dead period includes a first sub-phase and a second sub-phase, and the first sub-phase precedes the second sub-phase. The first inductor L1 is charged in the first sub-phase, and the first inductor L1 is discharged in the second sub-phase.
[0091] The first sub-stage: the processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the on state, see Figure 7 At this time, the parasitic capacitances of the fourth switch device Q4, the sixth switch device Q6 and the eighth switch device Q8 are discharged, and the voltage becomes 0 V; the first inductor L1 is charged, and the voltage rises to 5 V. Correspondingly, the parasitic capacitances of the first switch device Q1 and the seventh switch device Q7 are charged, and the voltages rise to 10 V and 5 V respectively.
[0092] Second sub-stage: the processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the disconnected state, and controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the disconnected state, and other switch devices maintain the state of the first sub-stage unchanged. Figure 8 At this time, the parasitic capacitances of the first inductor L1, the second switching device Q2 and the tenth switching device Q10 are discharged, and the voltage becomes 0V; the parasitic capacitances of the third switching device Q3, the fifth switching device Q5 and the ninth switching device Q9 are charged, and the voltages rise to 10V, 10V and 5V respectively.
[0093] In the second charging stage, the processor 11 controls the first switch device Q1, the third switch device Q3, the fifth switch device Q5, the seventh switch device Q7, the ninth switch device Q9, the eleventh switch device Q11, the thirteenth switch device Q13, the fifteenth switch device Q15 and the seventeenth switch device Q17 to switch to the off state, controls the second switch device Q2, the fourth switch device Q4, the sixth switch device Q6, the eighth switch device Q8, the tenth switch device Q10, the twelfth switch device Q12, the fourteenth switch device Q14, the sixteenth switch device Q16 and the eighteenth switch device Q18 to switch to the on state, and switches the first transfer control switch Q20 and the second transfer control switch Q21 to the off state. The equivalent circuit is as follows: Figure 6 See Figure 6 , at this time, the darker switching device is turned on and the darker switching device is turned off.
[0094] It should be noted that the first charge pump branch 21 and the second charge pump branch 22 are symmetrical structures, so the charging and discharging of the parasitic capacitances of the switch devices at symmetrical positions are the same as in the previous charging stage.
[0095] In this embodiment, by transferring part of the charge of the parasitic capacitor of the first target switch to the second target switch, the second target switch can be used as the first target switch in the next control cycle because the parasitic capacitor pre-stores or releases the charge, achieving the condition of zero voltage switching, thereby reducing the switching loss. In addition, part of the charge of the parasitic capacitor of the first target switch can be transferred to the load electrically connected to the specified output terminal or absorb the charge from the load, which can avoid energy waste, ensure the zero voltage switching condition, reduce the switching loss, and help improve the conversion efficiency of the charge pump circuit; or it can absorb energy from the load to ensure that the parasitic capacitor is in a fully charged state, creating a zero voltage condition for the switch device, and further reducing the switching loss.
[0096] In the second working mode, the processor can control the charge pump circuit to switch to the second working mode, i.e., the 2:1 charging mode. At this time, in the second working mode, the first switch device Q1, the second switch device Q2, the third switch device Q3 and the fourth switch device Q4 remain in the on state, the seventh switch device Q7, the eighth switch device Q8, the ninth switch device Q9, the tenth switch device Q10, the seventeenth switch device Q17 and the eighteenth switch device Q18 remain in the off state, the sixth switch device Q6, the twelfth switch device Q12, the fourteenth switch device Q14 and the sixteenth switch device Q16 are used as the first charge pump branch 21, the fifth switch device Q5, the thirteenth switch device Q13, the eleventh switch device Q11 and the fifteenth switch device Q15 are used as the second charge pump branch 22, and the designated output terminal of the charge pump is the second output terminal VOUT or the third output terminal VO2. Taking the processor controlling the first charge pump branch 21 as an example, the charging process includes:
[0097] The first charging stage
[0098] The processor controls the sixth switch device Q6, the twelfth switch device Q12, the fourteenth switch device Q14 and the sixteenth switch device Q16 to switch to the on state, and the fifth switch device Q5, the thirteenth switch device Q13, the eleventh switch device Q11 and the fifteenth switch device Q15 to switch to the off state. At this time, the parasitic capacitance of the thirteenth switch device Q13 and the fifteenth switch device Q15 is charged to 5V. Fig. 9 shown.
[0099] The first sub-stage of the dead time: the processor controls the first transfer control switch Q20 and the seventh transfer control switch Q27 to be turned on, see Fig. 9At this time, the parasitic capacitances of the thirteenth switching device Q13 and the fifteenth switching device Q15 are discharged, and the voltage becomes 0V; when the designated output terminal is the second output terminal, the first inductor L1 is charged, and its stored energy is E.
[0100] The second sub-stage of the dead time: the processor controls the first transfer control switch Q20 and the second transfer control switch Q21 to switch to the disconnected state, and the other switch devices maintain the state of the first sub-stage unchanged. The equivalent circuit is as follows: Fig.10 See Fig.10 At this time, the parasitic capacitances of the thirteenth switching device Q13 and the fifteenth switching device Q15 are discharged, and the voltage becomes 0V; the first inductor L1 is discharged, and its stored energy changes from E to 0; the parasitic capacitances of the twelfth switching device Q12 and the sixteenth switching device Q16 are charged, and the voltages rise to 5V respectively.
[0101] Second charging stage
[0102] The processor controls the sixth switch device Q6, the twelfth switch device Q12, the fourteenth switch device Q14 and the sixteenth switch device Q16 to switch to the off state, and the fifth switch device Q5, the thirteenth switch device Q13, the eleventh switch device Q11 and the fifteenth switch device Q15 to switch to the on state, at which time the parasitic capacitance of the twelfth switch device Q12 and the sixteenth switch device Q16 is charged to 5V.
[0103] The above process describes the scheme of charge transfer in the dead time after the charging process of the first charge pump branch 21. The scheme of charge transfer in the dead time of the charging process of the second charge pump branch 22 is similar to that of the first charge pump branch 21, and will not be repeated here. In this embodiment, part of the charge of the parasitic capacitance of the first switching device can be transferred to the second switching device and the load connected to the specified output terminal in the second working mode. When the second switching device is used as the first switching device in the next control cycle, the charge can be stored due to the parasitic capacitance. The parasitic capacitance can be charged and discharged in advance to create a zero voltage condition for the switching device, thereby reducing the switching loss. In addition, this embodiment can take into account the charging efficiency while achieving high-power charging and shorten the charging time.
[0104] It should be noted that the scheme of charge transfer in the second working mode is similar to that in the first working mode. Specifically, the scheme of charge transfer in the second working mode can be understood by analogy analysis in combination with the scheme of the first working mode.
[0105] In some possible embodiments, a chip is also provided, including the above Figures 1 to 10 The example charge pump circuit.
[0106] Fig.11 1 is a block diagram of an electronic device according to an exemplary embodiment. For example, the electronic device 1100 may be a smart phone, a computer, a digital broadcast terminal, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.
[0107] Reference Fig.11 The electronic device 1100 may include one or more of the following components: a processing component 1102 , a memory 1104 , a power component 1106 , a multimedia component 1108 , an audio component 1110 , an input / output (I / O) interface 1112 , a sensor component 1114 , a communication component 1116 , and an image acquisition component 1118 .
[0108] The processing component 1102 generally controls the overall operation of the electronic device 1100, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1102 may include one or more processors 1120 to execute computer programs. In addition, the processing component 1102 may include one or more modules to facilitate interaction between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate interaction between the multimedia component 1108 and the processing component 1102. In one example, the processor 1120 may control the charge pump circuit to charge the battery.
[0109] The memory 1104 is configured to store various types of data to support operations on the electronic device 1100. Examples of such data include computer programs for any application or method operating on the electronic device 1100, contact data, phone book data, messages, pictures, videos, etc. The memory 1104 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.
[0110] The power supply component 1106 provides power to various components of the electronic device 1100. The power supply component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1100. The power supply component 1106 may include the above-mentioned charge pump circuit or chip to power a battery.
[0111] The multimedia component 1108 includes a screen that provides an output interface between the electronic device 1100 and the target object.
[0112] In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input information from a target object. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.
[0113] The audio component 1110 is configured to output and / or input audio file information. For example, the audio component 1110 includes a microphone (MIC), and when the electronic device 1100 is in an operation mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive external audio file information. The received audio file information can be further stored in the memory 1104 or sent via the communication component 1116. In some embodiments, the audio component 1110 also includes a speaker for outputting audio file information.
[0114] The I / O interface 1112 provides an interface between the processing component 1102 and a peripheral interface module, which may be a keyboard, a click wheel, a button, etc.
[0115] The sensor component 1114 includes one or more sensors for providing various aspects of status assessment for the electronic device 1100. For example, the sensor component 1114 can detect the open / closed state of the electronic device 1100, the relative positioning of the components, such as the display screen and the keypad of the electronic device 1100, and the sensor component 1114 can also detect the position change of the electronic device 1100 or a component, the presence or absence of contact between the target object and the electronic device 1100, the orientation or acceleration / deceleration of the electronic device 1100, and the temperature change of the electronic device 1100. In this example, the sensor component 1114 can include a magnetic sensor, a gyroscope, and a magnetic field sensor, and can also include an inertial sensor, an image sensor, etc., wherein the magnetic field sensor includes at least one of the following: a Hall sensor, a thin film magnetoresistive sensor, and a magnetic liquid acceleration sensor.
[0116] The communication component 1116 is configured to facilitate wired or wireless communication between the electronic device 1100 and other devices. The electronic device 1100 can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 1116 receives broadcast information or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1116 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.
[0117] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.
[0118] In an exemplary embodiment, a chip is also provided, the chip including a processor and an interface for reading a computer program through the interface to implement the above method. The chip may be a conventional CPU (central processing unit) chip, a GPU (graphics processing unit) chip, etc., or an acceleration chip dedicated to artificial intelligence technology, such as an AI (Artificial Intelligence) accelerator, etc.
[0119] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.
[0120] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A charge pump circuit, characterized in that: include: a first charge pump branch, a second charge pump branch, and a charge transfer control branch; The charge transfer control branch is electrically connected to the first charge pump branch and the second charge pump branch respectively, and the charge transfer control branch is electrically connected to a designated output terminal; the designated output terminal is the designated output terminal of the charge pump circuit, which refers to one of the first output terminal VO1, the second output terminal VOUT or the third output terminal VO2; The charge transfer control branch is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another portion of the charge to a load electrically connected to the designated output terminal during a dead period in the first operating mode or the second operating mode; The dead zone period refers to the period during which the switching devices in the first charge pump branch and the second charge pump branch are both in the off state, the first target switch refers to the switching device that was in the on state in the previous control cycle, and the second target switch refers to the switching device that was in the off state in the previous control cycle.
2. The charge pump circuit according to claim 1, characterized in that: The first charge pump branch includes a first sub-branch and a second sub-branch that are electrically connected; the second charge pump branch includes a third sub-branch and a fourth sub-branch that are electrically connected; the first sub-branch is electrically connected to the fourth sub-branch, and the second sub-branch is electrically connected to the third sub-branch; the charge transfer control branch includes a first transfer control sub-branch; The first transfer control sub-branch is electrically connected to the first sub-branch, the third sub-branch and the designated output terminal of the charge pump circuit, respectively, and is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch to the parasitic capacitance of the first target switch and another part of the charge to a load electrically connected to the designated output terminal during the dead zone of the first operating mode.
3. The charge pump circuit according to claim 2, characterized in that: The first sub-branch includes a first switch device, a fourth switch device and a sixth switch device; the first transfer control sub-branch includes a first inductor; The first end of the first switch device is electrically connected to the input end of the charge pump circuit, and the second end of the first switch device is electrically connected to the first end of the fourth switch device; the second end of the fourth switch device is electrically connected to the first end of the sixth switch device, and the second end of the sixth switch device is electrically connected to the fourth sub-branch; The third sub-branch includes a second switch device, a third switch device and a fifth switch device; a first end of the second switch device is electrically connected to an input end of the charge pump circuit, a second end of the second switch device is electrically connected to a first end of the third switch device; a second end of the third switch device is electrically connected to a first end of the fifth switch device, and a second end of the fifth switch device is electrically connected to the second sub-branch; In one of the first sub-phase and the second sub-phase during the dead zone, the first end of the first inductor is electrically connected to the second end of the first switching device, and the second end of the first inductor is electrically connected to the designated output end; in another sub-phase during the dead zone, the first end of the first inductor is electrically connected to the designated output end, and the second end of the first inductor is electrically connected to the second end of the second switching device.
4. The charge pump circuit according to claim 3, characterized in that: The first transfer control sub-branch includes a first transfer control switch and a second transfer control switch; the first end of the first transfer control switch is electrically connected to the second end of the first switch device, and the second end of the first transfer control switch is electrically connected to the first end of the first inductor; the second end of the first inductor is electrically connected to the first end of the second transfer control switch, and the second end of the second transfer control switch is electrically connected to the designated output end; the control ends of the first transfer control switch and the second transfer control switch are used to receive control signals; The first transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the first end of the first inductor to the second end of the first switching device; The second transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the second end of the first inductor to the designated output end.
5. The charge pump circuit according to claim 4, characterized in that: The first transfer control sub-branch further includes a third transfer control switch and a fourth transfer control switch; a first end of the third transfer control switch is electrically connected to the second end of the first inductor, and a second end of the third transfer control switch is electrically connected to the second end of the second switch device; a first end of the fourth transfer control switch is electrically connected to the first end of the first inductor, and a second end of the fourth transfer control switch is electrically connected to the designated output end; The third transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the second end of the first inductor to the second end of the second switch device; The fourth transfer control switch is used to switch to a conducting state when receiving a control signal during a dead period of the first working mode, so as to electrically connect the first end of the first inductor to the designated output end.
6. The charge pump circuit according to any one of claims 2 to 5, characterized in that: The designated output terminal includes a first output terminal, and the first output terminal is electrically connected to the second terminal of the fourth switching device and the second terminal of the third switching device, respectively.
7. The charge pump circuit according to any one of claims 2 to 5, characterized in that: The fourth sub-branch includes a thirteenth switch device, a fourteenth switch device and a fifteenth switch device; the first end of the thirteenth switch device is electrically connected to the first sub-branch, the second end of the thirteenth switch device is electrically connected to the first end of the fourteenth switch device, the first end of the fifteenth switch device is electrically connected to the second end of the fourteenth switch device, and the second end of the fifteenth switch device is grounded; The second sub-branch includes an eleventh switching device, a twelfth switching device, and a sixteenth switching device; the first end of the twelfth switching device is electrically connected to the third sub-branch, the second end of the twelfth switching device is electrically connected to the first end of the eleventh switching device, the first end of the sixteenth switching device is electrically connected to the second end of the eleventh switching device, and the second end of the sixteenth switching device is grounded.
8. The charge pump circuit according to claim 7, characterized in that: The designated output terminal includes a second output terminal electrically connected to the second terminal of the thirteenth switching device and the second terminal of the twelfth switching device, respectively.
9. The charge pump circuit according to claim 7, characterized in that: The designated output terminal includes a third output terminal, and the third output terminal is electrically connected to the second terminal of the eleventh switching device and the second terminal of the fourteenth switching device, respectively.
10. The charge pump circuit according to claim 3, characterized in that: The first inductance value of the first inductor is less than a target inductance value, and the target inductance value refers to an inductance value that matches the resonance of the parasitic capacitance of the switching device in the first charge pump branch and / or the second charge pump branch at the switching frequency of the two charge pump branches in the charge pump circuit.
11. A chip, characterized in that: The invention comprises a charge pump circuit as claimed in any one of claims 1 to 10.
12. An electronic device, characterized in that: include: A processor, a battery, a charging interface, and a charge pump circuit as claimed in any one of claims 1 to 10; the charge pump circuit is electrically connected to the battery and the charging interface respectively; The processor is electrically connected to the charge pump circuit; The processor is used to control the first target switch of the first charge pump branch and the second target switch of the second charge pump branch to switch to the on state and the off state in one control cycle; The processor is used to switch the charge pump circuit to one of the first working mode or the second working mode, and control all the switch devices of the first charge pump branch and the second charge pump branch to switch to the disconnected state during the dead period of the working mode; The processor is further configured to output a control signal to a charge transfer control branch of the charge pump circuit during a dead period of the operating mode; The charge transfer control branch is used to transfer a part of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch and another part of the charge to the load electrically connected to the designated output terminal when receiving a control signal during the dead time period of the working mode; and / or, A processor, a battery, a charging interface, and a chip as claimed in claim 11; the chip is electrically connected to the battery, the charging interface, and the processor respectively; The processor is used to control the first target switch of the charge pump circuit in the chip to switch to the on state and the second target switch to switch to the off state within a control cycle; The processor is used to switch the charge pump circuit to one of the first working mode or the second working mode, and control all the switch devices of the first charge pump branch and the second charge pump branch to switch to the disconnected state during the dead period of the working mode; The processor is further configured to output a control signal to a charge transfer control branch of the charge pump circuit during a dead period of the operating mode; The charge transfer control branch is used to transfer a portion of the charge stored in the parasitic capacitance of the second target switch in the previous control cycle to the parasitic capacitance of the first target switch and another portion of the charge to a load electrically connected to the designated output terminal when a control signal is received during the dead zone of the working mode.