Package structure

Abstract

A package structure includes a cell chip structure having a memory cell and a multiplexer. The package structure includes an intermediate chip structure directly bonded to a unit chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding, and the package structure has a sense amplifier and a driving element. The intermediate chip structure does not have memory cells. The package structure includes an operation chip structure bonded to an intermediate chip structure and having an operation element.

Description

Technical Field

[0001] The present disclosure relates to a packaging structure, and more particularly to a packaging structure with an intermediate chip structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and patterning the various material layers using photolithography techniques to form circuit components and elements thereon.

[0003] Typically, dozens or hundreds of integrated circuits can be manufactured on a single semiconductor wafer. Individual dies on the wafer are separated by sawing the integrated circuits along the scribe line. Individual dies are usually packaged separately, such as in a multi-chip module, or in other types of packaging. The individual dies are then packaged separately. By continuously reducing the size of the smallest component, the semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), allowing more components to be integrated in a given area. However, as component sizes continue to shrink, production processes continue to become more difficult to perform. Therefore, reliable packaging of electronic components with high integration density is a challenge. Utility Model Content

[0004] An object of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0005] The present disclosure provides a packaging structure, including: a cell chip structure, having a memory cell and a multiplexer; an intermediate chip structure, directly bonded to the cell chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding, and having a sense amplifier and a driving element, wherein the intermediate chip structure does not have a memory cell; and a computing chip structure, bonded to the intermediate chip structure, and having a computing element.

[0006] According to one embodiment of the present invention, the unit chip structure has a first substrate, the first substrate has a first front surface facing the intermediate chip structure, the memory unit and the multiplexer are formed on the first front surface, the intermediate chip structure has a second substrate, the second substrate has a second front surface facing the unit chip structure, and the sensing amplifier and the driving element are formed on the second front surface.

[0007] According to one embodiment of the present invention, the unit chip structure has a first bonding pad located on the first front surface, the middle chip structure has a second bonding pad located below the second front surface, and the first bonding pad is directly bonded to the second bonding pad.

[0008] According to one embodiment of the present invention, the unit chip structure further has a first dielectric structure and a first heat-conducting layer located on the first dielectric structure, the first dielectric structure covers the memory unit and the multiplexer, and the first heat-conducting layer laterally surrounds the first bonding pad.

[0009] According to one embodiment of the present invention, the computing chip structure has a substrate. The substrate has a front surface facing away from the middle chip structure, and the computing element is formed on the front surface.

[0010] The disclosed embodiment provides a packaging structure, comprising: an intermediate chip structure having a sensing amplifier and a driving element but not having a memory unit; and a unit chip structure directly bonded to the intermediate chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding, wherein the unit chip structure has a memory unit, a multiplexer, a first bonding pad, a first dielectric structure, and a first thermal conductive layer located under the first dielectric structure, the first dielectric structure covers the memory unit and the multiplexer, the first thermal conductive layer surrounds the first bonding pad, the first thermal conductive layer is made of a first dielectric material, and the thermal conductivity of the first thermal conductive layer is higher than the thermal conductivity of the first dielectric structure.

[0011] According to one embodiment of the present invention, the intermediate chip structure further has a second dielectric structure and a second heat-conducting layer located on the second dielectric structure, and the second dielectric structure covers the sensing amplifier and the driving element.

[0012] According to one embodiment of the present invention, the first heat-conducting layer is directly bonded to the second heat-conducting layer.

[0013] According to one embodiment of the present invention, it also includes:

[0014] A computing chip structure is located under the middle chip structure, and the computing chip structure has a computing element.

[0015] According to one embodiment of the present invention, the first heat conducting layer is thinner than the first bonding pad.

[0016] The present embodiment provides a method for forming a packaging structure, comprising: providing a unit chip structure, the unit chip structure having a memory unit and a multiplexer; bonding an intermediate chip structure to the unit chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding, wherein the intermediate chip structure has a sensing amplifier and a driving element, and the intermediate chip structure does not have a memory unit; and bonding a computing chip structure to the intermediate chip structure, wherein the computing chip structure has a computing element. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0018] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E as well as Figure 1F Schematic diagram of cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0019] Figure 2 is a cross-sectional view of a package structure according to some embodiments.

[0020] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E as well as Figure 3F Schematic diagram of cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0021] Figure 4 is a cross-sectional view of a package structure according to some embodiments.

[0022] Figure 5 is a cross-sectional view of a package structure according to some embodiments.

[0023] Figure 6 is a cross-sectional view of a package structure according to some embodiments.

[0024] The reference numerals are as follows: 100, 200, 300, 400, 500, 600: packaging structure

[0025] 110, 110', 120, 130, 140: unit chip structure

[0026] 111, 141, 151: Substrate

[0027] 111a, 141a, 151a: front surface

[0028] 111b, 141b, 151b: rear surface

[0029] 112, 113, 142, 152, 501: Device elements

[0030] 114, 143a, 153a: Dielectric structure

[0031] 115, 143b, 143b1, 143b2, 153b: wiring layer

[0032] 116, 143c, 153c: guide holes

[0033] 117, 124, 144, 148, 157, 310: thermal conductive layer

[0034] 117a, 118a, 148a, 149a, 310a, 320a: top surface

[0035] 117b: Opening

[0036] 118, 125, 145, 149, 158: Bonding pads

[0037] 121, 126, 146, 154, 159, 210: dielectric layer

[0038] 122, 147a, 155: Guide hole structure

[0039] 123, 147b, 156, 330: Insulation layer

[0040] 124a, 125a, 144a, 145a, 157a, 158a: bottom surface

[0041] 150, 150': Computing chip structure

[0042] 160:Solder bump

[0043] 320: Bonding pad / guide hole structure

[0044] 340, 542: redistribution layer

[0045] 510, 510', 520, 530, 540: Processing chip

[0046] B: Axis

[0047] D118: Distance

[0048] MA: Memory Cell Array

[0049] MC:Memory Cell

[0050] MUX: Multiplexer DETAILED DESCRIPTION

[0051] The following disclosure provides many embodiments or examples for implementing the different elements provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0052] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0053] Some embodiments of the present invention are described below. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0054] Other components and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packages or 3D integrated circuit devices. Test structures may include, for example, test pads formed within a redistribution layer or on a substrate to allow testing of 3D packages or 3D integrated circuit devices, or testing using probes and / or probe cards and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with intermediate verification methods in conjunction with good die to increase yield and reduce costs.

[0055] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E as well as Figure 1F1 is a cross-sectional view of various stages of a process for forming a package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a cell chip structure 110 is provided. According to some embodiments, the cell chip structure 110 is also referred to as a chip-containing structure. According to some embodiments, the cell chip structure 110 has a substrate 111, a device element 112, a device element 113, a dielectric structure 114, a wiring layer 115, a guide hole 116, a heat conductive layer 117, and a bonding pad 118.

[0056] For example, the substrate 111 includes a semiconductor substrate. For example, the substrate 111 includes a semiconductor wafer (e.g., a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the substrate 111 is made of an elemental semiconductor material, and the elemental semiconductor material includes silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0057] In some embodiments, the substrate 111 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, or a combination thereof. The substrate 111 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0058] In some embodiments, device elements 112 and device elements 113 are formed in and / or on substrate 111. Examples of device elements 112 and device elements 113 include active devices, passive devices, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed on front surface 111a of substrate 111. Passive devices include resistors, capacitors, or other suitable passive devices.

[0059] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS), bipolar junction transistor (BJT), high voltage transistor, high frequency transistor, p-channel and / or n-channel field effect transistor (PFETs / n-channel field effect transistor NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor manufacturing processes, are performed to form various device elements. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more applicable processes, or a combination thereof.

[0060] In some embodiments, an isolation feature (not shown) is formed in the substrate 111. The isolation feature is used to surround the active region and electrically isolate various device elements formed in and / or on the substrate 111 in the active region. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

[0061] According to some embodiments, dielectric structure 114 is formed on substrate 111. According to some embodiments, dielectric structure 114 covers device element 112 and device element 113. According to some embodiments, dielectric structure 114 includes a dielectric layer. According to some embodiments, wiring layer 115 and via 116 are formed in dielectric structure 114. According to some embodiments, the number of wiring layer 115 is between about 3 and about 5.

[0062] According to some embodiments, the thermal conductive layer 117 and the bonding pad 118 are formed on the dielectric structure 114. According to some embodiments, the thermal conductive layer 117 surrounds the bonding pad 118.

[0063] In some embodiments, top surface 117a of thermal conductive layer 117 and top surface 118a of bonding pad 118 are substantially coplanar. According to some embodiments, via 116 electrically connects wiring layer 115 , device element 112 , device element 113 , and bonding pad 118 .

[0064] In some embodiments, the device element 112 includes a transistor (and a capacitor), and a plurality of the device elements 112 collectively form a memory cell MC. In some embodiments, a plurality of the memory cells MC collectively form a memory cell array MA.

[0065] In some embodiments, the device element 113 comprises a transistor, and according to some embodiments, the device element 113, a portion of the wiring layer 115, and a via 116 electrically connected to the element 113 together form a multiplexer MUX. According to some embodiments, the memory cell array MA is electrically connected to the multiplexer MUX. According to some embodiments, the dielectric structure 114 covers the memory cells MC and the multiplexer MUX.

[0066] The multiplexer MUX is used to provide many-to-one connections between the memory cells MC and a single circuit. In some embodiments, the memory cell array MA is electrically connected to the bonding pads 118 through the multiplexer MUX. Therefore, the distance D118 between the bonding pads 118 is not limited by the small pitch (e.g., about 0.1 μm) of the memory cells MC.

[0067] Therefore, according to some embodiments, the distance D118 is increased by the multiplexer MUX, which reduces the difficulty of the subsequent bonding process. According to some embodiments, the distance D118 is between 0.3 μm and 0.8 μm.

[0068] According to some embodiments, the dielectric structure 114 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG), or a combination thereof. Alternatively, according to some embodiments, the dielectric structure 114 includes a low-k material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0069] The dielectric structure 114 is formed using a chemical vapor deposition (CVD) process (e.g., a low-pressure CVD process, a plasma-enhanced CVD process, or a high-density plasma CVD process), an atomic layer deposition (ALD) process, a spin-on process, a physical vapor deposition (PVD) process, or another suitable process.

[0070] According to some embodiments, the wiring layer 115 , the vias 116 , and the bonding pads 118 are made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0071] According to some embodiments, the thermal conductivity of the heat conducting layer 117 is higher than the thermal conductivity of the dielectric structure 114. According to some embodiments, the heat conducting layer 117 is made of a dielectric material. According to some embodiments, the dielectric material includes a nitride material, such as aluminum nitride or boron nitride, a carbon-containing material, such as diamond, or another suitable high thermal conductivity dielectric material, the thermal conductivity of the high thermal conductivity dielectric material being higher than the thermal conductivity of silicon oxide.

[0072] According to some embodiments, forming the thermal conductive layer 117 and the bonding pad 118 includes depositing the thermal conductive layer 117 on the dielectric structure 114 ; partially removing the thermal conductive layer 117 to form an opening 117 b in the thermal conductive layer 117 ; and forming the bonding pad 118 in the opening 117 b .

[0073] The heat conductive layer 117 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a PVD process, or another suitable process.

[0074] like Figure 1B As shown, according to some embodiments, the unit chip structure 120 is bonded to the unit chip structure 110. According to some embodiments, the unit chip structure 120 is similar to the unit chip structure 110 except that it further has a dielectric layer 121, conductive via structures 122, an insulating layer 123, a thermal conductive layer 124, and a bonding pad 125.

[0075] According to some embodiments, the dielectric layer 121 is formed below the rear surface 111b of the substrate 111 of the unit chip structure 120. According to some embodiments, the dielectric layer 121 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof. Alternatively, according to some embodiments, the dielectric layer 121 includes a low-k material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0076] The dielectric layer 121 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0077] According to some embodiments, the via structure 122 passes through the substrate 111 and the dielectric layer 121. According to some embodiments, the insulating layer 123 is between the via structure 122 and the substrate 111, and between the via structure 122 and the dielectric layer 121.

[0078] According to some embodiments, the insulating layer 123 is used to electrically insulate (or separate) the via structure 122 from the substrate 111. According to some embodiments, the insulating layer 123 continuously and laterally surrounds each via structure 122.

[0079] According to some embodiments, the via structure 122 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, the insulating layer 123 is made of an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0080] Alternatively, according to some embodiments, insulating layer 123 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0081] According to some embodiments, the thermal conductive layer 124 and the bonding pad 125 are formed under the dielectric layer 121 , the via structure 122 , and the insulating layer 123 . According to some embodiments, the thermal conductive layer 124 surrounds the bonding pad 125 .

[0082] In some embodiments, the bottom surface 124a of the thermally conductive layer 124 and the bottom surface 125a of the bonding pad 125 are substantially coplanar. Figure 1BAs shown, according to some embodiments, the bottom surface 124 a of the thermal conductive layer 124 and the bottom surface 125 a of the bonding pad 125 are substantially horizontal. According to some embodiments, the via structure 122 is electrically connected to the corresponding bonding pad 125 .

[0083] According to some embodiments, the unit chip structure 120 is bonded to the unit chip structure 110 by dielectric-to-dielectric bonding and metal-to-metal bonding. For example, according to some embodiments, the thermal conductive layer 124 is directly bonded to the thermal conductive layer 117 of the unit chip structure 110 after the unit chip structure 120 is bonded to the unit chip structure 110. According to some embodiments, the bonding pad 125 is directly bonded to the bonding pad 118 of the unit chip structure 110 after the unit chip structure 120 is bonded to the unit chip structure 110.

[0084] According to some embodiments, the thermal conductivity of the heat conducting layer 124 is higher than the thermal conductivity of the dielectric structure 114 or the thermal conductivity of the dielectric layer 121. According to some embodiments, the heat conducting layer 124 is made of a dielectric material. According to some embodiments, the dielectric material includes a nitride material, such as aluminum nitride or boron nitride, a carbon-containing material, such as diamond, or another suitable high thermal conductivity dielectric material, the thermal conductivity of the high thermal conductivity dielectric material being higher than the thermal conductivity of silicon oxide.

[0085] The thermal conductive layer 124 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a PVD process, or another suitable process.

[0086] According to some embodiments, the bonding pad 125 is made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0087] like Figure 1C As shown, according to some embodiments, the unit chip structure 130 is bonded to the unit chip structure 120. According to some embodiments, the unit chip structure 130 is similar to the unit chip structure 120. According to some embodiments, the unit chip structure 130 is bonded to the unit chip structure 120 by dielectric-to-dielectric bonding and metal-to-metal bonding.

[0088] For example, according to some embodiments, the heat conductive layer 124 of the unit chip structure 130 is directly bonded to the heat conductive layer 117 of the unit chip structure 120 after the unit chip structure 130 is bonded to the unit chip structure 120. According to some embodiments, the bonding pad 125 of the unit chip structure 130 is directly bonded to the bonding pad 118 of the unit chip structure 120 after the unit chip structure 130 is bonded to the unit chip structure 120.

[0089] like Figure 1D As shown, according to some embodiments, the intermediate chip structure 140 is bonded to the unit chip structure 130 by dielectric-to-dielectric bonding and metal-to-metal bonding. According to some embodiments, the intermediate chip structure 140 is also referred to as a chip-containing structure.

[0090] According to some embodiments, the intermediate chip structure 140 has a substrate 141, a device element 142, a dielectric structure 143a, a wiring layer 143b, a via 143c, a thermal conductive layer 144, a bonding pad 145, a dielectric layer 146, a via structure 147a, an insulating layer 147b, a thermal conductive layer 148, and a bonding pad 149.

[0091] For example, the substrate 141 includes a semiconductor substrate. For example, the substrate 141 includes a semiconductor wafer (e.g., a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the substrate 141 is made of an elemental semiconductor material, and the elemental semiconductor material includes silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0092] In some embodiments, the substrate 141 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, or a combination thereof. The substrate 141 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0093] In some embodiments, device element 142 is formed in and / or on substrate 141. According to some embodiments, device element 142 includes sense amplifiers (SA) and / or driver elements. According to some embodiments, the driver element includes a word line driver.

[0094] According to some embodiments, the middle chip structure 140 does not have a memory cell and a multiplexer. According to some embodiments, the unit chip structure 110 , the unit chip structure 120 , and the unit chip structure 130 do not have a sense amplifier and / or a driver element.

[0095] According to some embodiments, the memory cells MC and the multiplexer MUX of the unit chip structure 130 are interposed between the substrate 111 of the substrate of the unit chip structure 130 and the substrate 141 of the unit chip structure 140 .

[0096] In some embodiments, the device element 142 includes an active device, a passive device, other suitable elements or a combination thereof. The active device may include a transistor or a diode (not shown) formed on the front surface 141a of the substrate 141. According to some embodiments, the front surface 141a faces the unit chip structure 130. The passive device includes a resistor, a capacitor or other suitable passive devices.

[0097] For example, the transistor may be a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor, a bipolar junction transistor, a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor, etc. Various processes, such as FEOL semiconductor manufacturing processes, are performed to form various device elements. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more applicable processes, or a combination thereof.

[0098] In some embodiments, an isolation feature (not shown) is formed in the substrate 141. The isolation feature is used to surround the active area and electrically isolate various device elements formed on and / or in the substrate 141 in the active area. In some embodiments, the isolation feature includes a shallow trench isolation feature, a local oxidation of silicon feature, other suitable isolation features, or a combination thereof.

[0099] According to some embodiments, the dielectric structure 143a is formed under the substrate 141. According to some embodiments, the dielectric structure 143a covers the device element 142. According to some embodiments, the dielectric structure 143a includes a dielectric layer. According to some embodiments, the wiring layer 143b and the via 143c are formed in the dielectric structure 143a. According to some embodiments, the number of the wiring layer 143b is between about 5 and about 7.

[0100] According to some embodiments, the thermal conductive layer 144 and the bonding pad 145 are formed under the dielectric structure 143 a . According to some embodiments, the thermal conductive layer 144 surrounds the bonding pad 145 .

[0101] In some embodiments, the bottom surface 144a of the thermal conductive layer 144 and the bottom surface 145a of the bonding pad 145 are substantially coplanar. According to some embodiments, the via 143c electrically connects the wiring layer 143b, the device element 142 and the bonding pad 145.

[0102] According to some embodiments, the heat conducting layer 144 is directly bonded to the heat conducting layer 117 of the unit chip structure 130 after the intermediate chip structure 140 is bonded to the unit chip structure 130. According to some embodiments, the bonding pad 145 is directly bonded to the bonding pad 118 of the unit chip structure 130 after the intermediate chip structure 140 is bonded to the unit chip structure 130.

[0103] According to some embodiments, the dielectric structure 143a is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof. Alternatively, according to some embodiments, the dielectric structure 143a includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0104] The dielectric structure 143 a is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0105] According to some embodiments, the wiring layer 143 b , the vias 143 c and the bonding pads 145 are made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver or tungsten) or an alloy thereof.

[0106] According to some embodiments, the thermal conductivity of the heat conducting layer 144 is higher than the thermal conductivity of the dielectric structure 143a. According to some embodiments, the heat conducting layer 144 is made of a dielectric material. According to some embodiments, the dielectric material includes a nitride material, such as aluminum nitride or boron nitride, a carbon-containing material, such as diamond, or another suitable high thermal conductivity dielectric material, the thermal conductivity of the high thermal conductivity dielectric material being higher than the thermal conductivity of silicon oxide.

[0107] The thermal conductive layer 144 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a PVD process, or another suitable process.

[0108] According to some embodiments, the dielectric layer 146 is formed on the rear surface 141b of the substrate 141. According to some embodiments, the dielectric layer 146 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0109] Alternatively, according to some embodiments, dielectric layer 146 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0110] The dielectric layer 146 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0111] According to some embodiments, the via structure 147a passes through the substrate 141 and the dielectric layer 146. The insulating layer 147b is between the via structure 147a and the substrate 141, and between the via structure 147a and the dielectric layer 146. According to some embodiments, the insulating layer 147b is used to electrically insulate (or separate) the via structure 147a from the substrate 141.

[0112] According to some embodiments, the insulating layer 147b continuously surrounds each via structure 147a. According to some embodiments, the via structure 147a is made of a conductive material, such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0113] According to some embodiments, the insulating layer 147 b is made of an oxide-containing material (eg, silicon oxide or TEOS oxide), a nitrogen-containing oxide material (eg, silicon oxynitride), a glass material (eg, borosilicate glass, phosphosilicate glass, borophosphosilicate glass or fluorinated silicate glass) or a combination thereof.

[0114] Alternatively, according to some embodiments, the insulating layer 147 b includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0115] The heat conducting layer 148 and the bonding pad 149 are formed on the dielectric layer 146 , the via structure 147 a and the insulating layer 147 b . According to some embodiments, the heat conducting layer 148 surrounds the bonding pad 149 .

[0116] In some embodiments, the top surface 148 a of the thermal conductive layer 148 and the top surface 149 a of the bonding pad 149 are substantially coplanar. According to some embodiments, the via structure 147 a is electrically connected to the corresponding bonding pad 149 .

[0117] In some embodiments, the thermal conductivity of the heat conducting layer 148 is higher than the thermal conductivity of the dielectric structure 143a or higher than the thermal conductivity of the dielectric layer 146. According to some embodiments, the heat conducting layer 148 is made of a dielectric material. According to some embodiments, the dielectric material includes a nitride material, such as aluminum nitride or boron nitride, a carbon-containing material, such as diamond, or another suitable high thermal conductivity dielectric material, the thermal conductivity of the high thermal conductivity dielectric material being higher than the thermal conductivity of silicon oxide.

[0118] The thermal conductive layer 148 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a PVD process, or another suitable process.

[0119] According to some embodiments, the bonding pad 149 is made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0120] like Figure 1E As shown, according to some embodiments, the computing chip structure 150 is bonded to the intermediate chip structure 140. According to some embodiments, the computing chip structure 150 and the intermediate chip structure 140 are bonded back-to-back. According to some embodiments, the computing chip structure 150 is also referred to as a chip-containing structure.

[0121] According to some embodiments, the computing chip structure 150 has a substrate 151 , a device element 152 , a dielectric structure 153 a , a wiring layer 153 b , a via 153 c , a dielectric layer 154 , a via structure 155 , an insulating layer 156 , a thermal conductive layer 157 , and a bonding pad 158 .

[0122] For example, the substrate 151 includes a semiconductor substrate. For example, the substrate 151 includes a semiconductor wafer (e.g., a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the substrate 151 is made of an elemental semiconductor material, which includes silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0123] In some other embodiments, the substrate 151 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, or a combination thereof. The substrate 111 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0124] In some embodiments, the device element 152 is formed on and / or in the substrate 151. According to some embodiments, the device element 152 includes a computing element. According to some embodiments, the computing element includes a cache element. According to some embodiments, the computing chip structure 150 does not have a memory cell, a multiplexer, a sense amplifier and / or a driving element.

[0125] In some embodiments, device element 152 includes active devices, passive devices, other suitable elements or combinations thereof. Active elements may include transistors or diodes (not shown) formed on front surface 151a of substrate 151. According to some embodiments, front surface 151a faces away from middle chip structure 140. Passive devices include resistors, capacitors or other suitable passive devices.

[0126] For example, the transistor may be a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor, a bipolar junction transistor, a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor, etc. Various processes, such as FEOL semiconductor manufacturing processes, are performed to form various device elements. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more applicable processes, or a combination thereof.

[0127] In some embodiments, an isolation feature (not shown) is formed in the substrate 151. The isolation feature is used to surround the active area and electrically isolate various device elements formed on and / or in the substrate 151 in the active area. In some embodiments, the isolation feature includes a shallow trench isolation feature, a local oxidation of silicon feature, other suitable isolation features, or a combination thereof.

[0128] According to some embodiments, dielectric structure 153a is formed on substrate 151. According to some embodiments, dielectric structure 153a covers device element 152. According to some embodiments, dielectric structure 153a includes a dielectric layer.

[0129] According to some embodiments, the wiring layer 153b and the via 153c are formed in the dielectric structure 153a. According to some embodiments, the number of the wiring layer 153b is between about 11 and about 15. According to some embodiments, the via 153c is electrically connected between the wiring layer 153b and the device element 152.

[0130] According to some embodiments, the dielectric structure 153a is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof. Alternatively, according to some embodiments, the dielectric structure 153a includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0131] The dielectric structure 153 a is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0132] According to some embodiments, the wiring layer 153 b and the via 153 c are made of a conductive material, such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0133] According to some embodiments, the dielectric layer 154 is formed below the rear surface 151b of the substrate 151. According to some embodiments, the dielectric layer 154 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0134] Alternatively, according to some embodiments, dielectric layer 154 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0135] The dielectric layer 154 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0136] According to some embodiments, the via structure 155 passes through the substrate 151 and the dielectric layer 154. According to some embodiments, the insulating layer 156 is between the via structure 155 and the substrate 151, and between the via structure 155 and the dielectric layer 154. According to some embodiments, the insulating layer 156 is used to electrically insulate (or separate) the via structure 155 from the substrate 151.

[0137] According to some embodiments, the insulating layer 156 continuously surrounds each via structure 155. According to some embodiments, the via structure 155 is made of a conductive material, such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0138] According to some embodiments, the insulating layer 156 is made of an oxide-containing material (eg, silicon oxide or TEOS oxide), a nitrogen-containing oxide material (eg, silicon oxynitride), a glass material (eg, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0139] Alternatively, according to some embodiments, insulating layer 156 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0140] According to some embodiments, the thermal conductive layer 157 and the bonding pad 158 are formed under the dielectric layer 154, the via structure 155, and the insulating layer 156. According to some embodiments, the thermal conductive layer 157 laterally surrounds the bonding pad 158.

[0141] In some embodiments, the bottom surface 157 a of the thermal conductive layer 157 and the top surface 158 a of the bonding pad 158 are substantially coplanar. According to some embodiments, the via structures 155 are electrically connected to the corresponding bonding pads 158 .

[0142] According to some embodiments, the computing chip structure 150 is bonded to the intermediate chip structure 140 by dielectric-to-dielectric bonding and metal-to-metal bonding. For example, according to some embodiments, the thermal conductive layer 157 is directly bonded to the thermal conductive layer 148 of the intermediate chip structure 140 after the computing chip structure 150 is bonded to the intermediate chip structure 140. According to some embodiments, the bonding pad 158 is directly bonded to the bonding pad 149 of the intermediate chip structure 140 after the computing chip structure 150 is bonded to the intermediate chip structure 140.

[0143] According to some embodiments, the thermal conductivity of the heat conducting layer 157 is higher than the thermal conductivity of the dielectric structure 153a or higher than the thermal conductivity of the dielectric layer 154. According to some embodiments, the heat conducting layer 157 is made of a dielectric material. According to some embodiments, the dielectric material includes a nitride material, such as aluminum nitride or boron nitride, a carbon-containing material, such as diamond, or another suitable high thermal conductivity dielectric material, the thermal conductivity of the high thermal conductivity dielectric material being higher than the thermal conductivity of silicon oxide.

[0144] According to some embodiments, the dielectric constant (k) value of thermal conductive layer 117 , thermal conductive layer 124 , thermal conductive layer 144 , thermal conductive layer 148 , or thermal conductive layer 157 is higher than the dielectric constant (k) value of dielectric structure 114 , dielectric structure 143 a , dielectric structure 153 a , or silicon oxide.

[0145] The heat conductive layer 157 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a PVD process, or another suitable process.

[0146] According to some embodiments, the bonding pad 158 is made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0147] like Figure 1E As shown, according to some embodiments, a solder bump 160 is formed on the dielectric structure 153a. According to some embodiments, the solder bump 160 is electrically connected to the wiring layer 153b and the via 153c. According to some embodiments, the solder bump 160 is made of a conductive material, such as a tin-based alloy.

[0148] like Figure 1E as well as Figure 1F As shown, according to some embodiments, a dicing process is performed along a dicing line. According to some embodiments, the package structure 100 is formed after the dicing process. According to some embodiments, for simplicity, Figure 1F Only one package structure 100 is shown.

[0149] According to some embodiments, the package structure 100 includes a unit chip structure 110, a unit chip structure 120, a unit chip structure 130, an intermediate chip structure 140, a computing chip structure 150, and portions of solder bumps 160. According to some embodiments, the computing chip structure 150 includes a central processing unit (CPU) chip structure. According to some embodiments, the unit chip structure 110, the unit chip structure 120, the unit chip structure 130, and the intermediate chip structure 140 together form a static random access memory (SRAM) device.

[0150] In a comparative example (not shown), the memory cell array, multiplexer, sense amplifier and driver element are formed in the same chip structure, and data is transmitted laterally from the memory cell array to the multiplexer and sense amplifier and / or driver element, and the length of the lateral transmission path is in the millimeter level.

[0151] In contrast, according to some embodiments, the present disclosure forms a memory array MA and a multiplexer MUX in a first chip structure (i.e., unit chip structure 110, unit chip structure 120, or unit chip structure 130), and forms a sense amplifier and a driving unit (i.e., device element 142) in a second chip structure (i.e., middle chip structure 140), and the first chip structure and the second chip structure are stacked vertically with each other. Therefore, data is vertically transmitted from the first chip structure to the second chip structure, and the length of the vertical transmission path is between about 250 μm and about 350 μm, which is much smaller than the length of the lateral transmission path of the comparative example.

[0152] Therefore, according to some embodiments, the present disclosure shortens the data transmission path, which improves the performance of the package structure 100. In addition, according to some embodiments, since the unit chip structure 110, the unit chip structure 120, or the unit chip structure 130 only has the memory cell array MA and the multiplexer MUX, the number of wiring layers 115 is reduced, thereby reducing the thickness of the unit chip structure 110, the unit chip structure 120, and the unit chip structure 130.

[0153] Likewise, according to some embodiments, since the intermediate chip structure 140 only has a sense amplifier and a driving element (i.e., the device element 142), the number of wiring layers 143b is reduced, thereby reducing the thickness of the intermediate chip structure. Therefore, the total thickness of the unit chip structure 110, the unit chip structure 120, the unit chip structure 130, and the intermediate chip structure 140 is reduced.

[0154] Therefore, according to some embodiments, the heat dissipation path from the computing chip structure 150 to the unit chip structure 110 is shortened, and the heat dissipation path is connected to the heat dissipation cover in the subsequent process. Therefore, according to some embodiments, the heat dissipation performance of the package structure 100 is improved.

[0155] Since the unit chip structure 110, the unit chip structure 120 or the unit chip structure 130 only has a small pitch memory array MA and a multiplexer MUX, and does not have other large pitch peripheral devices, the distance D118 between the bonding pads 118 is smaller than the distance between the bonding pads in the comparative example. Therefore, according to some embodiments, the number of bonding pads 118 of the present disclosure is greater than the number of bonding pads in the comparative example, which improves the transmission capacity (or bandwidth) of the package structure 100.

[0156] According to some embodiments, since the memory cell MC is formed using a more advanced technology node than surrounding device elements (e.g., sense amplifiers and driver elements), the unit chip structure 110, the unit chip structure 120, and the unit chip structure 130 are formed independently of the intermediate chip structure 140 to individually optimize and reduce manufacturing costs.

[0157] According to some embodiments, since the package structure 100 includes the heat conducting layer 117 , the heat conducting layer 124 , the heat conducting layer 144 , the heat conducting layer 148 , and the heat conducting layer 157 , the heat dissipation performance of the package structure 100 is improved.

[0158] like Figure 1F As shown, according to some embodiments, the via structure 122 of the unit chip structure 120 and the via structure 122 of the unit chip structure 130 are aligned with each other along an axis B, and the axis B is substantially perpendicular to the front surface 111a of the substrate 111. Therefore, according to some embodiments, data is transmitted from the unit chip structure 110 to the intermediate chip structure 140 through the shortest path, thereby improving the data transmission performance of the package structure 100.

[0159] Figure 2 FIG. 2 is a cross-sectional view of a package structure 200 according to some embodiments. Figure 2 As shown, according to some embodiments, the package structure 200 is similar to the package structure 200 except that the thermal conductive layer 117 of the package structure 200 is thinner than the bonding pad 118. Figure 1F A packaging structure 100 is provided.

[0160] Furthermore, according to some embodiments, thermally conductive layer 124 is thinner than bonding pads 125. According to some embodiments, thermally conductive layer 144 is thinner than bonding pads 145 of intermediate chip structure 140.

[0161] According to some embodiments, heat conducting layer 148 is thinner than bonding pads 149 of middle chip structure 140. According to some embodiments, heat conducting layer 157 is thinner than bonding pads 158 of computing chip structure 150.

[0162] According to some embodiments, the unit chip structure 120 further has a dielectric layer 126. According to some embodiments, the dielectric layer 126 is between the dielectric layer 121 and the thermal conductive layer 124. According to some embodiments, the dielectric layer 126 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0163] Alternatively, according to some embodiments, dielectric layer 126 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0164] The dielectric layer 126 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0165] According to some embodiments, the unit chip structure 130 also has a dielectric layer 126. According to some embodiments, the dielectric layer 126 is interposed between the dielectric layer 121 and the thermal conductive layer 124.

[0166] According to some embodiments, the intermediate chip structure 140 further has a dielectric layer 210. According to some embodiments, the dielectric layer 210 is between the dielectric layer 146 and the thermally conductive layer 148. According to some embodiments, the dielectric layer 210 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0167] Alternatively, according to some embodiments, dielectric layer 210 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5. Dielectric layer 210 is formed using a CVD process (e.g., a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0168] According to some embodiments, the computing chip structure 150 further has a dielectric layer 159. According to some embodiments, the dielectric layer 159 is between the dielectric layer 154 and the thermal conductive layer 157. According to some embodiments, the dielectric layer 159 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0169] Alternatively, according to some embodiments, dielectric layer 159 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5. Dielectric layer 159 is formed using a CVD process (e.g., a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0170] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E as well as Figure 3F 1 is a cross-sectional view of various stages of a process for forming a package structure according to some embodiments. Figure 3AAs shown, according to some embodiments, a computing chip structure 150' is provided. According to some embodiments, except that the computing chip structure 150' does not have Figure 1E The computing chip structure 150′ is similar to the computing chip structure 150′ except for the dielectric layer 154, the guide hole structure 155, the insulating layer 156, the heat conductive layer 157 and the bonding pad 158 of the computing chip structure 150. Figure 1E A computing chip structure 150 is provided.

[0171] According to some embodiments, the computing chip structure 150 ′ further has a heat conducting layer 310 and a bonding pad 320 . According to some embodiments, the heat conducting layer 310 and the bonding pad 320 are formed on the dielectric structure 153 a . According to some embodiments, the heat conducting layer 310 surrounds the bonding pad 320 .

[0172] In some embodiments, the top surface 310 a of the thermal conductive layer 310 is substantially coplanar with the top surface 320 a of the bonding pad 320 . According to some embodiments, the via 153 c electrically connects the wiring layer 153 b , the device element 152 , and the bonding pad 320 .

[0173] According to some embodiments, the thermal conductivity of the heat conducting layer 310 is higher than the thermal conductivity of the dielectric structure 153a. According to some embodiments, the heat conducting layer 310 is made of a dielectric material. According to some embodiments, the dielectric material includes a nitride material, such as aluminum nitride or boron nitride, a carbon-containing material, such as diamond, or another suitable high thermal conductivity dielectric material, the high thermal conductivity dielectric material having a thermal conductivity higher than the thermal conductivity of silicon oxide.

[0174] The heat conductive layer 310 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a PVD process, or another suitable process.

[0175] According to some embodiments, the bonding pad 320 is made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0176] like Figure 3B As shown, according to some embodiments, the intermediate chip structure 140 is bonded to the computing chip structure 150 ′. According to some embodiments, the intermediate chip structure 140 is similar or identical to Figure 1E The intermediate chip structure 140 is shown.

[0177] According to some embodiments, the intermediate chip structure 140 is bonded to the computing chip structure 150' by dielectric-to-dielectric bonding and metal-to-metal bonding. For example, according to some embodiments, the thermal conductive layer 148 is directly bonded to the thermal conductive layer 310 of the computing chip structure 150' after the intermediate chip structure 140 is bonded to the computing chip structure 150'. According to some embodiments, the bonding pad 149 is directly bonded to the bonding pad 320 of the computing chip structure 150' after the intermediate chip structure 140 is bonded to the computing chip structure 150'.

[0178] like Figure 3C As shown, according to some embodiments, a unit chip structure 130 is provided. According to some embodiments, the unit chip structure 130 is similar to or the same as Figure 1E The unit chip structure 130. Figure 3C As shown, according to some embodiments, the unit chip structure 130 is directly bonded to the intermediate chip structure 140 through dielectric-to-dielectric bonding and metal-to-metal bonding.

[0179] For example, according to some embodiments, the heat conductive layer 117 is directly bonded to the heat conductive layer 144 of the intermediate chip structure 140 after the unit chip structure 130 is directly bonded to the intermediate chip structure 140. According to some embodiments, the bonding pad 118 is directly bonded to the bonding pad 145 of the intermediate chip structure 140 after the unit chip structure 130 is directly bonded to the intermediate chip structure 140.

[0180] like Figure 3D As shown, according to some embodiments, a unit chip structure 120 is provided. According to some embodiments, the unit chip structure 120 is similar to or the same as Figure 1E The unit chip structure 120. Figure 3D As shown, according to some embodiments, the unit chip structure 120 is directly bonded to the unit chip structure 130 through dielectric-to-dielectric bonding and metal-to-metal bonding.

[0181] For example, according to some embodiments, the heat conductive layer 117 is directly bonded to the heat conductive layer 124 of the unit chip structure 130 after the unit chip structure 120 is directly bonded to the unit chip structure 130. According to some embodiments, the bonding pad 118 is directly bonded to the bonding pad 125 of the unit chip structure 130 after the unit chip structure 120 is directly bonded to the unit chip structure 130.

[0182] like Figure 3E According to some embodiments, a unit chip structure 110' is provided. According to some embodiments, in addition to the unit chip structure 110' further having a dielectric layer 310, a via structure 320, an insulating layer 330 and a redistribution layer 340, the unit chip structure 110' is similar to Figure 1E A unit chip structure 110 is provided.

[0183] According to some embodiments, the dielectric layer 310 is formed on the rear surface 111b of the substrate 111 of the unit chip structure 110'. According to some embodiments, the dielectric layer 310 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof. Alternatively, according to some embodiments, the dielectric layer 310 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0184] The dielectric layer 310 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0185] According to some embodiments, the via structure 320 passes through the substrate 111 and the dielectric layer 310. According to some embodiments, the insulating layer 330 is interposed between the via structure 320 and the substrate 111, and between the via structure 320 and the dielectric layer 310.

[0186] According to some embodiments, the insulating layer 330 is used to electrically insulate (or separate) the via structure 320 from the substrate 111. According to some embodiments, the insulating layer 330 continuously surrounds the via structure 320.

[0187] According to some embodiments, the via structure 320 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, the insulating layer 330 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof. Alternatively, according to some embodiments, the insulating layer 330 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0188] According to some embodiments, the redistribution layer 340 includes a dielectric structure (not shown), a wiring layer (not shown), and a via (not shown). According to some embodiments, the wiring layer and the via are located in the dielectric structure. According to some embodiments, the via is electrically connected between the wiring layer and the via structure 320.

[0189] According to some embodiments, the dielectric structure is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), an oxide-nitride-containing material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0190] Alternatively, according to some embodiments, the dielectric structure comprises a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5. According to some embodiments, the wiring layer and the vias are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver or tungsten) or an alloy thereof.

[0191] like Figure 3E as well as Figure 3F As shown, according to some embodiments, the cutting process is performed along the cutting line. According to some embodiments, the package structure 300 is formed after the cutting process. According to some embodiments, for simplicity, Figure 3F Only one package structure 300 is shown.

[0192] According to some embodiments, the package structure 300 includes portions of the unit chip structure 110 ′, the unit chip structure 120 , the unit chip structure 130 , the intermediate chip structure 140 , the computing chip structure 150 ′, and the solder bumps 160 .

[0193] Figure 4 FIG. 4 is a cross-sectional view of a package structure 400 according to some embodiments. Figure 4 As shown, according to some embodiments, the package structure 400 is similar to the package structure 400 except that the thermal conductive layer 117 of the package structure 400 is thinner than the bonding pad 118. Figure 3F A packaging structure 300 is provided.

[0194] Furthermore, according to some embodiments, thermally conductive layer 124 is thinner than bonding pads 125. According to some embodiments, thermally conductive layer 144 is thinner than bonding pads 145 of intermediate chip structure 140.

[0195] According to some embodiments, heat conducting layer 148 is thinner than bonding pads 149 of middle chip structure 140. According to some embodiments, heat conducting layer 310 is thinner than bonding pads 320 of computing chip structure 150'.

[0196] According to some embodiments, the unit chip structure 120 further has a dielectric layer 126. The dielectric layer 126 is between the dielectric layer 121 and the thermal conductive layer 124. According to some embodiments, the dielectric layer 126 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0197] Alternatively, according to some embodiments, dielectric layer 126 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5.

[0198] The dielectric layer 126 is formed using a CVD process (eg, a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0199] According to some embodiments, the unit chip structure 130 also has a dielectric layer 126. According to some embodiments, the dielectric layer 126 is interposed between the dielectric layer 121 and the thermal conductive layer 124.

[0200] According to some embodiments, the intermediate chip structure 140 further has a dielectric layer 210. According to some embodiments, the dielectric layer 210 is between the dielectric layer 146 and the thermally conductive layer 148. The dielectric layer 126 is between the dielectric layer 121 and the thermally conductive layer 124. According to some embodiments, the dielectric layer 210 is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0201] Alternatively, according to some embodiments, dielectric layer 210 includes a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5. Dielectric layer 210 is formed using a CVD process (e.g., a low pressure CVD process, a plasma enhanced CVD process, or a high density plasma CVD process), an atomic layer deposition process, a spin coating process, a PVD process, or another suitable process.

[0202] Figure 5 FIG. 5 is a cross-sectional view of a package structure 500 according to some embodiments. Figure 5As shown, according to some embodiments, the packaging structure 500 is similar to the packaging structure 100 of 1F, except that the packaging structure 500 does not have the computing chip structure 150 of the packaging structure 100, and uses a processing chip (processing chip) 510, a processing chip 520, a processing chip 530 and a processing chip 540 to replace the unit chip structure 110, the unit chip structure 120, the unit chip structure 130 and the intermediate chip structure 140 of the packaging structure 100 respectively.

[0203] According to some embodiments, processing chip 510, processing chip 520, and processing chip 530 are similar to unit chip structure 110, unit chip structure 120, and unit chip structure 130 of package structure 100, respectively, except that device element 501 is used to replace device element 112 of unit chip structure 110, device element 112 of unit chip structure 130, and device element 112 of unit chip structure 130. According to some embodiments, device element 501 includes a logic device element, such as a transistor having a logic gate (e.g., AND gate, OR gate, XOR gate, NOT gate, NAND gate, NOR gate, and XNOR gate).

[0204] According to some embodiments, processing chip 540 is similar to intermediate chip structure 140 of package structure 100 except that redistribution layer 542 replaces thermal conductive layer 148 and bonding pads 149 of package structure 100. According to some embodiments, solder bumps 160 are formed on redistribution layer 542.

[0205] According to some embodiments, the redistribution layer 542 includes a dielectric structure (not shown), a wiring layer (not shown), and a via (not shown). According to some embodiments, the wiring layer and the via are located in the dielectric structure.

[0206] According to some embodiments, the via is electrically connected between the wiring layer and the via structure 147 a. According to some embodiments, the solder bump 160 is electrically connected to the via structure 147 a through the wiring layer of the redistribution layer 542 and the via of the redistribution layer 542 .

[0207] According to some embodiments, the dielectric structure is made of an oxide-containing material (e.g., silicon oxide or TEOS oxide), an oxide-nitride-containing material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or fluorinated silicate glass), or a combination thereof.

[0208] Alternatively, according to some embodiments, the dielectric structure comprises a low dielectric constant material or a porous dielectric material having a dielectric constant (k) value lower than that of silicon oxide or a dielectric constant lower than about 3.0 or about 2.5. According to some embodiments, the wiring layer and the vias are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver or tungsten) or an alloy thereof.

[0209] According to some embodiments, the device element 142 includes a sense amplifier, a buffer element and / or a driver element. According to some embodiments, the driver element includes a word line driver.

[0210] According to some embodiments, processing chip 540 includes wiring layers 143b1 and 143b2. According to some embodiments, wiring layer 143b1 includes conductive lines electrically connected to logic gates of device elements 501 of processing chips 510, 520, and 530, and the conductive lines are similar to word lines.

[0211] According to some embodiments, wiring layer 143b2 includes conductive lines electrically connected to drain electrodes of device elements 501 of processing chip 510, processing chip 520, and processing chip 530, and the conductive lines are similar to bit lines.

[0212] According to some embodiments, processing chip 540 does not have logic device elements, such as transistors having logic gates (e.g., AND gates, OR gates, XOR gates, NOR gates, NAND gates, NOR gates, and XNOR gates). According to some embodiments, processing chip 510, processing chip 520, and processing chip 530 do not have sense amplifiers, cache elements, driver elements, and conductive lines such as word lines and bit lines.

[0213] The package structure 500 is an XPU package, such as an accelerated processing unit (APU) package structure, a central processing unit package structure, a graphic processing unit (GPU) package structure or the like.

[0214] Figure 6 FIG. 6 is a cross-sectional view of a package structure 600 according to some embodiments. Figure 6 As shown, according to some embodiments, the package structure 600 is similar to the package structure 300 except that the package structure 600 does not have the computing chip structure 150' of the package structure 300, and uses the processing chip 510', the processing chip 520, the processing chip 530 and the processing chip 540 to replace the unit chip structure 110', the unit chip structure 120, the unit chip structure 130 and the intermediate chip structure 140 of the package structure 300 respectively. Figure 3F A packaging structure 300 is provided.

[0215] According to some embodiments, processing chip 510′, processing chip 520, and processing chip 530 are similar to unit chip structure 110′, unit chip structure 120, and unit chip structure 130, respectively, except that device element 501 is used to replace device element 112 of unit chip structure 110′, unit chip structure 120, and unit chip structure 130. According to some embodiments, device element 501 includes a logic device element, such as a transistor having a logic gate (e.g., an AND gate, an OR gate, an XOR gate, a NOR gate, an NAND gate, an NOR gate, and an XNOR gate).

[0216] According to some embodiments, processing chip 540 is similar to middle chip structure 140 of package structure 300 , except that processing chip 540 does not have dielectric layer 146 , via structure 147 a , insulation layer 147 b , thermal conductive layer 148 , and bonding pad 149 of middle chip structure 140 .

[0217] According to some embodiments, the device element 142 includes a sense amplifier, a cache unit and / or a driver element. According to some embodiments, the driver element includes a word line.

[0218] According to some embodiments, the wiring layer 143b of the processing chip 540 includes a wiring layer 143b1 and a wiring layer 143b2. According to some embodiments, the wiring layer 143b1 includes conductive lines, which are electrically connected to the logic gates of the device elements 501 of the processing chips 510', 520, and 530, and the conductive lines are similar to word lines.

[0219] According to some embodiments, wiring layer 143b2 includes conductive lines electrically connected to drain electrodes of device elements 501 of processing chip 510', processing chip 520, and processing chip 530, and the conductive lines are similar to bit lines.

[0220] According to some embodiments, the processing chip 540 does not have logic device elements, such as transistors having logic gates (e.g., AND gates, OR gates, XOR gates, NOR gates, NAND gates, NOR gates, and XNOR gates). According to some embodiments, the processing chip 510', the processing chip 520, and the processing chip 530 do not have sense amplifiers, cache elements, driver elements, and conductive lines such as word lines and bit lines.

[0221] The package structure 600 is an XPU package, such as an accelerated processing unit package structure, a central processing unit package structure, a graphics processing unit package structure or the like.

[0222] The processes and materials used to form package structures 200, 300, 400, 500, and 600 may be similar to or the same as the processes and materials used to form the package structure 100. Figure 6 Components designated by the same symbols have the same or similar structures and materials. Therefore, the detailed description thereof will not be repeated in the present disclosure.

[0223] According to some embodiments, a packaging structure and a method for forming the same are provided. This method (the method for forming the packaging structure) forms a memory array and a multiplexer in a first chip structure, and forms a sense amplifier and a drive unit in a second chip structure, and the first chip structure and the second chip structure are stacked vertically with each other. Therefore, data is vertically transmitted from the first chip structure to the second chip structure, and the transmission path is shortened. Therefore, the performance of the packaging structure is improved.

[0224] According to some embodiments, a packaging structure is provided. This packaging structure includes a unit chip structure having a memory unit and a multiplexer. This packaging structure includes an intermediate chip structure, which is directly bonded to the unit chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding, and the intermediate chip structure has a sense amplifier and a driving element. This intermediate chip structure does not have a memory unit. This packaging structure includes a computing chip structure, which is bonded to the intermediate chip structure, and the computing chip has a computing element. In some embodiments, the packaging structure, wherein the unit chip structure has a first substrate, the first substrate has a first front surface facing the intermediate chip structure, the memory unit and the multiplexer are formed on the first front surface, the intermediate chip structure has a second substrate, the second substrate has a second front surface facing the unit chip structure, and the sense amplifier and the driving element are formed on the second front surface. In some embodiments, the packaging structure, wherein the unit chip structure has a first bonding pad located above the first front surface, the intermediate chip structure has a second bonding pad located below the second front surface, and the first bonding pad is directly bonded to the second bonding pad. In some embodiments, a packaging structure, wherein the unit chip structure further has a first dielectric structure and a first thermally conductive layer located on the first dielectric structure, the first dielectric structure covers the memory unit and the multiplexer, the first thermally conductive layer laterally surrounds the first bonding pad, the first thermally conductive layer is made of a first dielectric material, and the thermal conductivity of the first thermally conductive layer is higher than the thermal conductivity of the first dielectric structure. In some embodiments, a packaging structure, wherein the intermediate chip structure further has a second dielectric structure and a second thermally conductive layer located below the second dielectric structure, the second dielectric structure covers the sensing amplifier and the driving element, the second thermally conductive layer surrounds the second bonding pad, the thermal conductivity of the second thermally conductive layer is higher than the thermal conductivity of the second dielectric structure, the second thermally conductive layer is made of a second dielectric material, and the first thermally conductive layer is directly bonded to the second thermally conductive layer. In some embodiments, a packaging structure, wherein the computing chip structure has a substrate, the substrate has a front surface facing away from the intermediate chip structure, and the computing element is formed on the front surface. In some embodiments, a packaging structure, wherein the computing chip structure is bonded to the intermediate chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding.

[0225] According to some embodiments, a packaging structure is provided. This packaging structure includes an intermediate chip structure, which has a sensing amplifier and a driving element, and does not have a memory unit. This packaging structure includes a unit chip structure, which is directly bonded to the intermediate chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. This unit chip structure has a memory unit, a multiplexer, a first bonding pad, a first dielectric structure, and a first thermal conductive layer located under the first dielectric structure, the first dielectric structure covers the memory unit and the multiplexer, the first thermal conductive layer surrounds the first bonding pad, the first thermal conductive layer is made of a first dielectric material, and the thermal conductivity of the first thermal conductive layer is higher than the thermal conductivity of the first dielectric structure. In some embodiments, the packaging structure, wherein the intermediate chip structure also has a second dielectric structure and a second thermal conductive layer located above the second dielectric structure, the second dielectric structure covers the sensing amplifier and the driving element, the second thermal conductive layer is made of a second dielectric material, and the thermal conductivity of the second thermal conductive layer is higher than the thermal conductivity of the second dielectric structure. In some embodiments, the packaging structure, wherein the first thermal conductive layer is directly bonded to the second thermal conductive layer. In some embodiments, the package structure further comprises a computing chip structure located below the intermediate chip structure, and the computing chip structure has a computing element. In some embodiments, the package structure, wherein the computing chip structure further comprises a second dielectric structure and a second heat-conducting layer located above the second dielectric structure, the second heat-conducting layer covers the computing element, and the thermal conductivity of the second heat-conducting layer is higher than the thermal conductivity of the second dielectric structure. In some embodiments, the package structure, wherein the first heat-conducting layer is thinner than the first bonding pad.

[0226] According to some embodiments, a method for forming a package structure is provided. The method for forming the package structure includes providing a unit chip structure, wherein the unit chip structure has a memory unit and a multiplexer. The method for forming the package structure includes bonding an intermediate chip structure to the unit chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding. The intermediate chip structure has a sense amplifier and a driving element, and the intermediate chip structure does not have a memory unit. The method for forming the package structure includes bonding a computing chip structure to the intermediate chip structure, wherein the computing chip structure has a computing element. In some embodiments, the method for forming the package structure, wherein the unit chip structure also has a first substrate, the intermediate chip structure also has a second substrate, and the memory unit, the multiplexer, the sense amplifier and the driving element are between the first substrate and the second substrate. In some embodiments, the method for forming the package structure, wherein the unit chip structure also has a first dielectric structure and a first heat-conducting layer, the first dielectric structure covers the memory unit and the multiplexer, the first heat-conducting layer is formed on the first dielectric structure, the first heat-conducting layer is made of a first dielectric material, and the thermal conductivity of the first heat-conducting layer is higher than the thermal conductivity of the first dielectric structure. In some embodiments, a method for forming a packaging structure, wherein the intermediate chip structure also has a second dielectric structure and a second heat-conducting layer, the second dielectric structure covers the sensing amplifier and the driving element, the second heat-conducting layer is located below the second dielectric structure, the thermal conductivity of the second heat-conducting layer is higher than the thermal conductivity of the second dielectric structure, the second heat-conducting layer is made of a second dielectric material, and after the step of bonding the intermediate chip structure to the unit chip structure, the second heat-conducting layer is directly bonded to the first heat-conducting layer. In some embodiments, a method for forming a packaging structure, wherein the intermediate chip structure also has a substrate and a third heat-conducting layer, the substrate is between the second heat-conducting layer and the third heat-conducting layer, the third heat-conducting layer is made of a third dielectric material, and the thermal conductivity of the third heat-conducting layer is higher than the thermal conductivity of the second dielectric structure. In some embodiments, a method for forming a packaging structure, wherein the computing chip structure also has a fourth heat-conducting layer, the fourth heat-conducting layer is made of a fourth dielectric material, and the fourth heat-conducting layer is directly bonded to the third heat-conducting layer.

[0227] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: A unit chip structure has a memory unit and a multiplexer; an intermediate chip structure directly bonded to the unit chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding, and the intermediate chip structure has a sense amplifier and a driving element, wherein the intermediate chip structure does not have a memory cell; and A computing chip structure is connected to the intermediate chip structure, and the computing chip has a computing element.

2. The packaging structure according to claim 1, characterized in that: The unit chip structure has a first substrate, the first substrate has a first front surface facing the middle chip structure, the memory unit and the multiplexer are formed on the first front surface, the middle chip structure has a second substrate, the second substrate has a second front surface facing the unit chip structure, and the sensing amplifier and the driving element are formed on the second front surface.

3. The packaging structure according to claim 2, characterized in that: The unit chip structure has a first bonding pad located on the first front surface, the middle chip structure has a second bonding pad located under the second front surface, and the first bonding pad is directly bonded to the second bonding pad.

4. The packaging structure according to claim 3, characterized in that: The unit chip structure also has a first dielectric structure and a first heat-conducting layer located on the first dielectric structure. The first dielectric structure covers the memory unit and the multiplexer, and the first heat-conducting layer laterally surrounds the first bonding pad.

5. The packaging structure according to claim 1 or 2, characterized in that: The computing chip structure has a substrate. The substrate has a front surface facing away from the middle chip structure, and the computing element is formed on the front surface.

6. A packaging structure, characterized in that: include: an intermediate chip structure having a sense amplifier and a driving element but no memory cell; and A unit chip structure is directly bonded to the intermediate chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding, wherein The unit chip structure has a memory unit, a multiplexer, a first bonding pad, a first dielectric structure and a first heat-conducting layer under the first dielectric structure. The first dielectric structure covers the memory unit and the multiplexer, and the first heat-conducting layer surrounds the first bonding pad.

7. The packaging structure according to claim 6, characterized in that: The middle chip structure also has a second dielectric structure and a second heat-conducting layer located on the second dielectric structure, and the second dielectric structure covers the sensing amplifier and the driving element.

8. The packaging structure according to claim 7, characterized in that: The first heat conducting layer is directly bonded to the second heat conducting layer.

9. The packaging structure according to claim 6, characterized in that: Also includes: A computing chip structure is located under the middle chip structure, and the computing chip structure has a computing element.

10. The packaging structure according to claim 6, characterized in that: The first heat conducting layer is thinner than the first bonding pad.

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