Power semiconductor device of integrated sensor

Abstract

The utility model discloses a power semiconductor device of an integrated sensor. The power semiconductor device comprises a substrate, a power semiconductor wafer, a power terminal and a signal terminal, the substrate is used for providing circuit connection and mechanical support for the power semiconductor wafer, the power terminal and the signal terminal; an electrode on the power semiconductor wafer is electrically connected with the power terminal and the signal terminal through the substrate, and the power terminal and the signal terminal are folded upwards in the direction away from the power semiconductor wafer; the power semiconductor wafer comprises a plurality of power semiconductor units, and each power semiconductor unit comprises a plurality of power semiconductor cells, a current sensor and / or a temperature sensor. According to the utility model, the current sensor and / or the temperature sensor are / is integrated in the power semiconductor unit, so that the current and / or junction temperature detection of the power semiconductor wafer is realized, and the expansion application of the power semiconductor device is facilitated.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a power semiconductor device with an integrated sensor. Background Art

[0002] In the field of power electronics, wide bandgap semiconductor material silicon carbide has advantages over silicon, such as higher breakdown voltage, lower switching loss and high temperature resistance. In order to meet the application requirements of heat dissipation consistency and simplified circuits, silicon carbide chips are usually used in the form of module products. Currently, silicon carbide modules are mainly divided into three research directions: reducing parasitic parameters, enhancing heat dissipation and strengthening insulation.

[0003] In a power semiconductor disclosed in CN102790043A and a power semiconductor device package disclosed in CN118398570A, an independent NTC resistor is used as a temperature detector, and there is a temperature difference of 20 to 30°C between the temperature of the NTC resistor and the temperature of the chip. Although the plastic package can be dissolved in advance, and then the curve of the NTC resistance value and the chip junction temperature can be calibrated with an infrared imager, this solution is relatively complicated and not suitable for large-scale production. In addition, the function of the current sensor is not integrated in these two public patents, making it difficult for circuit engineers to estimate the output current of the chip under actual working conditions (the purpose of monitoring the junction temperature of the chip is also to estimate the output current of the chip when it is working), and the module is not convenient when actually used. Utility Model Content

[0004] Technical purpose: In view of the deficiencies of the above-mentioned devices, the utility model provides a power semiconductor device with integrated sensors. By integrating current sensors and / or temperature sensors in power semiconductor units, current and / or junction temperature detection of power semiconductor wafers can be achieved, thereby facilitating the expanded application of power semiconductor devices.

[0005] Technical solution: In order to achieve the above technical objectives, the utility model adopts the following technical solution.

[0006] A power semiconductor device with integrated sensor, comprising: a substrate, a power semiconductor wafer, a power terminal and a signal terminal;

[0007] The substrate is used to provide circuit connection and mechanical support for the power semiconductor wafer, power terminals, and signal terminals; the electrodes on the power semiconductor wafer are electrically connected to the power terminals and signal terminals through the substrate, and the power terminals and signal terminals are folded upward in a direction away from the power semiconductor wafer; the power semiconductor wafer includes a plurality of power semiconductor units, each of which includes a plurality of power semiconductor cells, current sensors and / or temperature sensors.

[0008] The power terminals are located on one side of the substrate, and the signal terminals are located on the other side of the substrate;

[0009] The signal terminal includes a first signal terminal and a second signal terminal, the first signal terminal is used to lead out the source and drain on the power semiconductor wafer, and the second signal terminal is used to lead out the source, gate, temperature sensor electrode and / or current sensor electrode on the power semiconductor wafer.

[0010] Preferably, the current sensor is located in a power semiconductor unit, the source electrodes of some power semiconductor cells among a plurality of power semiconductor cells are isolated from the source electrodes of other power semiconductor cells, the isolated power semiconductor cells are current sensors, and the source electrodes of the isolated power semiconductor cells are current sensor electrodes.

[0011] Preferably, the single-side width of the current sensor is not less than the width of 5 power semiconductor cells.

[0012] Preferably, the ratio of the area of ​​the current sensor to the area of ​​all power semiconductor cells in the power semiconductor unit is 1:50-1:5.

[0013] Preferably, the temperature sensor is located in the power semiconductor unit, some of the power semiconductor cells are temperature sensors, and the functional areas on the drift area of ​​the power semiconductor cells corresponding to the temperature sensor are a Pwell injection area and two unconnected P+ injection areas, and the P+ injection area is located in the Pwell injection area; an ohmic contact metal is provided on the upper surface of each P+ injection area, the two ohmic contact metals are unconnected, and an insulating layer is covered on the upper surface of the P+ injection area and on both sides of the ohmic contact metal; electrodes are respectively provided on the two ohmic contact metals as temperature sensor electrodes.

[0014] Preferably, in the power semiconductor unit, the source electrode forms an xy plane from a top-down perspective. In the xy plane, the two electrode connection lines of the temperature sensor are defined as the long side, i.e., the x direction, and the electrode width perpendicular to the long side is defined as the short side, i.e., the y direction. The length ratio of the long side to the short side is 2:1~5:1.

[0015] Preferably, in the power semiconductor unit, the source electrode forms an xy plane from a top view, and in the xy plane, the two electrode connection lines of the temperature sensor are defined as the long side, i.e., the x direction. In the x direction, the spacing between the two electrodes of the temperature sensor is not less than 10 power semiconductor cell widths.

[0016] Preferably, when the current sensor and the temperature sensor are integrated into one power semiconductor unit, the shortest distance between the current sensor and the temperature sensor is not less than 0.3 times the shortest side length of the active area of ​​the power semiconductor unit.

[0017] Preferably, the utility model further comprises a plastic package, which encapsulates the substrate, the power semiconductor wafer and part of the power terminals and part of the signal terminals, wherein the part of the power terminals and part of the signal terminals refer to the part connected to the substrate below the terminal bend.

[0018] Preferably, when the power terminal is located on one side of the substrate and the signal terminal is located on the other side of the substrate, the power terminal and the signal terminal are arranged adjacent to each other or opposite to each other.

[0019] Preferably, a conductive layer is attached to the substrate, a power semiconductor wafer is fixedly arranged on the conductive layer, and electrodes on the power semiconductor wafer are electrically connected to the power terminals and the signal terminals through the conductive layer.

[0020] Preferably, the substrate comprises an insulating plate, on which a conductive layer is fixedly arranged, the conductive layer is a plurality of disconnected conductive units, on which power semiconductor wafers, power terminals and signal terminals are arranged.

[0021] Beneficial effects:

[0022] (1) The signal terminal of the utility model includes a temperature sensor electrode and a current sensor electrode, which realizes the real-time monitoring of the junction temperature and current of the power semiconductor device when it is working. The temperature sensor directly detects the junction temperature of the power semiconductor unit. Compared with the temperature detection using thermistors in the prior art, there is no temperature difference between the temperature detected by the temperature sensor and the junction temperature of the power semiconductor unit, which is convenient for the expansion of the application of power semiconductor devices and more conducive to the practical application of circuit engineers.

[0023] (2) The utility model provides two types of connection terminals, power terminals and signal terminals, respectively, which reduces crosstalk between signals;

[0024] (3) The utility model achieves top heat dissipation by folding the power terminals and the signal terminals upward in a direction away from the power semiconductor wafer, thereby solving the problem of poor heat dissipation on the back of the surface-mount device and being more conducive to the electronic components outputting greater power. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic structural diagram of a power semiconductor device with integrated sensor according to Example 1;

[0026] Figure 2 This is a schematic diagram of a power semiconductor device with integrated sensor after packaging according to Embodiment 1;

[0027] Figure 3 A manufacturing flow chart of a power semiconductor device with integrated sensor according to Example 1;

[0028] Figure 4A schematic diagram of a current sensor of a power semiconductor unit in a power semiconductor device with integrated sensor according to Embodiment 1;

[0029] Figure 5 A schematic diagram of a temperature sensor of a power semiconductor unit in a power semiconductor device with integrated sensor according to Embodiment 1;

[0030] Figure 6 This is a schematic diagram of a front electrode of a power semiconductor unit in a power semiconductor device with integrated sensor according to Example 1;

[0031] Explanation of the reference numerals: 1. substrate; 2. first conductive unit; 3. second conductive unit; 4. third conductive unit; 5. fourth conductive unit; 6. fifth conductive unit; 7. sixth conductive unit; 8. seventh conductive unit; 9. eighth conductive unit; 10. ninth conductive unit; 11. tenth conductive unit; 12. eleventh conductive unit. DETAILED DESCRIPTION

[0032] The following is a further explanation and description of a power semiconductor device with integrated sensor of the present invention in conjunction with the accompanying drawings and embodiments.

[0033] The embodiments are only used to illustrate the present invention and do not limit the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0034] In addition, in the description of the present invention, it should be noted that the orientation or position relationship indicated by the spatial relationship terms "center", "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0035] The embodiments of the present application do not specifically limit the specific application scenarios of power semiconductor devices. For example, they can be applied to power supply systems, where the power supply system can be a photovoltaic power generation system, a wind power system or an energy storage system. In addition, they can also be applied to charging piles of electric vehicles or chargers or motor drivers of electric vehicles, such as the charging circuit inside the charging pile. Generally, the charging circuit includes a power converter, and the power converter may include a DC / DC conversion circuit and an AC / DC conversion circuit (rectifier circuit). These conversion circuits generally include power semiconductor devices. In addition, it can also be applied to power supplies for data centers or artificial intelligence (AI, Artificial Intelligence).

[0036] Example 1

[0037] As attached Figure 1 -Attached Figure 2 As shown, a power semiconductor device with integrated sensor in this embodiment includes a substrate 1, a power semiconductor wafer, a power terminal, a signal terminal and a plastic package; the substrate 1 is a packaging substrate of the power semiconductor device, and a DBC substrate or other substrates can be used.

[0038] The substrate 1 is used to provide circuit connection and mechanical support for the power semiconductor wafer, power terminals, and signal terminals; a conductive layer is attached to the substrate 1, a power semiconductor wafer is fixed on the conductive layer, the electrodes on the power semiconductor wafer are electrically connected to the power terminals and signal terminals through the conductive layer, and the power terminals and signal terminals are folded upward in a direction away from the power semiconductor wafer; the plastic package wraps the substrate 1, the power semiconductor wafer, and part of the power terminals and part of the signal terminals, and part of the power terminals and part of the signal terminals refer to the part connected to the substrate below the bend of the pins. The plastic package is used to provide mechanical protection and sealing to prevent oxygen and water vapor;

[0039] In some other embodiments of the present invention, the size of the injection molded body is 27 mm×25 mm×6 mm.

[0040] The signal terminal includes a first signal terminal and a second signal terminal, wherein the first signal terminal is used to lead out the source and drain on the power semiconductor wafer, and the second signal terminal is used to lead out the source, gate, temperature sensor electrode and / or current sensor electrode on the power semiconductor wafer. The power terminal is located on one side of the substrate, and the signal terminal is located on the other side of the DBC substrate. The power terminal and the signal terminal can be arranged adjacently or oppositely, depending on the actual situation.

[0041] The conductive layer is fixed to the power terminal and the signal terminal by welding with PbSnAg solder;

[0042] The electrodes on the power semiconductor wafer include a source, a drain, a gate, a current sensor electrode and / or a temperature sensor electrode; the power semiconductor wafer includes a plurality of power semiconductor units, which can be one, two, or more, and the number can be set according to the actual application scenario.

[0043] Each power semiconductor unit includes a plurality of power semiconductor cells, a current sensor and / or a temperature sensor;

[0044] As attached Figure 4 As shown, the current sensor is located in a power semiconductor unit, the source of some power semiconductor cells in a plurality of power semiconductor cells is isolated from the source of other power semiconductor cells, the separated part of the power semiconductor cells is a current sensor, the source of the separated part of the power semiconductor cells is a current sensor electrode, and the structural manufacturing process of the current sensor is: on the basis of the existing plurality of power semiconductor cells, a current sensor electrode is separately manufactured, and the source of a small number of power semiconductor cells is isolated from the source of other power semiconductor cells as a current sensor electrode, and the current of the current sensor is proportional to the source current, and the ratio can be estimated by the ratio of the isolated cells to the total cells under normal circumstances. The output of the current sensor electrode is a pin; the single side width of the current sensor is not less than the width of 5 power semiconductor cells, which is used to ensure a certain current carrying capacity and prevent the current from being too small; the single side of the current sensor refers to the xy plane formed in the top view of the source in the power semiconductor unit, and the single side width of the current sensor in the x direction and the y direction is not less than the width of 5 power semiconductor cells. The ratio of the current sensor area to the area of ​​all power semiconductor cells in the power semiconductor unit is 1:50~1:5. The lower limit is used to ensure a certain current flow capacity to prevent the current from being too small; the upper limit is used to avoid occupying too much space.

[0045] As attached Figure 5As shown, the temperature sensor is located in the power semiconductor unit, some of the power semiconductor cells in the several power semiconductor cells are temperature sensors, and the functional areas on the drift area of ​​the power semiconductor cells corresponding to the temperature sensor are a Pwell injection area and two unconnected P+ injection areas, and the P+ injection area is located in the Pwell injection area; an ohmic contact metal is arranged on the upper surface of each P+ injection area, and the two ohmic contact metals are unconnected, and an insulating layer is covered on the upper surface of the P+ injection area and on both sides of the ohmic contact metal; electrodes are respectively arranged above the two ohmic contact metals as temperature sensor electrodes; the structural manufacturing process of the temperature sensor is: temperature sensor electrodes are separately manufactured on the basis of several existing power semiconductor cells, and the functional areas of some power semiconductor cells are replaced by continuous large-area Pw The Pwell injection area and two unconnected P+ injection areas, the P+ injection area is located in the Pwell injection area; the functional area of ​​the power semiconductor cell refers to other structures except the drain, substrate, epitaxial layer, ohmic contact metal and thickened metal; each P+ injection area has an ohmic contact metal on the upper surface, the two ohmic contact metals are unconnected, the ohmic contact metal is P-type, and the upper surface of the P+ injection area and both sides of the ohmic contact metal are covered with an insulating layer; electrodes are provided above the two ohmic contact metals as temperature sensor electrodes, and the temperature sensor electrodes are isolated from the source and gate of other power semiconductor cells; the temperature sensor can detect the temperature of the power semiconductor device in real time by detecting the resistance value of the doped resistor in the Pwell area. Its working principle is the same as the temperature detection principle of thermistor, which will not be repeated here. The temperature sensor electrode output is two pins.

[0046] In the power semiconductor unit, the source electrode forms an xy plane from a top-down perspective. In the xy plane, the two electrode connection lines of the temperature sensor are defined as the long side, i.e., the x direction. The electrode width perpendicular to the long side is defined as the short side, i.e., the y direction. The length ratio of the long side to the short side is 2:1~5:1, which is used to ensure a certain effective length for observing resistance changes. In the x direction, the spacing between the two electrodes of the temperature sensor is not less than 10 power semiconductor cell widths, which is used to ensure a certain effective length for observing resistance changes.

[0047] Both the current sensor and the temperature sensor are arranged in the active area of ​​the power semiconductor unit, also called the chip active area. When the current sensor and the temperature sensor are integrated into a power semiconductor unit, the shortest distance between the current sensor and the temperature sensor is not less than 0.3 times the shortest side length of the chip active area to avoid signal crosstalk.

[0048] In this embodiment, a conductive layer is attached to the substrate 1, and the conductive layer includes a first conductive unit 2, a second conductive unit 3, a third conductive unit 4, a fourth conductive unit 5, a fifth conductive unit 6, a sixth conductive unit 7, a seventh conductive unit 8, an eighth conductive unit 9, a ninth conductive unit 10, a tenth conductive unit 11, and an eleventh conductive unit 12; the first conductive unit 2, the second conductive unit 3 and the third conductive unit 4 are adjacent and located on one side of the surface of the substrate 1, the fourth conductive unit 5, the fifth conductive unit 6, the sixth conductive unit 7, the seventh conductive unit 8, the eighth conductive unit 9, the ninth conductive unit 10, the tenth conductive unit 11, and the eleventh conductive unit 12 are located on the other side of the surface of the substrate 1, and are adjacent to the fourth conductive unit 5 and the first conductive unit 2 and the third conductive unit 4; the fourth conductive unit 5, the fifth conductive unit 6, the sixth conductive unit 7, the seventh conductive unit 8, the eighth conductive unit 9, the ninth conductive unit 10, the tenth conductive unit 11, and the eleventh conductive unit 12 are not connected to each other. The substrate 1 also includes an insulating plate, and the conductive layer is fixedly arranged on the insulating ceramic plate. The insulating plate can use an insulating ceramic plate or an insulating plate of other insulating materials.

[0049] The edges of the first conductive unit 2, the third conductive unit 4, the fourth conductive unit 5, the fifth conductive unit 6, the sixth conductive unit 7, the seventh conductive unit 8, the eighth conductive unit 9, the ninth conductive unit 10, the tenth conductive unit 11 and the eleventh conductive unit 12 have through holes for relieving stress;

[0050] The power semiconductor wafer includes a first silicon carbide device N1 and a second silicon carbide device N2, wherein the first silicon carbide device N1 constitutes an upper bridge arm, and the second silicon carbide device N2 constitutes a lower bridge arm, and the power semiconductor wafer realizes a full-bridge function; the first silicon carbide device N1 is placed on the first conductive unit 2, and the second silicon carbide device N2 is placed on the third conductive unit 4; the first silicon carbide device N1, the second silicon carbide device N2, the first conductive unit 2, and the third conductive unit 4 are fixed by welding with PbSnAg solder; the first conductive unit 2 is provided with four positioning grooves around the first silicon carbide device N1, and the third conductive unit 4 is provided with four positioning grooves around the second silicon carbide device N2, and the positioning grooves are used to realize the position positioning of the silicon carbide device on the conductive unit;

[0051] The drain of the first silicon carbide device N1 is led out through the first power terminal S1 via the first conductive unit 2, and the drain of the second silicon carbide device N2 is led out through the third power terminal S3 via the third conductive unit 4; the second conductive unit 3 is electrically connected to the third conductive unit 4, and the source of the second silicon carbide device N2 is led out through the second power terminal S2 after passing through the third conductive unit 4 and the second conductive unit 3 in sequence; the first power terminal S1 is in contact with the drain of the first silicon carbide device N1, the third power terminal S3 is in contact with the drain of the second silicon carbide device N2, and the second power terminal S2 is in contact with the source of the second silicon carbide device N2. The first power terminal S1, the second power terminal S2, and the third power terminal S3 are located on one side of the substrate 1;

[0052] The source of the first silicon carbide device N1 is connected to the third conductive unit 4 through four 12 mil aluminum wires, and the source of the second silicon carbide device N2 is connected to the second conductive unit 3 through four 12 mil aluminum wires;

[0053] The first conductive unit 2 is electrically connected to the eleventh conductive unit 12, and the source of the first silicon carbide device N1 is led out through the fourth signal terminal S4 after passing through the first conductive unit 2 and the eleventh conductive unit 12 in sequence; the fourth signal terminal S4 is also a Kelvin pin; the first silicon carbide device N1 is connected to the eleventh conductive unit 12 through a 12mil aluminum wire;

[0054] The third conductive unit 4 is electrically connected to the fourth conductive unit 5, and the source of the second silicon carbide device N2 is led out through the third conductive unit 4 and the fourth conductive unit 5 in sequence through the eleventh signal terminal S11; the eleventh signal terminal S11 is also a Kelvin pin; the second silicon carbide device N2 is connected to the fourth conductive unit 5 through a 12mil aluminum wire;

[0055] The first conductive unit 2 is electrically connected to the tenth conductive unit 11, and the gate of the first silicon carbide device N1 is led out through the fifth signal terminal S5 after passing through the first conductive unit 2 and the tenth conductive unit 11 in sequence; the first silicon carbide device N1 is connected to the tenth conductive unit 11 through a 5mil aluminum wire;

[0056] The third conductive unit 4 is electrically connected to the fifth conductive unit 6, and the gate of the second silicon carbide device N2 is led out through the third conductive unit 4 and the fifth conductive unit 6 in sequence through the tenth signal terminal S10; the second silicon carbide device N2 is connected to the fifth conductive unit 6 through a 5mil aluminum wire;

[0057] The sixth signal terminal S6, the seventh signal terminal S7, the eighth signal terminal S8, and the ninth signal terminal S9 are respectively located on the ninth conductive unit 10, the eighth conductive unit 9, the seventh conductive unit 8, and the sixth conductive unit 7. The seventh conductive unit 8 and the sixth conductive unit 7 are electrically connected to the third conductive unit 4. The ninth conductive unit 10 and the eighth conductive unit 9 are electrically connected to the first conductive unit 2. The temperature sensor pin and the current sensor pin of the first silicon carbide device N1 are respectively led out through the sixth signal terminal and the seventh signal terminal. The temperature sensor pin and the current sensor pin of the second silicon carbide device N2 are respectively led out through the eighth signal terminal and the ninth signal terminal. The sixth signal terminal, the seventh signal terminal, the eighth signal terminal, and the ninth signal terminal are used to realize three functions: empty connection, temperature sensor, or current sensor. The schematic diagram of the front electrode of the power semiconductor unit is shown in the attached figure. Figure 6 shown.

[0058] For example, when it is necessary to monitor the temperature of two silicon carbide devices separately, the ninth signal terminal S9 and the eighth signal terminal S8 can be used to monitor the junction temperature of the first silicon carbide device N1, and the sixth signal terminal S6 and the seventh signal terminal S7 can be used to monitor the junction temperature of the second silicon carbide device N2. When it is necessary to monitor the temperature of one silicon carbide device and the current of another silicon carbide device separately, the ninth signal terminal S9 and the eighth signal terminal S8 can be used to monitor the junction temperature of the first silicon carbide device N1, the sixth signal terminal S6 can be used to monitor the current of the second silicon carbide device N2, and the seventh signal terminal S7 can be left unconnected. At this time, the eighth conductive unit 9 does not need to be electrically connected to the first conductive unit 2. When it is necessary to monitor the current of two silicon carbide devices separately, the ninth signal terminal S9 can be used to monitor the current of the first silicon carbide device N1, the sixth signal terminal S6 can be used to monitor the current of the second silicon carbide device N2, the eighth signal terminal S8 and the seventh signal terminal S7 can be left unconnected. At this time, the eighth conductive unit 9 does not need to be electrically connected to the first conductive unit 2, and the seventh conductive unit 8 is electrically connected to the third conductive unit 4. When it is necessary to monitor the temperature and current of a silicon carbide device and the current of another silicon carbide device respectively, the ninth signal terminal S9 and the eighth signal terminal S8 can be used to monitor the junction temperature of the first silicon carbide device N1, the seventh signal terminal S7 can monitor the current of the first silicon carbide device N1, and the sixth signal terminal S6 can be used to monitor the current of the second silicon carbide device N2. In addition to the above examples, the use of the sixth signal terminal, the seventh signal terminal, the eighth signal terminal, and the ninth signal terminal can be combined according to actual requirements, which will not be described in detail here.

[0059] As attached Figure 3 As shown, this embodiment also discloses a method for manufacturing a power semiconductor device with an integrated sensor, comprising the following steps:

[0060] S1. Prepare substrate 1: substrate 1 is a DBC substrate, substrate 1 is attached with a conductive layer, in this embodiment, the conductive layer is a copper layer; substrate 1 is copper-clad on both sides, the upper surface is divided into a first conductive unit 2, a second conductive unit 3, a third conductive unit 4, a fourth conductive unit 5, a fifth conductive unit 6, a sixth conductive unit 7, a seventh conductive unit 8, an eighth conductive unit 9, a ninth conductive unit 10, a tenth conductive unit 11, and an eleventh conductive unit 12, and the lower surface is a whole copper layer;

[0061] S2. Place solder, power semiconductor wafer, power terminal and signal terminal: according to the position of the positioning hole on the inner copper layer, place solder, power semiconductor wafer, power terminal and signal terminal in the corresponding position on the first conductive unit 2, the second conductive unit 3, the third conductive unit 4, the fourth conductive unit 5, the fifth conductive unit 6, the sixth conductive unit 7, the seventh conductive unit 8, the eighth conductive unit 9, the ninth conductive unit 10, the tenth conductive unit 11 and the eleventh conductive unit 12 in sequence, and place a pressing block on the power terminal and the signal terminal to fix the terminal position;

[0062] S3, welding: placing the substrate 1 with the mounted power semiconductor wafer, power terminals and signal terminals in a sintering furnace, with the sintering temperature being 330-370°C at the highest, and the highest temperature being maintained for 10-20s. During sintering, vacuum is first drawn, and then nitrogen and formic acid are passed;

[0063] S4, X-ray inspection: Use X-ray to check the welding quality of power semiconductor wafers, power terminals and signal terminals, and the welding void rate is required to be less than 1%;

[0064] S5. Wire bonding: placing the substrate 1 in a bonding machine, and bonding is performed using appropriate bonding parameters according to the wiring diagram, wherein the source of the first silicon carbide device N1 is connected to the third conductive unit 4 through four 12mil aluminum wires, the source of the first silicon carbide device N1 is connected to the eleventh conductive unit 12 through one 12mil aluminum wire, the gate of the first silicon carbide device N1 is connected to the tenth conductive unit 11 through one 5mil aluminum wire, the source of the second silicon carbide device N2 is connected to the second conductive unit 3 through four 12mil aluminum wires, the source of the second silicon carbide device N2 is connected to the fourth conductive unit 5 through one 12mil aluminum wire, and the second silicon carbide device N2 is connected to the fifth conductive unit 6 through one 5mil aluminum wire. If the current sensor function is required, the current sensor terminal of the first silicon carbide device N1 is connected to the ninth conductive unit 10 through a 12mil aluminum wire, the current sensor terminal of the second silicon carbide device N2 is connected to the sixth conductive unit 7 through a 12mil aluminum wire, and the seventh conductive unit 8 and the eighth conductive unit 9 are not connected. If the temperature sensor function is required, the temperature sensor terminal of the first silicon carbide device N1 is connected to the ninth conductive unit 10 and the eighth conductive unit 9 through two 12mil aluminum wires, and the temperature sensor terminal of the second silicon carbide device N2 is connected to the seventh conductive unit 8 and the sixth conductive unit 7 through two 12mil aluminum wires. If the current sensor or temperature sensor is not required, the sixth conductive unit 7, the seventh conductive unit 8, the eighth conductive unit 9, and the ninth conductive unit 10 are not connected;

[0065] S6, Bonding test: Push-pull force test is performed to test the bonding strength of the bonding wire. The bonding strength between 12mil aluminum wire and copper layer is required to be greater than 1000g, the bonding strength between 12mil aluminum wire and silicon carbide device is required to be greater than 800g, the bonding strength between 5mil aluminum wire and copper layer is required to be greater than 100g, and the bonding strength between 5mil aluminum wire and silicon carbide device is required to be greater than 100g.

[0066] S6, injection molding: placing the substrate 1 in a press for injection molding, and performing post-curing at 175° C. after injection molding;

[0067] S7, tinning of pins: putting the injection molded body into the electroplating solution to electroplate metal tin;

[0068] S9, rib cutting and forming: cut off the excess injection plastic between the pins outside the frame and connected to the frame, and then bend the terminals.

[0069] The manufacturing method in this embodiment has relatively low process requirements and can be mass-produced.

[0070] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A power semiconductor device with integrated sensor, characterized in that: include: Substrates, power semiconductor wafers, power terminals and signal terminals; The substrate is used to provide circuit connection and mechanical support for the power semiconductor wafer, power terminals and signal terminals; the electrodes on the power semiconductor wafer are electrically connected to the power terminals and signal terminals through the substrate, and the power terminals and signal terminals are folded upward in a direction away from the power semiconductor wafer; the power semiconductor wafer includes a plurality of power semiconductor units, each of which includes a plurality of power semiconductor cells, current sensors and / or temperature sensors; The power terminal is located on one side of the substrate, and the signal terminal is located on the other side of the substrate; the signal terminal includes a first signal terminal and a second signal terminal, the first signal terminal is used to lead out the source and drain on the power semiconductor wafer, and the second signal terminal is used to lead out the source, gate, temperature sensor electrode and / or current sensor electrode on the power semiconductor wafer.

2. The power semiconductor device with integrated sensor according to claim 1, characterized in that: The current sensor is located in a power semiconductor unit, the source electrodes of some power semiconductor cells among a plurality of power semiconductor cells are isolated from the source electrodes of other power semiconductor cells, the isolated power semiconductor cells are current sensors, and the source electrodes of some power semiconductor cells are current sensor electrodes.

3. The power semiconductor device with integrated sensor according to claim 2, characterized in that: The single side width of the current sensor is not less than the width of 5 power semiconductor cells.

4. The power semiconductor device with integrated sensor according to claim 2, characterized in that: The ratio of the area of ​​the current sensor to the area of ​​all power semiconductor cells in the power semiconductor unit is 1:50-1:

5.

5. The power semiconductor device with integrated sensor according to claim 1, characterized in that: The temperature sensor is located in the power semiconductor unit, some of the power semiconductor cells are temperature sensors, and the functional areas on the drift area of ​​the power semiconductor cells corresponding to the temperature sensor are a Pwell injection area and two unconnected P+ injection areas, and the P+ injection area is located in the Pwell injection area; an ohmic contact metal is provided on the upper surface of each P+ injection area, the two ohmic contact metals are unconnected, and an insulating layer is covered on the upper surface of the P+ injection area and on both sides of the ohmic contact metal; electrodes are respectively provided on the two ohmic contact metals as temperature sensor electrodes.

6. The power semiconductor device with integrated sensor according to claim 5, characterized in that: In the power semiconductor unit, the source electrode forms an xy plane from a top-down perspective. In the xy plane, the two electrode connection lines of the temperature sensor are defined as the long side, i.e., the x direction, and the electrode width perpendicular to the long side is defined as the short side, i.e., the y direction. The length ratio of the long side to the short side is 2:1~5:

1.

7. The power semiconductor device with integrated sensor according to claim 5, characterized in that: In the power semiconductor unit, the source electrode forms an xy plane from a top-down perspective. In the xy plane, the two electrode connection lines of the temperature sensor are defined as the long side, i.e., the x direction. In the x direction, the spacing between the two electrodes of the temperature sensor is not less than 10 power semiconductor cell widths.

8. The power semiconductor device with integrated sensor according to claim 1, characterized in that: When the current sensor and the temperature sensor are integrated into one power semiconductor unit, the shortest distance between the current sensor and the temperature sensor is not less than 0.3 times the shortest side length of the active area of ​​the power semiconductor unit.

9. The power semiconductor device with integrated sensor according to claim 1, characterized in that: It also includes a plastic package, which wraps the substrate, the power semiconductor wafer, and part of the power terminals and part of the signal terminals. The part of the power terminals and part of the signal terminals refer to the parts connected to the substrate below the terminal bend.

10. The power semiconductor device with integrated sensor according to claim 1, characterized in that: When the power terminal is located on one side of the substrate and the signal terminal is located on the other side of the substrate, the power terminal and the signal terminal are arranged adjacent to each other or opposite to each other.

11. The power semiconductor device with integrated sensor according to claim 1, characterized in that: A conductive layer is attached to the substrate, a power semiconductor wafer is fixedly arranged on the conductive layer, and electrodes on the power semiconductor wafer are electrically connected to power terminals and signal terminals through the conductive layer.

12. The sensor-integrated power semiconductor device according to claim 11, characterized in that: The substrate comprises an insulating plate, on which a conductive layer is fixedly arranged, the conductive layer is composed of a plurality of unconnected conductive units, on which power semiconductor wafers, power terminals and signal terminals are arranged.

Images