Integrated semiconductor stacked structure device
By growing the reflective layer on the integrated semiconductor carrier metal layer and semiconductor chip, the problem of multi-faceted incomplete protection in the prior art is solved, long-term protection and light efficiency improvement are achieved, cost reduction and operation simplified.
Patent Information
- Application Number
- CN202420488300.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-14
- Publication Date
- 2025-02-07
- Estimated Expiration
- 2034-03-14
AI Technical Summary
There are multiple problems of incomplete protection of existing light emitting diodes and semiconductor devices in terms of protection, and existing protection methods such as sandblasting and white glue dispensing cannot effectively improve the brightness and light efficiency of the device, and are costly.
By growing a reflective layer with high light output on the integrated semiconductor carrier metal layer and the semiconductor chip, overall protection on the six-sided side is achieved and the light output of the carrier and semiconductor chip is improved.
It has achieved long-term anti-sulfurization and carbonization, while improving the light output and light efficiency of carriers and semiconductor chips, reducing production costs, and simplifying the operation process.
Smart Images
Figure CN222442203U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to an integrated semiconductor stacking structure device. Background Art
[0002] Most of the existing light-emitting diodes and semiconductors are shipped as single devices; even if a small part is made into devices, the devices are not given secondary protection, resulting in problems such as sulfurization, carbonization, and protection.
[0003] In existing light-emitting diodes or semiconductors, when preventing them from sulfidation and carbonization, a single-component anti-sulfidation agent is often used to dispense glue in the product cup or spray after the product is packaged. Both methods involve the protection of the anti-sulfidation agent, environmental pollution protection, and personnel operation protection. In addition, the existing anti-sulfidation agent generally evaporates after 1000 hours of use, thus becoming ineffective. The anti-sulfidation agent can only hinder and protect against damage from other reactive substances (such as sulfur, carbon, high temperature, etc.) in the short term.
[0004] In existing light-emitting diodes or semiconductors, sandblasting cannot improve the reflected light of the carrier, nor can it improve the light output rate of the semiconductor chip, so the brightness and light efficiency are not improved. Therefore, sandblasting cannot improve the brightness and light efficiency and will increase the cost.
[0005] In existing light-emitting diodes or semiconductors, white glue is dotted into the cup-shaped product to prevent the carrier layer from being damaged by external corrosive substances. However, this method will cause the white glue to adhere to the semiconductor chip or light-emitting diode on the side, thereby reducing the brightness and light output angle of the product.
[0006] When using anti-sulfurization agents, sandblasting, white glue and other methods for protection, only one corresponding surface can be protected, and it is impossible to achieve overall protection of the six surfaces.
[0007] Therefore, there is an urgent need for an integrated semiconductor stacked structure device that can achieve long-term anti-sulfurization and carbonization while improving the reflected light of the carrier and the light output rate of the semiconductor chip. Utility Model Content
[0008] The purpose of the utility model is to provide an integrated semiconductor stacked structure device, which can achieve long-term anti-sulfurization and carbonization while improving the reflected light of the carrier and the light output rate of the semiconductor chip by growing a material with a higher light output rate than the carrier, i.e., a reflective layer, on the metal layer of the integrated semiconductor carrier and on the semiconductor chip or semiconductor device.
[0009] To achieve the above purpose, the utility model provides the following solutions:
[0010] An integrated semiconductor stacked structure device comprises a carrier layer, a circuit layer, a metal layer module and a semiconductor module which are stacked in sequence from bottom to top; the semiconductor module comprises a plurality of semiconductor components;
[0011] The circuit layer includes electrodes of a plurality of semiconductor components, wherein the positive electrode of each semiconductor component is connected to the negative electrode of the adjacent semiconductor component;
[0012] The metal layer module includes one anti-migration metal layer or a plurality of anti-migration metal layers stacked in sequence from bottom to top;
[0013] A chip metal layer is also provided on the metal layer module of the first region and the second region; the first region is the region between the semiconductor component and its corresponding positive electrode; the second region is the region between the semiconductor component and its corresponding negative electrode;
[0014] A reflective layer is disposed on the metal layer module and the semiconductor component, or a reflective layer is disposed in a region between adjacent semiconductor components.
[0015] Optionally, the semiconductor component is a semiconductor chip or an electronic component; the electronic component is arranged in the left and right end regions of the carrier layer; and the semiconductor chip is arranged in the region between the left end region and the right end region.
[0016] Optionally, the semiconductor module further includes a protective layer; the protective layer is arranged on the light-transmitting layer of the semiconductor chip.
[0017] Optionally, the integrated semiconductor stacked structure device further includes a protective layer; the protective layer covers the reflective layer.
[0018] Optionally, the integrated semiconductor stacking structure device further includes a sidewall barrier layer; the sidewall barrier layer is disposed on the sidewall of the integrated semiconductor stacking structure device.
[0019] Optionally, the migration prevention metal layer is a nickel-plated layer, a palladium-plated layer, a gold-plated layer or a silver-plated layer.
[0020] Optionally, the chip metal layer is a gold-tin alloy layer, a silver layer or a tin layer.
[0021] Optionally, the thickness of the anti-migration metal layer ranges from 0.005 um to 2 mm.
[0022] Optionally, the thickness of the reflective layer ranges from 1 nm to 1 cm.
[0023] According to the specific embodiments provided by the utility model, the utility model discloses the following technical effects: the utility model provides an integrated semiconductor stacking structure device, including a carrier layer, a circuit layer, a metal layer module and a semiconductor module stacked from bottom to top; the semiconductor module includes a plurality of semiconductor components; the circuit layer includes electrodes of a plurality of semiconductor components, wherein the positive electrode of each semiconductor component is connected to the negative electrode of its adjacent semiconductor component; the metal layer module includes an anti-migration metal layer or a plurality of anti-migration metal layers stacked from bottom to top; a chip metal layer is also provided on the metal layer module in the first region and the second region; the first region is the region between the semiconductor component and its corresponding positive electrode; the second region is the region between the semiconductor component and its corresponding negative electrode; a reflective layer is provided in the region between adjacent semiconductor components. The utility model realizes the combination and heat transfer of the positive electrode, the negative electrode and the semiconductor module through the chip metal layer; by covering the reflective layer on the semiconductor module, the light output brightness can be increased, thereby improving the light efficiency and the light output rate of the semiconductor module, and can achieve long-term anti-sulfurization and anti-carbonization, green and environmentally friendly, and simple to operate. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0025] Figure 1 This is a front view of the integrated semiconductor stacked structure device provided by the utility model;
[0026] Figure 2 A top view of the integrated semiconductor stacked structure device provided by the utility model;
[0027] Figure 3 It is an enlarged schematic diagram of part A in the top view of the integrated semiconductor stacked structure device provided by the utility model.
[0028] Explanation of symbols:
[0029] Carrier layer-S100; circuit layer-S101; first metal layer-S102; second metal layer-S103; reflective layer-S104; protective layer-S105; side wall barrier layer-S106; semiconductor chip-S200; chip metal layer-S300; protective layer-S400; electronic components-S500. DETAILED DESCRIPTION
[0030] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0031] The purpose of the utility model is to provide an integrated semiconductor stacked structure device, which forms reflection between the material on the surface of the carrier and the chip to increase the brightness of the light, thereby improving the efficiency of light; grow materials on the semiconductor chip, form refraction between the chip and the protective layer or air, thereby improving the light output between the protective layer or the air, thereby improving the light output rate of the semiconductor chip itself, while achieving long-term anti-sulfurization and anti-carbonization, and being green and environmentally friendly. In an integrated manner or the semiconductor chip is directly integrated with the cost carrier, the deposition growth method is also used simultaneously to increase the reflectivity and protection of the integrated semiconductor carrier, and simultaneously increase the light output rate and protect the semiconductor chip, semiconductor devices, and electronic components. Thereby, without changing the angle of the product itself, the reliability, brightness, and light efficiency of the product are improved.
[0032] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0033] like Figure 1 As shown, this embodiment provides an integrated semiconductor stacked structure device, including a carrier layer S100, a circuit layer S101, a metal layer module and a semiconductor module stacked in sequence from bottom to top; the semiconductor module includes a plurality of semiconductor components.
[0034] The circuit layer S101 has electrodes of several semiconductor components, wherein the positive electrode of each semiconductor component is connected to the negative electrode of the adjacent semiconductor component.
[0035] A chip metal layer S300 is also provided on the metal layer module of the first region and the second region; the first region is the region between the semiconductor component and its corresponding positive electrode; the second region is the region between the semiconductor component and its corresponding negative electrode.
[0036] The metal layer module includes one anti-migration metal layer or a plurality of anti-migration metal layers stacked in sequence from bottom to top, which is not limited in this embodiment.
[0037] Figure 2 A top view of an integrated semiconductor stacked structure device when the metal layer module includes two migration-preventing metal layers stacked in sequence from bottom to top, Figure 3 for Figure 2The enlarged view of part A in the figure. Figure 3 The middle metal layer module includes two anti-migration metal layers, namely a first metal layer-S102 and a second metal layer-S103.
[0038] The thickness of the anti-migration metal layer ranges from 0.005um to 2mm; the anti-migration metal layer is a nickel-plated layer, a palladium-plated layer, a gold-plated layer or a silver-plated layer, or may be a layer of other materials.
[0039] The chip metal layer S300 is located between the second metal layer S103 and the semiconductor chip S200, and can be bonded with a material of 0.5W / (Mk)-2300W / (Mk) according to the power; the chip metal layer S300 is used to combine and transfer heat between the semiconductor chip S200 and the circuit layer S101, and its thickness can be 1um-30um; the chip metal layer can be a gold-tin alloy layer, a silver layer or a tin layer, any one of which can be selected.
[0040] A reflective layer S104 is disposed on the second metal layer S103 and the semiconductor components, or a reflective layer S104 is disposed in a region between adjacent semiconductor components.
[0041] The semiconductor component is a semiconductor chip S200 or an electronic component S500, and the electronic component S500 is arranged at the left and right end areas of the carrier layer; the semiconductor chip S200 is arranged in the area between the left end area and the right end area. That is, the semiconductor module includes a plurality of semiconductor chips S200 and electronic components S500.
[0042] The semiconductor module further comprises a protective layer S400; the protective layer S400 is arranged on the light-transmitting layer of the semiconductor chip S200. When the protective layer S400 is arranged, a light-transmitting layer may be further covered on the top and side of the protective layer S400.
[0043] If S200 is a semiconductor chip layer directly packaged with a carrier, S400 is a protective layer S400 of S200. If S200 and S400 are semiconductor packaged devices combined with a carrier, then S200 and S400 are considered as one body to obtain a semiconductor packaged device. In this embodiment, there can be 28 semiconductor chips S200 and protective layer S400, and the specific number and arrangement can be designed according to actual requirements. When S200 and S400 are integrated, the thickness of the semiconductor packaged device can be 0.15mm-2cm. When S400 and S200 are not an integrated packaged device, S400 is a protective layer S400 to protect the S200 semiconductor chip S200 from damage. S400 is no less than 1 layer, and the thickness of the protective layer S400 is controlled to be 0.1mm-2cm. In this embodiment, the size of a single semiconductor chip S200 may be 10um*10um-15800*15800um, and the size of a single semiconductor device may be 200*200um-25400*25400ummil.
[0044] Electronic components, i.e. Figure 1 The electronic components of S500 include Figure 1 Devices ①, ②, ③ and ④, circuits and semiconductor devices are superimposed on the carrier layer, which is convenient for users to use directly after purchase. Between the electronic component S500 and the semiconductor device, there is at least a single device circuit control, and the number of electronic components can be adjusted according to the semiconductor chip S200 or the device and application requirements. In this embodiment, the electronic component S500 can be a resistor, a capacitor, an IC and other devices. The electronic component S500 constitutes a power control system. After the current is directly input, the semiconductor chip S200 is lit, and different colors of light are obtained through the protective layer S400.
[0045] The carrier layer S100 is not less than one layer and is made of a high heat dissipation material such as ceramic, resin and silicone resin, etc. The thickness of the carrier is in the range of 0.1mm-1cm. Figure 1 As shown, the carrier layer S100 is a substrate that serves as a carrier. Multiple pieces can be stacked or wired, or a single carrier can be used. The integrated semiconductor carrier layer S100 can be designed as a plane, or can be stacked by selecting materials with a range of 0.5W / (Mk)-2300W / (Mk) and made into a concave-convex cup carrier through a mold, which can be selected according to different design requirements.
[0046] The circuit layer S101 is interconnected with the first metal layer S102, the second metal layer S103, the chip metal layer S300, and the semiconductor chip S200, and the connecting circuits formed by them reasonably connect the electrodes of the component package; the circuit layer S101 can be set to a single-layer or multi-layer structure, and the material of the circuit layer S101 is generally a conductive material, for example, the circuit layer S101 can be copper-plated.
[0047] The first metal layer S102, the second metal layer S103, and the chip metal layer S300 are coatings that conduct the circuit layer S101 and the semiconductor chip S200, and the semiconductor chip S200 is directly connected to the substrate of the integrated semiconductor stacked structure device by manual wire bonding; the first metal layer S102 is a nickel-plated layer or a palladium-plated layer, or can be a layer of other materials. The first metal layer S102 is used to prevent the migration of copper ions and the second metal layer S103 material.
[0048] The second metal layer S103 may be a gold-plated layer or a silver-plated layer. The thickness of the first metal layer S102 and the second metal layer S103 ranges from 0.005 um to 2 mm.
[0049] The first metal layer S102 and the second metal layer S103: their function is to prevent the migration of metal elements in each layer, and there are no less than 2 layers in total.
[0050] In a specific example, the reflective layer S104 can be generated by any of the methods such as deposition growth, plating, dispensing, coating, and spraying. Specifically: 1) On the basis of the second metal layer of the carrier, a reflective material higher than the second metal layer, namely, the reflective layer S104, is grown by any of the methods such as deposition growth, plating, dispensing, coating, and spraying, thereby improving the reflectivity of the second metal layer; 2) A material higher than the semiconductor chip S200 is grown on the semiconductor chip S200, thereby improving the light output rate of the semiconductor chip S200; 3) A material higher than the protective layer S400 is grown on the protective layer S400, thereby improving the light output rate of the protective layer S400; the protective layer S400 can be provided on the light-transmitting layer of one or more semiconductor chips S200 according to product design requirements, so that the semiconductor chip can emit light of different colors. It should be noted that by adopting the above-mentioned generation range of the reflective layer S104, the reflective layer 104 may not be provided in the area between adjacent semiconductor components, that is, Figure 1 Similarly, if the reflective layer 104 is set in the area between adjacent semiconductor components, that is, Figure 1 The reflective layer 104 is provided in the blank portion of the substrate shown in the figure, and the reflective layer S104 is not grown on the second metal layer S103, the semiconductor chip S200 and the protective layer S400.
[0051] The thickness of the reflective layer S104 can range from 1 nm to 1 cm, and the deposition growth is controlled to be at least one layer, and the controlled deposition material is at least one. In this embodiment, the reflective layer S104 can be deposited and grown in multiple layers, each layer can be made of different materials, and at least one layer can be deposited. The deposition material can be silicon dioxide, aluminum oxide, titanium oxide, calcium oxide, etc.
[0052] This embodiment uses deposition growth (including physical growth and chemical growth), coating, 360-degree spraying, etc. to achieve secondary optical reflection, mutual refraction, protection, superposition, etc. During the 360-degree rotation operation, high-temperature glue or blocking objects are required to block the carrier welding pad to avoid cold soldering of the patch.
[0053] The integrated semiconductor stacked structure device may further include a protective layer S105; the protective layer S105 covers the reflective layer S104. The protective layer S105 is a mixed layer, and its material may be a mixture of silicon oxide and titanium dioxide or other dual materials, multi-material mixture, etc. Its material may be added or removed as needed, and the thickness of the protective layer S105 may be 5um-10mm. It should be noted that in this embodiment, the protective layer S105 may also be provided on the reflective layer S104 according to user needs.
[0054] The integrated semiconductor stacking structure device further includes a sidewall barrier layer S106; the sidewall barrier layer S106 is disposed on the sidewall of the integrated semiconductor stacking structure device.
[0055] In this embodiment, a mold can be used to make a retaining wall (side wall retaining layer S106), and the side wall retaining layer S106 can be higher than the integrated semiconductor stacked structure device substrate, or not higher than the integrated semiconductor stacked structure device substrate, so that the semiconductor chip S200 can be reduced or enlarged in angle through the concave and convex of the retaining wall (i.e., the side wall retaining layer S106); if there is a side wall retaining layer S106, according to user needs, it can be selected to deposit and coat a layer of reflective layer S104 outside the side wall retaining layer S106, or not to deposit and coat a layer of reflective layer S104 outside the side wall retaining layer S106; the reflective layer S104 can be deposited and coated as needed. The thickness of the side wall retaining layer S106 can be 0.005um-1cm, and the height can be 0.1um-2cm.
[0056] This embodiment has the following beneficial effects:
[0057] 1. Use any of the methods such as deposition growth, coating, dispensing, coating, and spraying to grow materials with higher light output than the carrier on the integrated semiconductor carrier metal and the semiconductor chip or device; through verification, it can avoid oxidation, carbonization and other adverse effects after contact with air and other external corrosive substances, and enhance the metal's ability to be sulfided and oxidized by sulfur and oxygen in the air.
[0058] 2. Use any of the following methods, such as deposition growth, coating, dispensing, coating, and spraying, to coat the integrated semiconductor carrier metal and semiconductor chips or devices with a material with a higher light output rate than the carrier; deposit and grow materials with a higher reflectivity than the carrier material on the integrated semiconductor carrier; deposit and grow the same materials as on the carrier on the semiconductor chips and semiconductor devices on the integrated semiconductor carrier, but the semiconductor chips and semiconductor devices will increase the refraction effect. Through verification, it is concluded that: 1) the material on the surface of the carrier forms a reflection with the chip, increasing the brightness of the light, thereby improving the efficiency of the light and increasing the reflectivity of the surface layer of the carrier; 2) grow materials on the semiconductor chip, and form refraction between the chip and the protective layer or air, thereby improving the light output between the protective layer or air, thereby improving the light output efficiency of the semiconductor chip itself, that is, the light output rate of the integrated semiconductor chip can be increased without direct refraction with the air, thereby improving the overall brightness and light efficiency of the product.
[0059] 3. Use any of the methods such as deposition growth, plating, dispensing, coating, and spraying to grow materials with a higher light output rate than the carrier on the integrated semiconductor carrier metal and the semiconductor chip or device; it is better than adding spraying anti-sulfurization agent (the anti-sulfurization agent is highly volatile and requires separate exhaust and personnel protection), and has a longer protection time (the anti-sulfurization agent will fail after 1000 hours); it is also more convenient than applying white glue in a cup to the metal layer outside the chip (because it cannot be ensured that the white glue will not climb onto the semiconductor chip, thereby affecting the light output of the chip and reducing the brightness).
[0060] 4. The stacked layer structure can realize the control of a single semiconductor chip or device, or multiple chips or not less than one chip. In addition, it can realize an integrated device combining circuit components and carriers, which is convenient for use and does not require substrate design.
[0061] 5. The integrated circuit board of the integrated semiconductor stacking structure device has components, ICs, resistors, semiconductor devices, semiconductor ICs, semiconductor chips, etc., and the integrated circuit and chip circuit design can be carried out according to needs; the circuit devices and semiconductor chips, light-emitting diodes, and light-emitting diode devices are combined into an integrated semiconductor design to realize single-chip control or multiple-chip control, and the circuit design can be carried out according to requirements.
[0062] 6. By using deposition growth, the six surfaces can be protected. For unwanted positions, high-temperature glue or protective materials can be used to apply them.
[0063] 7. Low production cost, high efficiency, and no need for operator protection.
[0064] This article uses specific examples to illustrate the principles and implementation methods of the utility model. The above examples are only used to help understand the method and core ideas of the utility model. At the same time, for those skilled in the art, according to the ideas of the utility model, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the utility model.
Claims
1. An integrated semiconductor stacking structure device, characterized in that: It includes a carrier layer, a circuit layer, a metal layer module and a semiconductor module which are stacked in sequence from bottom to top; the semiconductor module includes a plurality of semiconductor components; The circuit layer includes electrodes of a plurality of semiconductor components, wherein the positive electrode of each semiconductor component is connected to the negative electrode of the adjacent semiconductor component; The metal layer module includes one anti-migration metal layer or a plurality of anti-migration metal layers stacked in sequence from bottom to top; A chip metal layer is also provided on the metal layer module of the first region and the second region; the first region is the region between the semiconductor component and its corresponding positive electrode; the second region is the region between the semiconductor component and its corresponding negative electrode; A reflective layer is disposed on the metal layer module and the semiconductor component, or a reflective layer is disposed in a region between adjacent semiconductor components.
2. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The semiconductor component is a semiconductor chip or an electronic component; the electronic component is arranged at the left and right end regions of the carrier layer; and the semiconductor chip is arranged in the region between the left end region and the right end region.
3. The integrated semiconductor stacking structure device according to claim 2, characterized in that: The semiconductor module further comprises a protection layer; the protection layer is arranged on the light-transmitting layer of the semiconductor chip.
4. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The integrated semiconductor stacked structure device further includes a protective layer; the protective layer covers the reflective layer.
5. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The integrated semiconductor stacking structure device further comprises a sidewall barrier layer; the sidewall barrier layer is arranged on the sidewall of the integrated semiconductor stacking structure device.
6. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The migration prevention metal layer is a nickel-plated layer, a palladium-plated layer, a gold-plated layer or a silver-plated layer.
7. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The chip metal layer is a gold-tin alloy layer, a silver layer or a tin layer.
8. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The thickness of the anti-migration metal layer ranges from 0.005um to 2mm.
9. The integrated semiconductor stacking structure device according to claim 1, characterized in that: The thickness of the reflective layer ranges from 1 nm to 1 cm.