Integrated circuit chip layout structure system

Abstract

The utility model provides an integrated circuit chip layout structure system. The integrated circuit chip layout structure system comprises a lead carrier plate; the plurality of first metal bumps are arranged at the bottom of the wire carrier plate, a plurality of through holes are formed in the tops of the first metal bumps, a silicon intermediate plate is mounted at the top of the wire carrier plate through third metal bumps, a plurality of lines are arranged at the top of the silicon intermediate plate, and the first metal bumps are arranged at the bottom of the wire carrier plate. The top of the silicon intermediate plate is provided with a chip through a second metal bump, the bottom of the chip is provided with a heat insulation layer, the protective cover is arranged at the top of the wire carrier plate, and the top of the wire carrier plate is also provided with a plurality of circuits. According to the integrated circuit chip layout structure system provided by the utility model, through the design, a plurality of chips which need to be matched with each other can be integrated into one protective cover, pin welding is avoided, and the overall size is reduced and the applicability is increased by adopting bottom welding.

Description

Technical Field

[0001] The utility model relates to the field of integrated circuit chip layout, in particular to an integrated circuit chip layout structure system. Background Art

[0002] An integrated circuit is a miniature electronic device or component. Using a certain process, the transistors, resistors, capacitors, inductors and other components and wiring required in a circuit are interconnected together, made on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a tube shell to become a miniature structure with the required circuit function.

[0003] In the layout of conventional chips, several protective covers of different structures are usually used to meet the layout requirements of different contact settings and usage, and several wiring areas are formed on both sides and the front and back sides of the chip to complete the contact and circuit layout of the chip.

[0004] Through the above chip layout, if multiple chips need to be used in conjunction, the volume of the protective cover needs to be increased, thereby increasing the volume of the chip assembly and reducing applicability, which is not conducive to installation on a smaller circuit board.

[0005] Therefore, it is necessary to provide an integrated circuit chip layout structure system to solve the above technical problems. Utility Model Content

[0006] The utility model provides an integrated circuit chip layout structure system, which solves the problem that when the wiring areas of the chip are located on the four sides of the protective cover, the volume of the protective cover will increase when multiple chips are used in combination, which is not conducive to installation on a circuit board with a smaller volume and reduces applicability.

[0007] In order to solve the above technical problems, the integrated circuit chip layout structure system provided by the utility model includes: a conductor carrier;

[0008] A plurality of first metal bumps, wherein the plurality of first metal bumps are arranged at the bottom of the wire carrier, a plurality of through holes are opened at the top of the first metal bumps, a silicon interposer is installed at the top of the wire carrier through a third metal bump, a plurality of circuits are arranged at the top of the silicon interposer, a chip is installed at the top of the silicon interposer through a second metal bump, and a heat insulation layer is arranged at the bottom of the chip;

[0009] A protective cover is arranged on the top of the wire carrier, and a plurality of circuits are also arranged on the top of the wire carrier.

[0010] The second metal bump is a circuit connection that penetrates the insulation layer and the top of the silicon interposer. The circuits on the silicon interposer and the conductor carrier are chemically etched. The protective cover can be made of ceramic material or special high-temperature resistant plastic material.

[0011] Preferably, a hole is formed on the top of the thermal insulation layer so as to allow the second metal bump to pass through, and a plurality of through holes are also formed on the top of the silicon interposer.

[0012] Preferably, a photolithography plate is installed at the bottom of the protective cover, and the front and back sides of the wire carrier are provided with taking-out openings.

[0013] The photolithography plate is convenient for laser engraving on it.

[0014] Preferably, the bottom of the wire carrier plate is provided with limiting openings near the four corners, and the top of the inner wall of the limiting opening is provided with through openings.

[0015] The through opening passes through the wire carrier, and the limit opening is directional.

[0016] Preferably, the bottom of the protective cover is fixedly connected with connecting bolts at four corners, and the bottom ends of the connecting bolts are provided with welding blocks.

[0017] After the connecting pins are passed through the through openings and connected to the welding blocks, the protective cover can be installed on the top of the wire carrier.

[0018] Preferably, sealant is provided at positions near the four surfaces of the bottom of the protective cover, and the sealant is made of polyurethane material.

[0019] Compared with the related art, the integrated circuit chip layout structure system provided by the utility model has the following beneficial effects:

[0020] The utility model provides an integrated circuit chip layout structure system. In order to reduce the volume when multiple chips are used in combination, the front side of each chip is firstly welded with multiple second metal bumps facing downward, and the second metal bumps at the bottom of the chip are connected through the heat insulation layer and the circuit on the silicon interposer, and the silicon interposer is provided with multiple through holes. Multiple third metal bumps are also installed at the bottom of the silicon interposer, and the third metal bumps and the second metal bumps at the top of the silicon interposer are connected through circuits at positions where they need to be connected. After the silicon interposer is installed, it is only necessary to connect the third metal bumps at the bottom of the silicon interposer to a wire carrier with through holes and circuits, and then cover the wire carrier with a protective cover to protect the chip inside. When in use, it is only necessary to connect the first metal bump at the bottom of the wire carrier to the circuit board. Through this design, multiple chips that need to cooperate with each other can be integrated into a protective cover, avoiding the use of pin welding, and using bottom welding to reduce the overall volume and increase applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic structural diagram of a first embodiment of an integrated circuit chip layout structure system provided by the utility model;

[0022] Figure 2 A schematic diagram of the structure of a first metal bump is provided for the utility model;

[0023] Figure 3 Provided for the utility model Figure 2 An enlarged view of point A is shown;

[0024] Figure 4 A schematic diagram of the structure of the perforation is provided for the utility model;

[0025] Figure 5 A schematic diagram of the structure of the second embodiment of the integrated circuit chip layout structure system provided by the utility model

[0026] Figure 6 A structural schematic diagram of a welding block is provided for the utility model;

[0027] Figure 7 Provided for the utility model Figure 5 An enlarged view of point B is shown.

[0028] Numbers in the figure: 1. wire carrier, 2. taking port, 3. protective cover, 4. photolithography board, 5. first metal bump, 6. perforation, 7. chip, 8. thermal insulation layer, 9. second metal bump, 10. sealant, 11. third metal bump, 12. connecting bolt, 13. silicon interposer, 14. circuit, 15. through-hole, 16. limit port, 17. welding block. DETAILED DESCRIPTION

[0029] The utility model is further described below in conjunction with the accompanying drawings and implementation modes.

[0030] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 ,in, Figure 1 A schematic structural diagram of a first embodiment of an integrated circuit chip layout structure system provided by the utility model; Figure 2 A schematic diagram of the structure of a first metal bump is provided for the utility model; Figure 3 Provided for the utility model Figure 2 An enlarged view of point A is shown; Figure 4 The utility model provides a schematic diagram of the structure of the perforation. The integrated circuit chip layout structure system includes: a conductor carrier 1;

[0031] A plurality of first metal bumps 5, the plurality of first metal bumps 5 are arranged at the bottom of the wire carrier 1, a plurality of through holes 6 are opened at the top of the first metal bumps 5, a silicon interposer 13 is installed at the top of the wire carrier 1 through a third metal bump 11, a plurality of circuits 14 are arranged at the top of the silicon interposer 13, a chip 7 is installed at the top of the silicon interposer 13 through a second metal bump 9, and a heat insulation layer 8 is arranged at the bottom of the chip 7;

[0032] The protective cover 3 is arranged on the top of the wire carrier 1 , and a plurality of circuits 14 are also arranged on the top of the wire carrier 1 .

[0033] The second metal bump 9 is connected to the circuit 14 that penetrates the insulation layer 8 and the top of the silicon interposer 13. The circuit 14 on the silicon interposer 13 and the conductor carrier 1 is chemically etched. The protective cover 3 can be made of ceramic or special high-temperature resistant plastic material, and the insulation layer 8 can be made of ceramic.

[0034] The top of the thermal insulation layer 8 is provided with a hole through which the second metal bump 9 can pass, and the top of the silicon interposer 13 is also provided with a plurality of through holes 6 .

[0035] The top of the thermal insulation layer 8 is in contact with the bottom of the chip 7 .

[0036] A photolithography plate 4 is installed at the bottom of the protective cover 3, and a taking port 2 is opened on the front and back of the wire carrier 1.

[0037] The photolithography plate 4 is convenient for laser engraving thereon, and the chip 7 model can be engraved thereon.

[0038] The working principle of the integrated circuit chip layout structure system provided by the utility model is as follows:

[0039] First, the front side of each chip 7 faces downward and is welded with a plurality of second metal bumps 9, and the second metal bumps 9 at the bottom of the chip 7 are connected through the insulation layer 8 and the circuit on the silicon interposer 13, and a plurality of through holes 6 are opened on the silicon interposer 13. A plurality of third metal bumps 11 are also installed at the bottom of the silicon interposer 13, and the third metal bumps 11 and the second metal bumps 9 at the top of the silicon interposer 13 are connected through circuits 14 at the positions where they need to be connected. After the silicon interposer 13 is installed, it is only necessary to connect the third metal bumps 11 at the bottom of the silicon interposer 13 to the wire carrier 1 with the through holes 6 and the circuits 14, and then cover the protective cover 3 on the wire carrier 1 to protect the chip 7 inside. When in use, it is only necessary to connect the first metal bump 5 at the bottom of the wire carrier 1 to the circuit board.

[0040] Compared with the related art, the integrated circuit chip layout structure system provided by the utility model has the following beneficial effects:

[0041] In order to reduce the volume when multiple chips 7 are used in combination, first, the front side of each chip 7 is facing down and welded with multiple second metal bumps 9, and the second metal bumps 9 at the bottom of the chip 7 are connected through the insulation layer 8 and the circuit on the silicon interposer 13, and the silicon interposer 13 is provided with multiple through holes 6. A plurality of third metal bumps 11 are also installed at the bottom of the silicon interposer 13, and the third metal bumps 11 and the second metal bumps 9 at the top of the silicon interposer 13 are connected through circuits 14. After the silicon interposer 13 is installed, it is only necessary to connect the third metal bumps 11 at the bottom of the silicon interposer 13 with the wire carrier 1 with the through holes 6 and the circuits 14, and then cover the protective cover 3 on the wire carrier 1 to protect the chip 7 inside. When in use, it is only necessary to connect the first metal bump 5 at the bottom of the wire carrier 1 to the circuit board. Through this design, multiple chips 7 that need to cooperate with each other can be integrated into a protective cover, avoiding the use of pin welding. The use of bottom welding reduces the overall volume and increases applicability. Example

[0042] Please refer to Figure 5-Figure 6 - Figure 7 , Figure 5 A schematic diagram of the structure of the second embodiment of the integrated circuit chip layout structure system provided by the utility model Figure 6 A structural schematic diagram of a welding block is provided for the utility model; Figure 7 Provided for the utility model Figure 5 The enlarged view at B is shown. Based on the integrated circuit chip layout structure system provided by the first embodiment of the present application, the second embodiment of the present application proposes another integrated circuit chip layout structure system. The second embodiment is only a preferred method of the first embodiment, and the implementation of the second embodiment will not affect the independent implementation of the first embodiment.

[0043] Specifically, the difference of the integrated circuit chip layout structure system provided in the second embodiment of the present application is that the bottom of the wire carrier 1 is provided with limit openings 16 near the four corners, and the top of the inner wall of the limit opening 16 is provided with a through opening 15.

[0044] The through opening 15 passes through the wire carrier 1, the limiting opening 16 is directional, and the through opening 15 is cylindrical.

[0045] The bottom of the protective cover 3 is fixedly connected to connecting bolts 12 at four corners, and the bottom ends of the connecting bolts 12 are each provided with welding blocks 17 .

[0046] After the connecting bolt 12 passes through the through hole 15 and is connected to the welding block 17 , the protective cover 3 can be installed on the top of the wire carrier 1 .

[0047] Sealant 10 is provided at the bottom of the protective cover 3 near the four surfaces. The sealant 10 is made of polyurethane material.

[0048] The sealant 10 is used to adhere the bottom of the protective cover 3 to the wire carrier 1 .

[0049] Compared with the related art, the integrated circuit chip layout structure system provided by the utility model has the following beneficial effects:

[0050] In order to facilitate the removal of the protective cover 3 when the chip 7 fails, four metal connecting bolts 12 are installed at the bottom of the protective cover 3, and four limiting openings 16 are opened at the bottom of the wire carrier 1 near the four corners, and the top of the inner wall of the limiting opening 16 is opened with a through-hole 15 for allowing the metal connecting bolts 12 to pass through. During the installation process, it is only necessary to apply sealant 10 to the bottom of the protective cover 3, and then insert the four metal connecting bolts 12 into the inside of the through-hole 15, and then turn over the wire carrier 1 to connect the welding block 17 and the connecting bolt 12 by welding, and let the welding block 17 be located inside the limiting opening 16. After welding is completed, the installation of the protective cover 3 is completed. When disassembling, first heat and soften the sealant 10, and then melt the welding block 17 by welding, and then pull the protective cover 3 to let the metal connecting bolt 12 separate from the through-hole 15 to complete the removal of the protective cover 3. Through this design, the protective cover 3 can be quickly installed and disassembled without affecting the sealing of the protective cover 3.

[0051] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An integrated circuit chip layout structure system, characterized in that: include: Wire carrier board; A plurality of first metal bumps, wherein the plurality of first metal bumps are arranged at the bottom of the wire carrier, a plurality of through holes are opened at the top of the first metal bumps, a silicon interposer is installed at the top of the wire carrier through a third metal bump, a plurality of circuits are arranged at the top of the silicon interposer, a chip is installed at the top of the silicon interposer through a second metal bump, and a heat insulation layer is arranged at the bottom of the chip; A protective cover is arranged on the top of the wire carrier, and a plurality of circuits are also arranged on the top of the wire carrier.

2. The integrated circuit chip layout structure system according to claim 1, characterized in that: The top of the thermal insulation layer is provided with a hole through which the second metal bump can pass, and the top of the silicon interposer is also provided with a plurality of through holes.

3. The integrated circuit chip layout structure system according to claim 1, characterized in that: A photolithography plate is installed at the bottom of the protective cover, and taking openings are provided on the front and back of the wire carrier.

4. The integrated circuit chip layout structure system according to claim 1, characterized in that: The bottom of the wire carrier plate is provided with limiting openings near the four corners, and the top of the inner wall of the limiting opening is provided with through openings.

5. The integrated circuit chip layout structure system according to claim 1, characterized in that: The bottom of the protective cover is fixedly connected with connecting bolts at four corners, and the bottom ends of the connecting bolts are provided with welding blocks.

6. The integrated circuit chip layout structure system according to claim 1, characterized in that: Sealant is arranged at positions near the four surfaces of the bottom of the protective cover, and the sealant is made of polyurethane material.

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